Emerging Domain In Electronics Engineering

(KEC-101T/201T)

Unit-II
Bipolar Junction Transistor and Field
Effect Transistor

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 Unit - II Bipolar Junction Transistor and Field Effect Transistor

SYLLABUS
Bipolar Junction Transistor: Transistor Construction,
Operation, Amplification action. Common Base, Common
Emitter, Common Collector Configuration.

Field Effect Transistor: Construction and Characteristic of

JFETs. Transfer Characteristic. MOSFET (MOS) (Depletion and
Enhancement) Type, Transfer Characteristic.

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Name of Topics (Unit-II)
Bipolar Junction Transistor:
 Transistor Construction, Operation, Amplification action.
 Common Base, Common Emitter, Common Collector
Configuration.
Field Effect Transistor:
 Construction and Characteristic of JFETs. Transfer
Characteristic.
 MOSFET (MOS) (Depletion and Enhancement) Type, Transfer
Characteristic.
KEC- 101
Transistor
• Transistor is a device which transfers applied signal from one
type of resister to other type, For example signal can be
transferred from low resistor to high or from high resistor to
low resistor.
• “Transistor” (Transfer +resistor).
• Transistor is called bipolar device because its operation
depends on the interaction of majority and minority carrier
both.
Classification of Transistor

Different types and sizes

FET: Field Effect Transistor

JFET: Junction Field Effect Transistor
MOSFET: Metal Oxide Semiconductor Field
Effect Transistor
Construction of Transistor
n-p-n

p-n-p
• Emitter: It is the highest doping region in the transistor. It supplies
(emits) carrier to the base. It supplies electron to the base in n-p-n
and holes in p-n-p.
• Base: The middle part of transistor is called base. It is very thin and
lightly doped . So most of the carrier coming from emitter passes to
collector.
• Collector: Collector collect the carriers which are coming from
base. Doping of collector is heavier than base but less than
emitter.
Area profile: C > E > B
Doping profile: E > C > B
Mode or Working Regions of Transistor
• Transistor operates in three modes:
i) Active region:
• In active region emitter-base junction (JE) is forward biased and collector -base
junction (JC) is reverse biased. In this region transistor works as an amplifier.
ii) Saturation region:
• In this region emitter-base junction (JE) and collector -base junction (JC) are
forward biased. In this region transistor works as a closed switch.

iii) Cut-off region:

• In this region emitter-base junction (JE) and collector -base junction (JC) are
reverse biased. In this region transistor works as a open switch.
Operation of Transistor in Active Region
• To operate BJT in active region JEB (emitter base junction) must be
forward biased and JCB (collector base junction) must be reverse biased.
Operation of Transistor in Active Region
• JEB is forward biased by the battery VEE by which the depletion region will
decrease and a majority carrier flow will occur from emitter to base
giving current Imajority or IE.

• So, Here, IeE is current due to electrons of emitter region and IhB is
current due to holes in base region.
Operation of Transistor in Active Region
• In base region there is recombination between electrons and holes due
to which base current is obtained. As number of holes in base is very
small, base current is very small.
• JCB is reverse biased by VCC. So collector current is due to flow of minority
charge carriers from both sides of the junction. In base minority carriers
are electrons left after recombination and in collector minority carriers
are holes. So,
• Directions of all terminal currents are shown in figure and it is clear that,
Operation of Transistor in Active Region

• Directions of all terminal currents are shown in figure and it is clear that,
Transistor Configuration or Connection
• Transistor has three terminals emitter, base and collector. But we require four
terminals to connect the transistor in a circuit as an amplifier. Two for input and
two for output.

• This is achieved by making one terminal of transistor common to input and

output.

• So, transistor has three configurations based on the common terminal.

i) Common base configuration (CB)

ii)Common emitter configuration (CE)
iii) Common collector configuration (CC)
Common base configuration (CB)
• Input is applied between emitter and base
• Output is taken out from collector and base
• Base is common between input and output.
i) DC Current gain:
• It is the ratio of output current (IC) to the input current (IE).

IC
α=
IE

• Since IE > IC so value of α is less than 1

• Value of α ranges from .90 to .99

• So, no current gain is available in CB configuration.

Expression for Output Current
𝐈𝐂 = 𝐈𝐂 𝐌𝐚𝐣 + 𝐈𝐂𝐎
For CB ICO = ICBO ( Collecter to base current when emitter is openሻ
𝐒𝐨 𝐈𝐂 = 𝐈𝐂 𝐌𝐚𝐣 + 𝐈𝐂𝐁𝐎 … … … … 1

IC(Majሻ
but α =
IE
IC(Majሻ = αIE … … … … … … 2

Using 1 and 2

𝐈𝐂 = 𝛂𝐈𝐄 + 𝐈𝐂𝐁𝐎
Common Emitter Configuration (CE)
In this configuration input is applied between base and emitter while output is
taken out from collector and emitter. So, emitter of transistor is common to both
input and output.
i) DC Current gain:
• It is the ratio of output current (IC) to the input current (IB).
IC
β=
IB

• Since value of IB << IC. So β >>1. Therefore, current gain is available in CE

configuration

• Value of β varies from 20 to 500.

Expression for Output Current
𝐈𝐂 = 𝛂𝐈𝐄 + 𝐈𝐂𝐁𝐎 1
= 𝜷 + 1 … … … … … .2
𝑰𝑪 = 𝜶 𝑰𝑪 + 𝑰𝑩 + 𝐈𝐂𝐁𝐎 1−𝜶
[IE = IC + IB] Using equation 1 and 2
𝑰𝑪 = 𝜷𝑰𝑩 + 𝜷 + 1 𝑰𝑪𝑩𝑶
𝑰𝑪 = 𝜶𝑰𝑪 + 𝜶𝑰𝑩 + 𝐈𝐂𝐁𝐎
𝑰𝑪 = 𝜷𝑰𝑩 + 𝑰𝑪𝑬𝑶
𝑰𝑪 1 − 𝜶 = 𝜶𝑰𝑩 + 𝐈𝐂𝐁𝐎
𝜶 𝑰𝑪𝑩𝑶 Where ICEO: Collector to emitter current
𝑰𝑪 = 𝑰𝑩 + ………1 when base is open and ICEO is given by
1−𝜶 1−𝜶
𝜶
𝒃𝒖𝒕 =𝜷 𝑰𝑪𝑬𝑶 = 𝜷 + 1 𝑰𝑪𝑩𝑶
1−𝜶
𝜶
+1=𝜷+1
1−𝜶
Common Collector Configuration (CC)
• In this configuration input is applied between base and collector while output is
taken out from emitter and collector. So, collector of transistor is common to
both input and output.
DC current gain (γ):

• It is the ratio of output current (IE) to the input current (IB).

IE
γ=
IB

• Since value of IB << IR. So γ >>1. Therefore, current gain is available in CC

configuration. But voltage gain is not available in CC.
Early Effect or Base Width Modulation Effect
• In a transistor JE is forward biased so width of depletion layer is narrow. JC is
reverse biased so, width of depletion layer is wide. So, depletion layer at JE can
be neglected as compared to depletion layer at JC.
• At JC doping of collector is high as compare to base. Hence width of depletion
layer is more in base. So, we can neglect the depletion layer in collector.
• If VCB is increased then width of depletion
layer in base will increase. So, there is less
chance of recombination of electrons in base
and vice versa.
• Therefore, increase in VCB will increase IE, IC
but decrease IB.
• This is called Early effect or Base width
modulation effect.
Early Effect or Base Width Modulation Effect
• In active region JEB : Forward bias & JCB: Reverse Bias.
• Doping profile: DE> Dc> DB
• So, width of depletion region formed on E_B junction and C_B
junction is non uniform.
• At both the junctions major width of depletion region is towards
base. So, effective width of base is very small.
• On increasing VCB, effective width of base region further reduces,
this process is called Early Effect (named after its discoverer
James M. Early )or Base Width Modulation.
• On increasing VCB, IE & IC increases but IB decreases (Due to
reduction in base, possibility of recombination in this region
reduces)
• Thus α, β & γ increases.
Input V/I Characteristics of CB Configuration

• It is graph between input current (IE) and input voltage (VEB) at

constant output voltage (VCB). This graph is drawn for active region of
BJT.
Input V/I Characteristics of CB Configuration
• By keeping constant VCB, when forward bias at emitter base junction is increased then
graph between IB and VEB is similar to forward characteristics of pn junction diode. If
this graph is again drawn for some higher value of VCB a similar graph is obtained with
reduced knee voltage.
Output V/I Characteristics of CB Configuration

• It is graph between output current IC and output voltage VCE at constant

input current IE. This graph is drawn for all three operating regions of BJT.
• To draw the graph in active region equation of output current,
Output V/I Characteristics of CB Configuration

• Active Region: For given α and IE, IC is dependent only on I0 which is slightly

dependent on VCB. So, graph of active region is almost independent of VCB.

• Saturation Region: When the transistor is switched from active to

saturation region, a large change in collector current for very small forward
bias voltage at collector to base junction is obtained in negative direction.

• Cut-Off Region: When both the junctions are reverse biased, a very small
collector current is obtained which is close to horizontal axis.
Output V/I Characteristics of CB Configuration
 Input V/I Characteristics of CE Configuration

•It is graph between input current (IB) and input voltage (VBE) at constant output

voltage (VCE). This graph is drawn for active region of BJT.

•By keeping constant VCE, when forward bias at emitter base junction is increased then

graph between IE and VBE is similar to forward characteristics of pn junction diode.

 Input V/I Characteristics of CE Configuration
If this graph is again drawn for some higher value of VCE a similar graph is obtained with
increased knee voltage. This is due to reduction in IB on increasing reverse bias at
collector base junction.
Input V/I Characteristics of CE Configuration
 Output V/I Characteristics of CE Configuration
•It is graph between output current IC and output voltage VCE at constant input
current IB. This graph is drawn for all three operating regions of BJT.

•To draw the graph in active region equation of output current,

 Output V/I Characteristics of CE Configuration
Active Region: For given β and IB, IC is dependent on (β +1)I0 which is more
dependent on VCE than in case of CB configuration. So, graph of active region has
some slope showing change in IC on changing VCE.

Saturation region: When the transistor is switched from active to saturation region, a
large change in collector current for very small change in collector voltage is obtained
in negative direction.

Cut-Off Region: When both the junctions are reverse biased, a very small collector
current is obtained which is close to horizontal axis.
Output V/I Characteristics of CE Configuration
Output V/I Characteristics of CE Configuration
Relation between α and β
IC IC 1 1
α= 𝑎𝑛𝑑 β = = +1
IE IB 𝛼 𝛽

𝐼𝐸 = 𝐼𝐵 + 𝐼𝐶
1 1+β
=
Dividing both sides by IC 𝛼 β
𝐼𝐸 𝐼𝐵 + 𝐼𝐶 α + αβ = β
=
𝐼𝐶 𝐼𝐶
β 1−α = α

𝐼𝐸 𝐼𝐵 𝜶
= +1 𝜷=
𝐼𝐶 𝐼𝐶 1−𝜶
Comparison of Transistor Configuration or Connections
FET: Field Effect Transistor
JFET: Junction Field Effect Transistor

MOSFET: Metal Oxide Semiconductor Field Effect Transistor

Difference Between BJT and FET(JFET, MOSFET)
S.N BJT JFET

1 It is bipolar device i.e. operation It is unipolar device i.e. operation depends only
depends on majority and minority on majority carrier.
carrier both.
2 Current controlled device i.e. Voltage controlled device i.e. output is
output is controlled by current. controlled by voltage.
3 Input resistance is very low. Input resistance is very high.
4 Temperature dependent due to Temperature independent due to absence of
minority carriers. minority carriers.
5 Power consumption is high. Power consumption is low.
6 More noisy Less noisy
7 Cost is low. Cost is high
N- Channel JFET( Junction Field Effect Transistor)
Construction:
• A n-channel JFET have n type base.
• On both side of base two heavily
doped p regions are formed.
• So two p-n junction is formed
which are internally connected by a
gate terminal. Other two terminal
are drain and source.
• In JFET structure, the channel is uniformly doped and it
can be modeled as series combination of equal
resistances.
• If current is flowing from drain to source, the voltage at
upper part of the channel is higher than the lower part.
• So if we apply VDs > 0 and VGS 0, both pn junctions are
reverse biased and very high input impedance is
achieved.
• This reverse bias voltage is not uniform and decreases as
we move downwards.
• So, a non uniform depletion region is formed at junctions
which is wider in upper part than the lower part of the
channel.
 Working of n Channel JFET
Its working is divided in two parts:
(1) When VDS>0 and VGS=0
(2) When VDS>0 and VGS<0

1. When VDS>0 and VGS=0:

• Two pn junctions are reverse biased and biasing voltage is decreasing from
top to bottom. So depletion is more on upper part of the structure than
lower part.
• Electrons in channel move towards drain (positive terminal), so a current
ID from drain to source us obtained
• On increasing VDS, ID as well as reverse bias both increases
Working of n Channel JFET
Working of n Channel JFET
• At certain value of VDS, width of depletion layer become maximum and drain current
become constant. It is called pinch off condition
• VDS corresponding to pinch-off condition is called pinch off voltage (VP) and constant
drain current is denoted as IDSS.
• After VDS= VP, on increasing VDS, ID remains constant until reverse breakdown.
• This condition is shown in graph of ID vs VDS at VGS=0V.

(2) When VDS>0 and VGS<0

• Now pinch off condition arrives at lower values of VDS
• The magnitude of saturation current is also smaller than the magnitude at VGS=0V.
• This condition is shown graphically for different negative values of VGS
Working of n Channel JFET (Drain Characteristics)
 Output Characteristics (Drain Characteristics)
• It is graph between output current ID and output voltage VDS at constant
VGS. It can be explained from working of the structure discussed above.
• For smaller values of VDS, ID VD. So this region of the graph is called
ohmic or linear region.
• In ohmic region the slope of the graph is dependent on VGS. So FET can
be used as voltage controlled resistance.
• After pinch off condition the drain current become constant and this
region of the graph is called saturation region.
 Transfer Characteristics
• It is graph between output current ID and input voltage VGS.
• The relation between ID and VGS can be given as:

• Above equation is also known as Shockley’s equation.

• The transfer curve can be obtained using Shockley’s equation or from the
output characteristics.
Transfer Characteristics
 Transfer Characteristics
• Here two graphs are provided, with the vertical scaling in milliamperes
for each graph. One is a plot of ID versus VDS , while the other is ID versus
VGS .
• Using the drain characteristics on the right of the “y” axis, a horizontal
line can be drawn from the saturation region of the curve denoted VGS =0
V to the ID axis. The resulting current level for both graphs is IDSS.
• In a similar way for different values of VGS we can note constant values of
ID from output curve.
• By joining all these points curve obtained is called transfer curve.
Transfer characteristics (From Schokley Equation)

2
𝐕𝐆𝐒
𝐈𝐃 = 𝐈𝐃𝐒𝐒 1−
𝐕𝐏
• Let IDSS = 8 mA, VP = -4 V
a) VGS = 0V c) VGS = -2V
𝟐 𝟐
𝑽𝑮𝑺 −𝟐
𝑰𝑫 = 𝑰𝑫𝑺𝑺 𝟏− 𝑰𝑫 = 𝟖 𝟏 − = 𝟐 𝒎𝑨
𝑽𝑷 −𝟒
𝟐 d) VGS = -3V
𝟎
𝑰𝑫 = 𝟖 𝟏 − = 𝟖 𝒎𝑨 𝟐
−𝟒 −𝟑
𝑰𝑫 = 𝟖 𝟏 − = 𝟎. 𝟓 𝒎𝑨
−𝟒
b) VGS = -1V
𝟐 e)VGS = -4V
−𝟏
𝑰𝑫 = 𝟖 𝟏 − = 𝟒. 𝟓 𝒎𝑨 𝟐
−𝟒 −𝟒
𝑰𝑫 = 𝟖 𝟏 − = 𝟎 𝒎𝑨
−𝟒
P- Channel JFET( Junction Field Effect Transistor)
Construction:
• A p-channel JFET have p type
base.
• On both side of base two heavily
doped n region are formed.
• So, two p-n junctions are formed
which are internally connected by
a gate terminal. Other two terminal
are drain and source.
JFET as a Voltage Variable Resistance (VVR) or Voltage
Controlled Resistance
• JFET works as a variable resistance in ohmic
region. The resistance of JFET is given by: 𝒓 = 𝐫𝐎
𝐝 𝟐
𝐕𝐆𝐒
Where: 𝟏 −
𝐕𝐏
ro = 10 KΏ (Resistance at VGS = 0)
i) At VGS = 0
𝟏𝟎
𝐫𝐝 = 𝟐
= 𝟏𝟎𝐊Ώ
𝟎
𝟏−
−𝟒
ii) At VGS = -2
𝟏𝟎
𝐫𝐝 = 𝟐
= 𝟏𝟑. 𝟑𝟑𝐊Ώ
−𝟐
𝟏−
−𝟒

So JFET works as variable resistance or voltage-controlled resistance.

N-Channel Depletion Type MOSFET
Construction:
• n-channel depletion type MOSFET have
p-type base(substrate). Then two n region
are formed.
• A thin layer of Sio2 (Silicon di oxide) is
deposited. Drain and source are connected
with metallic contact.
• A n channel is formed between two n
regions. Gate is insulated from n-channel
by Sio2 layer. So, IG is zero.
 Operation:
• When VDS is increased more and more
electrons move from source to drain. So
current increases. A condition comes when
current becomes cuuent.
• This condition is called pinch-off condition.
The value of VDS which established this
condition is called pinch-off voltage (VP).
After pinch-off current becomes constant.
VDS = +ve and VGS = -ve

• If VGS is increased then holes in p-type

substrate moves towards the channel.
• So, recombination process occurs in channel.
So, pinch-off condition comes earlier and
pinch-off voltage decreases in parabolic
manner. This is called depletion mode.
 VDS = + ve and VGS = + ve
• If positive voltage is applied at gate then
electrons in p-type substrate move towards
the channel. So, number of electrons in
channel increases. This is called enhancement
mode.

Characteristics.
It has two types of characteristics.
i) Drain or output characteristics: It is the curve between drain current (ID) and drain to source
voltage (VDS), while gate to source voltage (VGS) should be constant.
ii) Transfer characteristics:
It is the curve between drain current (ID) and gate to source voltage (VGS), while drain to source
voltage (VDS) should be constant.
Drain or Output Characteristics
 Output Characteristics
(Drain Characteristics)
• It is graph between output current ID and output voltage VDS at constant
VGS. It can be explained from working of the structure discussed above.
• For smaller values of VDS, IDVD. So this region of the graph is called ohmic
or linear region.
• In ohmic region the slope of the graph is dependent on VGS. So MOSFET
can be used as voltage controlled resistance.
• After pinch off condition the drain current become constant and this
region of the graph is called saturation region.
Transfer Characteristics
• It is graph between output current ID and input voltage VGS.
• The relation between ID and VGS can be given as:

• Above equation is also known as Shockley’s equation.

• The transfer curve can be obtained using Shockley’s equation or from
the output characteristics.
Transfer Characteristics
Transfer Characteristics
• Here two graphs are provided, with the vertical scaling in
milliamperes for each graph. One is a plot of ID versus VDS , while the
other is ID versus VGS .
• Using the drain characteristics on the right of the “y” axis, a
horizontal line can be drawn from the saturation region of the curve
denoted VGS =0 V to the ID axis. The resulting current level for both
graphs is IDSS.
• In a similar way for different values of VGS we can note constant
values of ID from output curve.
• By joining all these points curve obtained is called transfer curve.
N-Channel Enhancement Type MOSFET
• n-channel Enhancement type MOSFET
has p type substrate.
• Then two n regions are formed, A thin
layer of Sio2 (Silicon die oxide) is
deposited.
• Drain and source are connected with the
help of metallic contact. There is no
channel between two n regions.
Operation:
i) VDS = + ve, VGS = 0
• If VDS is increased then no current
will flow because the is no channel
i.e. ID = 0

ii) VDS = + Ve , VGS = +Ve

• If positive voltage is applied at gate then
electron in p type moves towards the gate
and holes moves away from the gate. Till
2V no channel is formed. But after 2V
channel is formed. This 2V is called
threshold voltage (VT). If VGS is further
increased then ID continuously increases.
This is called enhancement MOSFET.
It has two types of characteristics.
i) Drain or output characteristics: It is the curve
between drain current (ID) and drain to source
voltage (VDS), while gate to source voltage (VGS)
should be constant.
ii)Transfer characteristics:
It is the curve between drain current (ID) and gate to
source voltage (VGS), while drain to source voltage
(VDS) should be constant.
Output Characteristics (Drain Characteristics)

• It is graph between output current ID and output voltage VDS at constant

VGS. It can be explained from working of the structure discussed above.
• For smaller values of VDS, ID ∝ VD. So this region of the graph is called
ohmic or linear region.
• In ohmic region the slope of the graph is dependent on VGS. So MOSFET
can be used as voltage controlled resistance.
• After pinch off condition the drain current become constant and this
region of the graph is called saturation region.
Output Characteristics (Drain Characteristics)
Transfer Characteristics
• It is graph between output current ID and input voltage VGS.
• The relation between ID and VGS can be given as:
ID = k(VGS – VT )2
• Here k is a constant dependent on the construction of device
• The transfer curve can be obtained using above equation or from the
output characteristics.
• Here VT is called threshold voltage. It is minimum positive voltage
required for n channel EMOSFET to start conduction through n channel.
Transfer Characteristics
Transfer Characteristics
• Here two graphs are provided, with the vertical scaling in
milliamperes for each graph. One is a plot of ID versus VDS , while the
other is ID versus VGS .
• Using the drain characteristics on the right of the “y” axis, a
horizontal line can be drawn from the saturation region of the curve
denoted VGS =0 V to the ID axis. The resulting current level for both
graphs is IDSS.
• In a similar way for different values of VGS we can note constant
values of ID from output curve.
• By joining all these points curve obtained is called transfer curve.
Comparison between EMOSFET & DMOSFET
IDSS (Drain to source saturation current)
• When VGS = 0 and VDS = VP then maximum drain
current flows in JFET. This maximum drain
current is called drain to source saturation current
(IDSS).

Pinch-off voltage.
• When VDS is increased more and holes move from source
to drain. So current increases and depletion layer also
increases. So, channel becomes narrower. If VDS is
further increased a condition comes when depletion
region touches each other. This condition is called pinch-
off condition. The value of VDS which established this
condition is called pinch-off voltage (VP). After pinch-off
current becomes constant.
JFET as a voltage variable resistance (VVR) or voltage controlled resistance
JFET works as a variable resistance in ii) At VGS = -2
ohmic region. The resistance of JFET is 𝟏𝟎
𝐫𝐝 = 𝟐
= 𝟏𝟑. 𝟑𝟑𝐊Ώ
given by: 𝟏−
−𝟐
−𝟒
𝐫𝐎
𝐫𝐝 = 𝟐 So JFET works as variable resistance or voltage-
𝐕𝐆𝐒
𝟏− 𝐕 controlled resistance.
𝐏

Where:
ro = 10 KΏ (Resistance at VGS = 0)
i) At VGS = 0
𝟏𝟎
𝐫𝐝 = 𝟐
= 𝟏𝟎𝐊Ώ
𝟎
𝟏−
−𝟒
Transconductance (gm) and Its Expression
• Transconductance (gm): It is defined the ratio
𝒅𝑰𝑫
of change in drain current (ΔID) and change 𝑩𝒖𝒕 𝒈𝒎 =
𝒅𝑽𝑮𝑺
in gate to source voltage (ΔVGS) at constant
drain to source voltage (VDS). 2𝑰𝑫𝑺𝑺 𝑽𝑮𝑺
• Unit of gm is Siemen. 𝑺0 𝒈𝒎 = − 1− … … … .2
𝑽𝑷 𝑽𝑷
𝜟𝑰𝑫
𝒈𝒎 = | 𝑽𝑫𝑺 = 𝑪𝒐𝒏𝒔𝒕𝒂𝒏𝒕
𝜟𝑽𝑮𝑺
𝒅𝑰𝑫 𝑽𝑮𝑺 𝑰𝑫
𝑭𝒓𝒐𝒎 𝒆𝒒𝒖𝒂𝒕𝒊𝒐𝒏 1 1− = …..3
= 𝑽𝑷 𝑰𝑫𝑺𝑺
𝒅𝑽𝑮𝑺
Expression for transconductance (gm):
From Shockley equation 2𝑰𝑫𝑺𝑺 𝑰𝑫
𝑼𝒔𝒊𝒏𝒈 2 𝒂𝒏𝒅 3 𝒈𝒎 = −
𝑽𝑮𝑺 𝟐 𝑽𝑷 𝑰𝑫𝑺𝑺
𝑰𝑫 = 𝑰𝑫𝑺𝑺 𝟏 − -----------1
𝑽𝑷

Differentiating equation 1 with respect to VGS

2
𝒅𝑰𝑫 𝑽𝑮𝑺 1 𝑔𝑚 = 𝐼 𝐼
= 𝑰𝑫𝑺𝑺 𝑿 2 1 − 𝑉𝑃 𝐷𝑆𝑆 𝐷
𝒅𝑽𝑮𝑺 𝑽𝑷 𝑽𝑷
Thank You

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