International Conference on Logistics Engineering, Management and Computer Science (LEMCS 2014)

LDPC Encoder Design and FPGA

Implementation in Deep Space
Communication
Lei Cheng Guangxia Li
Institute of Communication Engineering Institute of Communication Engineering
PLA University of Science and Technology PLA University of Science and Technology
Nanjing, China Nanjing, China

Hongpeng Zhu
Institute of Communication Engineering Lei Yang
PLA University of Science and Technology Institute of Communication Engineering
Nanjing, China PLA University of Science and Technology
Nanjing, China

Abstract—According to the requirements of deep space CCSDS 131.1-O-2 standard on deep space communication
communication channel coding and referring to the standard 2/3 rate. This paper is focused on solving the key in
parameters of Consultative Committee for Space Data achieving time throughput and resource consumption
Systems (CCSDS), a high rate LDPC code scheme set for problems. At the same time, the intrinsic link among
deep space communications is adopted.[1][2] Due to the Low CCSDS deep space communications standards for various
density parity check (LDPC) codes’ excellent error rate LDPC codes is taken into account. The scalability of
performance, it’s necessary for Field Programmable Gate coding is considered in the design as well.[4]
Array(FPGA) to achieve CCSDS-LDPC coding. In this
context, the serial encoding of CCSDS deep space II. THE CODEWORD CONSTRUCTION OF LDPC
communication standard (1536,1024) LDPC code is realized
on the Xilinx company's XC5VSX100 chip. More specifically, LDPC codeword include Gallager[7] construction
the details of the encoding process is shown in this context. method, Mackay construction method and PEG
This design can be applied to other rate of LDPC codec construction method based on random construction method,
based upon deep space communication standard which is set this construction method is to search check matrix by the
by CCSDS flexibly. development of a certain girth or distribution rules. Finite
geometry and algebra constructor portfolio construction
Keywords-Deep Space Communicatio;CCSDS;LDPC;FPGA
method based on Method.
Quasi-cyclic LDPC code actually belongs to Gallager
I. INTRODUCTION LDPC codes, but it is not a random column permutation.
In deep space communications, due to the dramatic Quasi-cyclic LDPC code is a class of constructor code
increase in communication distance, the loss of with low complexity encoding. Its complexity relate to the
communication signals’ propagation in free space is large, generation matrix. A codeword of quasi-cyclic code which
the signal to noise ratio of the received signal is very low cyclic shift p( p  1) times is still a codeword of the code.
and the signal strength handled by communication systems QC-LDPC can be structured by quasi-cyclic matrix, the
is extremely weak. Therefore, improving the power encoded code can be achieved by using a register, and the
efficiency of the system is one of the most important issues hardware implementation is easier than other LDPC.
needed to be considered when designing deep space CCSDS standard provide a QC-LDPC codeword which
communications systems. Channel coding is an effective used for deep space communications. The matrix H of
way to improve the power efficiency. At present, it can be LDPC codeword with each rate is as follows:
said that without the assistance of the efficient channel I M  1 
0M 0M IM 0M
coding, it is difficult to achieve deep space 
communications in low SNR condition.[3] H1/2   I M IM 0M IM  2   3   4 
 I M  5   6 0M  7   8 
The high rate LDPC codes is recommended in deep IM
space communication system by Consultative Committee
for Space Data Systems(CCSDS). In 2010, the LDPC  0M 0M | 
codes was used in China's lunar exploration system, H 2/3 
  9  10  11 IM | H1/2 
‘Chang-e II’. It is first time that the LDPC codes is applied
to the field of deep space exploration.  IM 12  13  14 | 
This paper discuss in detail the design and
implementation of LDPC codes by FPGA (Field
Programmable Gate Array). The discussion is based on

© 2014. The authors - Published by Atlantis Press 343

  0M 0M |  III. LDPC CODING ALGORITHM
H 3/4 
 15  16  17 IM | H 2/3  Richardson proposed an efficient coding method for
randomly constructed codes, which can effectively solve
 IM 18  19   20 |  computational problem, the core idea of the algorithm is
In this paper, LDPC codeword is the QC-LDPC code to assume M  N dimensional random constructed parity
CCSDS 131.1-O-2 protocol, 1536 bits of the code length, check matrix transformation through the ranks, with the
1024 bits of information length, rate 2/3, sub-matrix size is following changes to the structure of the approximate
256 × 256, M is 256. A parity check matrix of the LDPC lower triangular matrix form. As shown in FIG.
code is configured in H 2/3 above.[1]
In H 2/3 , 0256 is the zero matrix of 256 × 256, I 256 is
the unit matrix of 256 × 256.  k is a permutation matrix
of 256 × 256, its i-th row is a column, and the others are 0,
the value of  k (i ) can be get in the follow.
 k (i)  64   k  i / 64  mod 4   k  i / 64   i  mod 64
Figure 1. The structure of the approximate lower triangular matrix

The values of k

and k is in the following table。
The size of each sub-matrix of A respectively
is (m  g )  (n  m) , B is (m  g )  g ,C is g  (n  m) , D
 k AND k
TABLE I. THE DESCRIPTION OF
is g  g . Codeword set C  (s, p1 , p2 ) , where S is the
k k k (0) k (1) k (2) k (3) information bit, parity bit sequence represented p1 and p2
1 3 59 0 0 0 together. p1 contains g bits, p2 m-g bits.
2 0 18 32 46 44 Switch the rows and columns of the matrix, the
3 1 52 21 45 51 elements do not change, therefore, the converted
4 2 23 36 27 12 approximate lower triangular matrix remains the sparsity.
5 2 11 30 48 15 Guarantee transformation T is full rank, the diagonal
6 3 7 29 37 12 elements of T are all "1”. Multiply left the matrix of the
transformed with matrix
7 0 22 44 41 4
 I 0
8 1 25 29 13 7   ET 1 I 
9 0 27 39 9 2  
10 1 30 14 49 30 You can get:
11 2 43 22 36 53  I 0  A B T   A B T
  ET 1 I  C D E     ET 1 A  C  ET 1B  D 0 
12 0 14 15 10 23     
13 2 46 48 11 29 According to HC T
 0 , you can get the following two
14 3 62 55 18 37 equations:
In this paper, H matrix can be obtained by calculate:
 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 59 
 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 1 1

 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 1
 
 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 
 27 30 43 1 0 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 18 52 23 1
 
1 39 14 22 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
H  
0 0 0 0 32 21 36 
36 1 9 49 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 0 1 27 1 46 45 
 
 30 53 1 2 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 0 51 12 1 44 
0 1 1 1 14 1 46 62 0 1 1 1 1 1 11 7 1 1 1 1 22 25 1 1 0 1 1 1
 
 1 0 1 1 55 15 1 48 1 0 1 1 29 1 1 30 1 1 1 1 1 44 29 1 1 0 1 1
 
 1 1 0 1 11 18 10 1 1 1 0 1 48 37 1 1 1 1 1 1 1 1 41 13 1 1 0 1
 1 1 1 0 1 29 37 23 1 1 1 0 1 15 12 1 1 1 1 1 7 1 1 4 1 1 1 0 
In the encoder, frame is the unit of information. The As  Bp  Tp  0
T T
1
T
2
frame length of the input information is 1024 bits. When
the coding is completed, the frame length is 1536 bits. ( ET A  C )sT  ( ET 1B  D) p1T  0
1

If the matrix  ET 1B  D is invertible, we can

obtain:

344
 p1T  ( ET 1B  D)1 ( ET 1 A  C )sT only need to store the first row, the use of circular shift
register can get to the next line.
First p1T calculate, then according to the following
The design of IP core
formula, p2T can be calculated. In this paper the program FPGA use slice resource to
As for matrix computation takes too many resources save RAM resources. Therefore, only one RAM is used in
in the FPGA, especially matrix inversion, so it is difficult this paper, for writing the cyclic shift matrix.
to realize the algorithm in hardware. In this paper, the From the data sheet of IP core, the type of data file formats
design of IP core will solve the problem. The inversion is .coe, contains two parameters:
results will be stored in RAM, which can save a lot of (1), memory_initialization_radix, namely vector base,
resources. which can be 2,10,16, behalf the data of binary, decimal,
hexadecimal , we use a hex ;
In this paper we use the encoding method as follows:
(2), memory_initialization_vector, initialization data based
a) H is a matrix of size 3M  7M . The matrix H is on vector. Among them, the number of vectors should be
divided into two portions P and Q, where P’s consistent with the generator ROM size of IP core.
size is 3M  3M , Q’s size is 3M  4M .M is 256. Based on the generated matrix W, the data depth is
b) W is a matrix of size 4M  3M . 128.
c) G matrix composed by the matrix W and the unit Interface block diagram of the encoder is shown in
matrix. G=  I 4 M W  the following FIG. Encoder 1024 information bits to
generate encoded 1536 bits. The encoder uses a systematic
IV. LDPC CODE ENCODER DESIGN code, the first 1024 bits of information encoded are the
same of the input bits, the next 512 bits are the parity bit.
The following brief analysis the structure of the
encoder. From the figure, we may find the structure do Clk Fd_out
parity calculations by using cyclic shift register[5].
a) Initially, first row of G matrix were loaded in 2M/m Rst
Rdy
shift registers by size of m = M/4, then phase the Fd_i
value of the register and the input bit, put the results n Dout
LDPC Encoder
into a 2M wide parity bit register. ND
Rfd
b) Put in the twice bit, the 2M/m shift registers cycle
one shift, then phase with the current input bit, XOR Din
the results and data in the parity bit register, and then
put the results into the 2M wide parity bit register.
c) When shift M/4 times, reload the first line value of
the second matrices, repeat the above operations. Figure 3. Interface block diagram of the encoder
When coded bits are fully put in, parity bits are
generated, so the coding structure works with high Below is the encoder timing diagram:
1024 Clks
throughput.
The encoder structure may be achieved by using a Clk
simple shift register, [6] the structure shown in the Rst

following FIG. ND
Fd_i
n
Din

RFD

Rdy

Fd_out

Dout
1536 Clks

Figure 4. the encoder timing diagram

V. FPGA IMPLEMENTATION RESULTS

Figure 2. The encoder structure
We achieve the CCSDS standard LDPC encoder On
The encoding algorithm based on a generator matrix: the XC6SLX100 chip of Xilinx company. The resource
c  S  G  S  ( I | B)  (S | S  B) consumption of encoder shown in the table:
Where S is the input information bits, matrix I is the
unit matrix, matrix B corresponding to the cyclic shift
section of generator matrix G. when doing multiplication
between vector and non-sparse matrix B, B can be split
into cyclic shift matrix for computing, storage array rotate

345
 TABLE II. DEVICE UTILIZATION SUMMARY QC-LDPC encoder which is suitable for deep space
communications CCSDS standards proposed[6][10]. It is
Device Utilization Summary (estimated shown in Section 1 that the structures of standard other
[-]
values) rate’s H matrix of LDPC and 2/3 rate’s H matrix have high
Logic Utilization Used Available Utilization consistency. Therefore, each sub-module and interleaved
iterative structure in this design can be easily extended to
Number of Slice Registers 2660 126576 2% the implementations of other rate LDPC[8].
Comprehensive results show that: in the case of small foot
Number of Slice LUTs 1257 63288 1% print, the encoder can achieve higher data throughput.
Number of fully used Thus it lays the foundation of the practical application of
1081 2836 38% LDPC codes[1]. The implementation structure discussed in
LUT-FF pairs
this article has a good engineering application in terms of
Number of bonded IOBs 9 326 2% both performance and resource consumption. As a result, it
Number of Block has a better prospect for the application. These aspects
1 268 0% provide the basis of LDPC codes’ application in deep
RAM/FIFO
space communications[10].
Number of
1 16 6%
BUFG/BUFGCTRLs REFERENCES
[1] CCSDS. Low density parity check codes for use in near-earth and
deep space applications [S]. CCSDS 131.1-O-2, Orange Book,
Partial results of the encoder operation shown in the FIG . Washington DC, USA, 2007.
[2] Klinc D, Ha J, McLaughlin S W, et al. LDPC codes for the
Gaussian wiretap channel[J]. Information Forensics and Security,
IEEE Transactions on, 2011, 6(3): 532-540.
[3] Pusane A E, Smarandache R, Vontobel P O, et al. Deriving good
LDPC convolutional codes from LDPC block codes[J].
Information Theory, IEEE Transactions on, 2011, 57(2): 835-857.
[4] Chen X, Kang J, Lin S, et al. Accelerating FPGA-based emulation
of quasi-cyclic LDPC codes with vector
processing[C]//Proceedings of the Conference on Design,
Automation and Test in Europe. European Design and Automation
Association, 2009: 1530-1535.
[5] Smarandache R, Vontobel P O. Quasi-cyclic LDPC codes:
Influence of proto-and Tanner-graph structure on minimum
Hamming distance upper bounds[J]. Information Theory, IEEE
Transactions on, 2012, 58(2): 585-607.
[6] Wang Z, Cui Z. Low-complexity high-speed decoder design for
quasi-cyclic LDPC codes[J]. Very Large Scale Integration (VLSI)
Figure 5. Partial results of the encoder operation Systems, IEEE Transactions on, 2007, 15(1): 104-114.
[7] GALLAGER R G． Low Density Parity Check Codes[J] ． IRE
Wherein the input information bits is Din, Dout is the Transaction on Information Theory，1962，8(1)：21—28．
output from the information bits. Encoder implemented [8] Darabiha A，carusone A c，Kschischang F R． Block-Interlaced
coding delay is : the first one encoder output coded bits LDPC Decoder with Reduced Interconnect Comple xity[J]．1EEE
delayed 16 clock cycles than the input first one ansactions on circuits and systems II，2008
information bit. [9] MacKay DJ c ． Good Error-Correcting Codes Based on Very
Throughput is calculated as follow: sparse Mat rices[J]．IEEE Transactions on Information Theory，
Throughput=(nLDPC/Cp)×fmax 1999,45(2):399—431
Where, fmax is the maximum operating frequency of the [10] Andrews K，Dolinar S，Divsalar D，et a1． Design of Low
encoder which can be achieved, nLDPC is the number of Density Parity Check(LDPC)Codes for Deep Space Applications.
Pasadena IPN,2004
information bits of one frame of the LDPC codes, Cp is the
number of the main encoder clock cycles to complete a
frame of encoded data.
The encoder can reach a maximum operating
frequency of 155MHz. For a coded frame, from the first
input data to the last encoded data, 1553 cycles are needed,
the value of Cp is 1553. The number of information bits is
1024, the throughput is 102.2 Mbps. Assuming the encoder
working frequency of 100MHz, the throughput frequency
of the encoder can achieve 65.9Mbps.
VI. CONCLUSION
The specific cyclic symmetry features makes it easier
for QC-LDPC codes to implement on FPGA. This paper
take (1536,1024) LDPC code for example, considering
high-speed , high efficiency , performance, portability and
other factors, to achieve a kind of realization structure of

346