Name: Aryan Bhadhrecha

Id: 2020UEC1570
Experiment - 1
Aim: To design layout of CMOS invertor using MOS generator vary the width and length of
NMOS and PMOS and do the simulation. Compare the static and transient characteristics of
three inverters

Software Used: Microwind (90nm)

Theory:
The inverter is universally accepted as the most basic logic gate doing a Boolean operation on a
single input variable.

The NMOS transistor is connected at the drain (D) & gate (G) terminals, a voltage supply
(VDD) is connected at the source terminal of PMOS & a GND terminal is connected at the
source terminal of NMOS. Input voltage (Vin) is connected to both the gate terminals of
transistors & output voltage (Vout) is connected to the drain (D) terminals of the transistor.
Analysis & Observations:

Circuit Connection:
 Name: Aryan Bhadhrecha
Id: 2020UEC1570
1. Wn = 0.1um, Wp = 0.2um and L = 0.1um (Wp > Wn)

DC Analysis:

Transient Analysis:

2. Wn = 0.2um, Wp = 0.2um and L = 0.1um (Wn = Wp) DC Analysis:

 Name: Aryan Bhadhrecha
Id: 2020UEC1570
Transient Analysis:

3. Wn = 0.4um, Wp = 0.2um and L = 0.1um (Wn = 2*Wp)

DC Analysis:

Transient Analysis:

Result:
Thus, the Analysis explains that for Wp:Wn = 2:1, there is a balanced rise and fall output time.
 Name: Aryan Bhadhrecha
Id: 2020UEC1570
Experiment - 2
Aim: To design layout of NAND gate using MOS generator and simulate it

Software used: Microwind (90nm)

Theory:

For two input NAND gate, if A and B are the inputs then its output Y = (A.B)’.
In NMOS network when we have AND operation between the two variables, then two NMOS
transistors will get connected in series. And the output will be complemented of it.

The PMOS network is dual of the NMOS network. In the NMOS network, if two transistors
are connected in series then in the PMOS network, the two PMOS transistors will get connected
in parallel.

Case1 : VA - Low & VB - Low

As VA and VB both are low, both the pMOS will be ON and both the nMOS will be OFF. So
the output Vout will get two paths through two ON pMOS to get connected with Vdd. The
output will be charged to the Vdd level. The output line will not get any path to the GND as
both the nMOS are off. So, there is no path through which the output line can discharge. The
output line will maintain the voltage level at Vdd; so, High.
 Name: Aryan Bhadhrecha
Id: 2020UEC1570
Case-2: VA - Low & VB - High

VA – Low: pMOS1 – ON; nMOS1 – OFF

VB – High: pMOS2 – OFF; nMOS2 – ON

pMOS1 and pMOS2 are in parallel. Though pMOS2 is OFF, still the output line will get a path
through pMOS1 to get connected with Vdd. nMOS1 and nMOS2 are in series. As nMOS1 is
OFF, so Vout will not be able to find a path to GND to get discharged. This in turn results the
Vout to be maintained at the level of Vdd; so, High.
Case3: VA - High & VB - Low

VA – High: pMOS1 – OFF; nMOS1 – ON

VB – Low: pMOS2 – ON; nMOS2 – OFF

The explanation is similar as case-2. Vout level will be High.

Case4: VA - High & VB - High

VA – High: pMOS1 – OFF; nMOS1 – ON

VB – High: pMOS2 – OFF; nMOS2 – ON

In this case, both the pMOS are OFF. So, Vout will not find any path to get connected with Vdd.
As both the nMOS are ON, the series connected nMOS will create a path from Vout to GND.
Since, the path to ground is established, Vout will be discharged; so, Low.

Analysis:

Circuit Connection:
 Name: VATSALYA SAGRAYA
Id: 2020UEC1198

Result:

Thus, we have designed the layout of 2-input NAND gate using MOS generator and simulated
the transient analysis.
 Name: VATSALYA SAGRAYA
Id: 2020UEC1198

Experiment - 3
Aim: To design layout of NOR gate using MOS generator and simulate it

Software used: Microwind (90nm)

Theory:

In CMOS design, the NOR gate consists of two nMOS in parallel connected to two pMOS in
series. The schematic diagram of the CMOS NOR cell is reported below. The nMOS in parallel
tie the output to the ground if either A or B are at 1. When both A and B are at 0, the nMOS
path is cut, but the two pMOS devices in series tie the output to the supply VDD.
Analysis:
Circuit Connection:
 Name: VATSALYA SAGRAYA
Id: 2020UEC1198

Result:

Thus, we have designed the layout of 2-input NOR gate using MOS generator and simulated
the transient characteristics.
 Name: VATSALYA SAGRAYA
Id: 2020UEC1198

Experiment – 4
Aim: To design layout of XOR gate using MOS generator and simulate it

Software Used: Microwind (90nm)

Theory:

In an XOR circuit, the output is a logic 1 when one and only one input is a logic 1. Hence the
output is logic 0 when both inputs are logic 1 or logic 0 simultaneously.
Analysis:

Circuit Connection:
 Name: VATSALYA SAGRAYA
Id: 2020UEC1198

Result:

Thus, we have designed the layout of 2-input XOR gate using MOS generator and simulated
the transient characteristics of the logic gate.
 Name: VATSALYA SAGRAYA
Id: 2020UEC1198

Experiment – 5
Aim: To design layout of XNOR gate using MOS generator and simulate it

Software Used: Microwind (90nm)

Theory:

Complementing the output of an XOR gate, we get the XNOR gate. Since the output is logic 1
for equal inputs, this function is also called the equivalence function.
Analysis:

Circuit Connection:
 Name: VATSALYA SAGRAYA
Id: 2020UEC1198

Result:

Thus, we have designed the layout of 2-input XNOR gate using MOS generator and simulated
the transient characteristics of the logic gate.
 Name: VATSALYA SAGRAYA
Id: 2020UEC1198
Experiment – 6
Aim: To design layout of Half Adder using MOS generator and simulate it
Software Used: Microwind (90nm)

Theory:

Half Adder is a digital circuit to calculate the arithmetic binary addition of two single-bit
numbers. It is a circuit with two inputs and two outputs.
For two single-bit binary numbers A and B, half adder produces two single-bit binary outputs
S and C, where S is the Sum and C is the carry. The sum is for the least significant bit (LSB)
and carry is for the most significant bit (MSB).

Analysis:

Circuit Connection:
 Name: VATSALYA SAGRAYA
Id: 2020UEC1198

Result:

Thus, we have designed the layout of Half Adder using MOS generator and simulated the
transient characteristics.
 Name: VATSALYA SAGRAYA
Id: 2020UEC1198
Experiment – 7
Aim: To design layout of Full Adder using MOS generator and simulate it

Software Used: Microwind (90nm)

Theory:

The half adder is used to add only two numbers. To overcome this problem, the full adder was
developed. The full adder is used to add three 1-bit binary numbers A, B, and carry C. The full
adder has three input states and two output states i.e., sum and carry.

The above block diagram describes the construction of the Full adder circuit. In the above
circuit, there are two half adder circuits that are combined using the OR gate. The first half
adder has two single-bit binary inputs A and B. As we know that, the half adder produces two
outputs, i.e., Sum and Carry. The 'Sum' output of the first adder will be the first input of the
second half adder, and the 'Carry' output of the first adder will be the second input of the second
half adder. The second half adder will again provide 'Sum' and 'Carry'. The final outcome of
the Full adder circuit is the 'Sum' bit. In order to find the final output of the 'Carry', we provide
the 'Carry' output of the first and the second adder into the OR gate. The outcome of the OR
gate will be the final carry out of the full adder circuit.
The MSB is represented by the final 'Carry' bit.

The full adder logic circuit can be constructed using the 'AND' and the 'XOR' gate with an OR
gate.

Analysis:

Circuit Connection:
 Name: VATSALYA SAGRAYA
Id: 2020UEC1198

Transient Analysis :

Result:

Thus, we have designed the layout of Full Adder using MOS generator and simulated the
transient characteristics.
 Name: VATSALYA SAGRAYA
Id: 2020UEC1198

Experiment – 8
Aim: To design layout of Common Source Amplifier using MOS generator and simulate it

Software Used: Microwind (90nm)

Theory:

In a common-source (CS) amplifier, the input signal is applied to the gate and the output signal
is taken from the drain. The amplifier has higher input resistance and lower gain than the
equivalent CE amplifier.
The ac voltage gain of this circuit is Vout=Vin, where Vin=Vgs and Vout=Vds. The voltage
gain expression is, therefore,

Av = Vds/Vgs

From the equivalent circuit, Vds = IdRd

and from the definition of transconductance, gm = Id/Vgs,
Substituting the two preceding expressions into the equation for voltage gain yields

Av=gm Rd

The bandwidth (also called the 3 dB frequency) is the frequency where the signal drops to 1/
√2 of its low-frequency value. (In decibels, dB(√2) = 3.01 dB). A reduction to 1/ √2 occurs
when ωCM RA = 1, making the input signal at this value of ω (call this value ω3 dB, say) vG
= VA / (1+j). The magnitude of (1+j) = √2. As a result, the 3 dB frequency f3 dB = ω3 dB / (2π)
is:
 Name: VATSALYA SAGRAYA
Id: 2020UEC1198
Analysis:

Circuit Connection:

Transient Analysis :
 Name: VATSALYA SAGRAYA
Id: 2020UEC1198

Result:

Thus, we have designed the layout of Common Source (CS) Amplifier using MOS generator
and simulated the transient characteristics.
 Name: VATSALYA SAGRAYA
Id: 2020UEC1198

Experiment – 9
Aim: To design layout of Differential Amplifier using MOS generator and simulate it

Software Used: Microwind (90nm)

Theory:

A differential amplifier (also known as a difference amplifier or op-amp subtractor) is a type of

electronic amplifier that amplifies the difference between two input voltages but suppresses any
voltage common to the two inputs. A differential amplifier is an analog circuit with two inputs
(V1 and V2) and one output (V0) in which the output is ideally proportional to the difference
between the two voltages.
The formula for a simple differential amplifier can be expressed:
Differential Amplifier formula

Where
V0 is the output voltage
V1 and V2 are the input voltages
Ad is the gain of the amplifier (i.e. the differential amplifier gain)
 Name: VATSALYA SAGRAYA
Id: 2020UEC1198

Analysis:

Circuit Connection:

Transient Analysis :
 Name: VATSALYA SAGRAYA
Id: 2020UEC1198

Result:

Thus, we have designed the layout of Differential Amplifier using MOS generator and
simulated the transient characteristics.