INDEX

Name- Aryan Bhadhrecha Branch-ECE

Subject-system Design Lab College ID-2020uec1570

Semester-VIII Year-2024

Sr.No Name Of Topic Page No.

1 To design Cmos inverter and simulate it 2

2 To design Nand Gate using CMOS 5

generator and simulate it

3 To design Nor Gate using CMOS generator 8

and simulate it

4 To design Xor Gate using CMOS generator 10

and simulate it

5 To design Xnor Gate using CMOS 13

generator and simulate it

6 To design Half Adder using CMOS 16

generator and simulate it

7 To design Full Adder using CMOS 18

generator and simulate it

8 To design CS Amplifier using CMOS 20

generator and simulate it

9 To design Differential Amplifier using 23

CMOS generator and simulate it

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 Experiment - 1
Aim: To design layout of CMOS inverter using MOS generator, vary the width and
length of NMOS and PMOS and do the simulation.
Software Used: Microwind (90nm)
Theory: The inverter is universally accepted as the most basic logic gate doing a Boolean
operaƟon on a single input variable.

The NMOS transistor is connected at the drain (D) & gate (G) terminals, a voltage supply
(VDD) is connected at the source terminal of PMOS & a GND terminal is connected at
the source terminal of NMOS. Input voltage (Vin) is connected to both the gate terminals
of transistors & output voltage (Vout) is connected to the drain (D) terminals of the
transistor
Layout Connection and Output:

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 Result :Thus, the Analysis explains that for Wp:Wn = 2:1, there is a balanced rise and
fall output time.

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 Experiment - 2
Aim: To design layout of NAND gate using CMOS generator and simulate it
Software Used: Microwind (90nm)
Theory:

For two input NAND gates, if A and B are the inputs then its output Y = (A.B)’. In
NMOS network when we have AND operaƟon between the two variables, then two
NMOS transistors will get connected in series. And the output will be complemented of
it. The PMOS network is dual of the NMOS network. In the NMOS network, if two
transistors are connected in series then in the PMOS network, the two PMOS transistors
will get connected in parallel.
Case1 : VA - Low & VB - Low
As VA and VB both are low, both the pMOS will be ON and both the nMOS will be OFF.
So the output Vout will get two paths through two ON pMOS to get connected with Vdd.
The output will be charged to the Vdd level. The output line will not get any path to the
GND as both the nMOS are off. So, there is no path through which the output line can
discharge. The output line will maintain the voltage level at Vdd; so, High.
Case-2: VA - Low & VB - High

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 VA – Low: pMOS1 – ON; nMOS1 – OFF
VB – High: pMOS2 – OFF; nMOS2 – ON
pMOS1 and pMOS2 are in parallel. Though pMOS2 is OFF, sƟll the output line will get
a path through pMOS1 to get connected with Vdd. nMOS1 and nMOS2 are in series. As
nMOS1 is OFF, so Vout will not be able to find a path to GND to get discharged. This in
turn results the Vout to be maintained at the level of Vdd; so, High.
Case3: VA - High & VB - Low
VA – High: pMOS1 – OFF; nMOS1 – ON
VB – Low: pMOS2 – ON; nMOS2 – OFF
The explanation is similar to case-2. Output level will be High.
Case4: VA - High & VB - High
VA – High: pMOS1 – OFF; nMOS1 – ON
VB – High: pMOS2 – OFF; nMOS2 – ON
In this case, both the pMOS are OFF. So, Vout will not find any path to get connected
with Vdd. As both the nMOS are ON, the series connected nMOS will create a path from
Vout to GND. Since, the path to ground is established, Vout will be discharged; so, Low.
Layout Connection and Output:

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 Result :Thus, we have designed the layout of 2-input NAND gate using CMOS generator
and simulated the transient analysis.

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 Experiment - 3
Aim: To design layout of NOR gate using CMOS generator and simulate it
Software Used: Microwind (90nm)
Theory:

In CMOS design, the NOR gate consists of two nMOS in parallel connected to two
pMOS in series. The schematic diagram of the CMOS NOR cell is reported below. The
nMOS in parallel the the output to the ground if either A or B are at 1. When both A and
B are at 0, the nMOS path is cut, but the two pMOS devices in series the the output to the
supply VDD.
Layout Connection and Output:

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 Result : Thus, we have designed the layout of 2-input NOR gate using CMOS generator
and simulated the transient characteristics.

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 Experiment - 4
Aim: To design layout of XOR gate using CMOS generator and simulate it
Software Used: Microwind (90nm)
Theory:

The design of an XOR gate using CMOS involves using both NMOS and PMOS
transistors to ensure that the gate operates efficiently in both the pull-up and pull-down
network configurations.CMOS technology is a common task in digital circuit design,
crucial for ensuring minimal power consumption and high noise immunity. XOR
(exclusive OR) gates are fundamental components used in various applications, including
arithmetic circuits and digital signal processing. The XOR gate outputs a high signal, or
logical '1', only when the inputs are at opposite logic levels; otherwise, it outputs a low
signal, or logical '0'.

Layout Connection and Output:

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 Transient Analysis

Result : Thus, we have designed the layout of 2-input XOR gate using CMOS generator
and simulated the transient characteristics.

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 Experiment - 5
Aim: To design layout of X-NOR gate using CMOS generator and simulate it
Software Used: Microwind (90nm)
Theory:

CMOS circuits use both PMOS and NMOS transistors to achieve the desired logic
functions. PMOS transistors conduct when their input is low (0), and NMOS transistors
conduct when their input is high (1).Designing an XNOR gate using CMOS technology
involves creating a circuit that outputs a true (logical high) signal only when both of its
inputs are either both true or both false. The circuit should provide a false (logical low)
output when the inputs differ.
Layout Connection and Output:

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 Transient Analysis

Result : Thus, we have designed the layout of 2-input XNOR gate using CMOS
generator and simulated the transient characteristics.

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 Experiment - 6
Aim: To design layout of Half-Adder gate using CMOS generator and simulate it
Software Used: Microwind (90nm)
Theory:

Half Adder is a digital circuit to calculate the arithmetic binary addition of two single-bit
numbers. It is a circuit with two inputs and two outputs. For two single-bit binary
numbers A and B, half adder produces two single-bit binary outputs S and C, where S is
the Sum and C is the carry. The sum is for the least significant bit (LSB) and carry is for
the most significant bit (MSB).
Layout Connection and Output:

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 Transient Analysis

Result : Thus, we have designed the layout of 2-input Half Adder gate using CMOS
generator and simulated the transient characteristics of sum and carry.

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 Experiment - 7
Aim: To design layout of Full-Adder gate using CMOS generator and simulate it
Software Used: Microwind (90nm)
Theory:

The half adder is used to add only two numbers. To overcome this problem, the full adder
was developed. The full adder is used to add three 1-bit binary numbers A, B, and carry
C. The full adder has three input states and two output states i.e., sum and carry. The
above block diagram describes the construction of the Full adder circuit. In the above
circuit, there are two half adder circuits that are combined using the OR gate. The first
half adder has two single-bit binary inputs A and B. As we know that, the half adder
produces two outputs, i.e., Sum and Carry. The 'Sum' output of the first adder will be the
first input of the second half adder, and the 'Carry' output of the first adder will be the
second input of the second half adder. The second half adder will again provide 'Sum' and
'Carry'. The final outcome of the Full adder circuit is the 'Sum' bit. In order to find the
final output of the 'Carry', we provide the 'Carry' output of the first and the second adder
into the OR gate. The outcome of the OR gate will be the final carry out of the full adder
circuit. The MSB is represented by the final 'Carry' bit. The full adder logic circuit can be
constructed using the 'AND' and the 'XOR' gate with an OR gate.
Layout Connection and Output:

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 Transient Analysis

Result : Thus, we have designed the layout of 3-input Full Adder gate using CMOS
generator and simulated the transient characteristics of sum and carry.

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 Experiment - 8
Aim: To design layout of Common Source Amplifier gate using CMOS generator and
simulate it
Software Used: Microwind (90nm)
Theory:

●
In a common-source (CS) amplifier, the input signal is applied to the gate and the output
signal is taken from the drain. The amplifier has higher input resistance and lower gain
than the equivalent CE amplifier. The ac voltage gain of this circuit is Vout=Vin, where
Vin=Vgs and Vout=Vds. The voltage gain expression is, therefore,
Av = Vds/Vgs
From the equivalent circuit, Vds = IdRd and from the definition of transconductance,
gm = Id/Vgs, Substituting the two preceding expressions into the equation for voltage
gain yields
Av=gm Rd
The bandwidth (also called the 3 dB frequency) is the frequency where the signal drops
to 1/ √2 of its low-frequency value. (In decibels, dB(√2) = 3.01 dB). A reduction to 1/ √2
occurs when ωCM RA = 1, making the input signal at this value of ω (call this value ω3
dB, say) vG = VA / (1+j). The magnitude of (1+j) = √2. As a result, the 3 dB frequency f3
dB = ω3 dB / (2π) is:

Layout Connection and Output:

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 Transient Analysis

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 Result : Thus, we have designed the layout of Common Source (CS) Amplifier using
MOS generator and simulated the transient characteristics.

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 Experiment - 9
Aim: To design layout of Differential Amplifier gate using CMOS generator and
simulate it
Software Used: Microwind (90nm)
Theory:

A differential amplifier (also known as a difference amplifier or op-amp subtractor) is a

type of electronic amplifier that amplifies the difference between two input voltages but
suppresses any voltage common to the two inputs. A differential amplifier is an analog
circuit with two inputs (V1 and V2) and one output (V0) in which the output is ideally
proportional to the difference between the two voltages. The formula for a simple
differential amplifier can be expressed: Differential Amplifier formula

Where
V0 is the output voltage V1 and V2 are the input voltages Ad is the gain of the amplifier
(i.e. the differential amplifier gain)
Layout Connection and Output:

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 Transient Analysis

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 Result : Thus, we have designed the layout of the Differential Amplifier using a MOS
generator and simulated the transient characteristics.

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