®

PCM66P
FPO
FPO

16-Bit CMOS Monolithic Audio

DIGITAL-TO-ANALOG CONVERTER

FEATURES DESCRIPTION
● LOW COST 16-BIT 2-CHANNEL CMOS The PCM66P is a low cost, dual output 16-bit CMOS
MONOLITHIC D/A CONVERTER digital-to-analog converter. The PCM66P features true
glitch-free voltage outputs, internal reference and re-
● SINGLE SUPPLY +5V OPERATION
quires only a single +5V supply. Total power dissipa-
● 50mW POWER DISSIPATION tion is less than 50mW max. Low maximum Total
● GLITCH-FREE VOLTAGE OUTPUTS Harmonic Distortion + Noise (–86dB max; PCM66P-
● LOW DISTORTION: –86dB max THD + N J) is 100% tested. Either one or two channel output
modes are fully user selectable.
● COMPLETE WITH REFERENCE
● SERIAL INPUT FORMAT The PCM66P comes in a space-saving 20-pin plastic
SOIC package. PCM66P accepts a serial data input
● SINGLE OR DUAL DAC MODE format and is compatible with other Burr-Brown PCM
OPERATION products such as the industry standard PCM56P.
● PLASTIC 20-PIN SOIC PACKAGE

VCC (+5V) Reference V REF

A COM
SDM SEL
LRDAC 16-Bit Integrate
VOUT DAC & Hold Amp L CH Out
Control
LRCLK
Logic
WDCLK V OUT
CLK Integrate
Serial-to-Parallel R CH Out
& Hold Amp
DATA Shift Register
D COM

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Tel: (602) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (602) 889-1510 • Immediate Product Info: (800) 548-6132

©
1990 Burr-Brown Corporation PDS-1051D Printed in U.S.A. October, 1993
SPECIFICATIONS
ELECTRICAL
All specifications at 25°C, and +VCC = +5V unless otherwise noted.

PCM66P AND PCM66P, J

PARAMETER CONDITIONS MIN TYP MAX UNITS
RESOLUTION 16 Bits
DYNAMIC RANGE 96 dB
DIGITAL INPUT TTL Compatible CMOS
Logic Family
Logic Level: VIH IIH = +40µA max +2.4 +5.25 V
VIL IIL = –40µA max 0 0.8 V
Data Format Serial BTC(1)
Input Clock Frequency 8.5 MHz
DYNAMIC CHARACTERISTICS
TOTAL HARMONIC DISTORTION + N(2)
PCM60P/66P: f = 991Hz (0dB)(3) fS = 176.4kHz(4) –88 –82 dB
f = 991Hz (–20dB) fS = 176.4kHz –68 dB
f = 991Hz (–60dB) fS = 176.4kHz –28 dB
PCM60P-J/66P-J: f = 991Hz (0dB) fS = 176.4kHz –92 –86 dB
f = 991Hz (–20dB) fS = 176.4kHz –68 dB
f = 99lHz (–60db) fS = 176.4kHz –28 dB
CHANNEL SEPARATION +80 +85 dB
TRANSFER CHARACTERISTICS
ACCURACY
Gain Error VOUT = 2.6 ±2 ±10 %
Gain Mismatch Channel to Channel ±1 %
Bipolar Zero Error(5) ±30 mV
Gain Drift 0°C to 70°C 100 ppm/°C
Warm-up Time 1 minute
IDLE CHANNEL SNR(6) 20-20kHz with A-weighted filter ±90 dB
ANALOG OUTPUT
Output Range 2.6 Vp-p
Output Impedance 2 Ω
Short Circuit Duration To Be Determined
Settling Time Suffieicnt to Meet 176.4kHz THD + N Specs
Glitch Energy Meets All THD + N Specs Without External Output Deglitching
POWER SUPPLY REQUIREMENTS
+VCC Supply Voltage +4.75 +5 +5.25 V
Supply Current +9.5 mA
Power Dissipation VCC = +5V 50 mW
TEMPERATURE RANGE
Specification 0 +70 °C
Operating –30 +70 °C
Storage –60 +100 °C

NOTES: (1) Binary Two’s Complement coding. (2) Ratio of (DistortionRMS + NoiseRMS) / SignalRMS. (3) D/A converter output frequency/signal level (on both left and
right channels). (4) D/A converter sample frequency (4 x 44.1kHz; 4 times oversampling per channel). (5) Offset error at bipolar zero. (6) Ratio of output at BPZ (Bipolar
Zero) to the full scale range using 20kHz low pass filter in addition to an A-weighted filter.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject
to change without notice. No patent right or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize
or warrant any BURR-BROWN product for use in life support devices and/or systems.

PCM66P 2
PCM66P PIN ASSIGNMENTS PACKAGE INFORMATION(1)
PIN DESCRIPTION MNEMONIC PACKAGE DRAWING
MODEL PACKAGE NUMBER
1 Left/Right Clock LRCLK
2 Word Clock WDCLK PCM66P 20-Pin SOIC 248
3 Clock Input CLK PCM66P, J 20-Pin SOIC 248
4 Data Input DATA NOTE: (1) For detailed drawing and dimension table, please see end of data
5 No Connection NC sheet, or Appendix D of Burr-Brown IC Data Book.
6 Digital Common DCOM
7 Analog Common ACOM
8 Left Channel VOUT L CH Out
9 Output Common VCOM USA OEM PRICES
ORDERING INFORMATION
10 Right Channel VOUT R CH Out
11 Analog Supply +VCC MODEL 1–24 25-99 PCM66P100+
-X
12 Analog Supply +VCC Basic Model Number
PCM66P
P: Plastic $11.80 $10.40 $9.15
13 Reference Decouple CREF
PCM66P-J 13.30
Performance Grade Code 11.70 10.30
14 Reference Sense VREF SENSE
15 Reference Output VREF
16 Analog Supply +VCC
17 Analog Supply +VCC
18 Digital Supply +VCC
19 Single DAC Mode SDM SEL ABSOLUTE MAXIMUM RATINGS
20 Left/Right DAC Select LRDAC
DC Supply Voltage ............................................................................ ±10V
Input Voltage Range ........................................................... –3V to +5.25V
Power Dissipation ............................................................................ 50mW
Operating Temperature .................................................... –30°C to +70°C
Storage Temperature ...................................................... –60°C to +100°C
Lead Temperature (soldering, 10s) ............................................... +300°C

THEORY OF OPERATION
The PCM66P is a dual output, 16-bit CMOS digital-to-analog ships. Data for left and right channel output is loaded
audio converter. The PCM66P, complete with internal refer- alternately into the PCM66P while the control logic
ence, has two glitch-free voltage outputs and requires only a switches the left and right output amplifiers between the
single +5V power supply. Output modes using either one or two appropriate integrate and hold modes. Data word latch-
channels per DAC are user selectable. The PCM66P accepts a ing is controlled by WDCLK (word clock) and channel
serial data input format that is compatible with other Burr- selection is made by LRCLK (left/right clock). Figure 1
Brown PCM products such as the industry standard PCM56P. shows the timing for the single DAC two-channel mode
of operation. The block diagram in Figure 2 shows how
a single DAC output provides switched output to both
ONE DAC TWO-CHANNEL OPERATION integrate and hold amplifiers. Output between left and
Normally, the PCM66P is operated with a continuous clock right channels in this mode is not in phase. See Figure 3
input in a two-channel output mode. This mode is selected when for proper connection of the PCM66P in the two-channel
SDM SEL is held low (single DAC mode select). Refer to the DAC mode.
truth table shown by Table I for exact control logic relation-

PIN FUNCTIONS SERIAL LEFT RIGHT

DATA WORD CHANNEL CHANNEL
SDM SEL LRDAC LRCLCK WDCLK INPUT OUTPUT OUTPUT
0 X 0 0 Right Hold Hold
0 X 0 1 Right Integrate Hold
0 X 1 0 Left Hold Hold
0 X 1 1 Left Hold Integrate
1 0 0 0 Inhibited VCOM Hold
1 0 0 1 Inhibited VCOM Hold
1 0 1 0 Left VCOM Integrate
1 0 1 1 Left VCOM Integrate
1 1 0 0 Right VCOM Hold
1 1 0 1 Right VCOM Hold
1 1 1 0 Inhibited VCOM Integrate
1 1 1 1 Inhibited VCOM Integrate

NOTE: Positive edge of CLK (P3) latches LRCLK (P1), WDCLK (P2), and DATA (P4).

TABLE I. PCM66P Logic Truth Table.

3 PCM66P
 TWO CHANNEL PER DAC OUTPUT MODE

P3 (CLK)

P2 (WDCLK)

P1 (LRCLK) Load Right Channel Data Load Left Channel Data

P4 (DATA) 1 2 8 9 10 11 12 13 14 15 16 1 2 8 9 10 11 12 13 14 15 16

P10 (LCH OUT) Hold Integrate Hold

P10 (LCH VOUT )

P12 (RCH OUT) Hold Integrate

P12 (RCH VOUT )

NOTES: Single DAC Mode Select = 0; L/R DAC Select = X; WDCLK = 50% duty cycle; Serial Data is read in MSB first with BTC coding (MSB
= Bit 1).

SINGLE CHANNEL PER DAC OUTPUT MODE

P3 (CLK)
Both DACs

P2 (WDCLK)
Both DACs

P1 (LRCLK) Load Right DAC Data Load Left DAC Data

Both DACs

P4 (DATA)
1 2 8 9 10 11 12 13 14 15 16 1 2 8 9 10 11 12 13 14 15 16
Both DACs

P12 (RCH OUT) Hold Integrate

Right DAC

P12 (RCH VOUT )

Right DAC

P12 (RCH OUT) Hold Integrate

Left DAC

P12 (RCH VOUT )

Left DAC

NOTES: Single DAC Mode Select = 1; L/R DAC Select = 0 (Left DAC) or 1 (Right DAC).

FIGURE 1. PCM66P Timing Diagram.

PCM66P 4
 DATA

Serial/Parallel
CLK
Shift Register

WDCLK

Mode Control Logic

16-Bit Input 4kΩ 30kΩ
Data Latch
LRCLK

LRDAC
16-Bit D/A 10kΩ 20kΩ
– LCH
SDM SEL Converter
0–3.5V + V OUT

VCOM
4kΩ 30kΩ

Reference
–
–
+
+ 20kΩ
– R CH
+ V OUT

+V CC V REF V REF C REF +V CC

SEN

FIGURE 2. PCM66P Block Diagram.

input with no additional input signals being required to latch

PCM66P the appropriate data from an alternating L/R data word input
Mode Select
stream. In the single DAC mode, the PCM66P’s left channel
1 LRCLK Mode 2 20 output is disabled and held at +VCOM. In this mode both
Digital 2 WDCLK Mode 1 19 DACs share common inputs for DATA, CLK, WDCLK, and
Input
3 CLK +VCC 18
LRCLK. Otherwise circuit connection is the same as the
two-channel DAC mode, with the exception of LRDAC
4 DATA +VCC 17
whose level selects whether the single DAC will output
5 NC +VCC 16 dedicated left or right channel data.
6 D COM VREF 15 10µF
7 A COM V REF SEN 14 INTEGRATE AND HOLD OUTPUT AMPLIFIERS
8 L CH Out CREF 13 The PCM66P incorporates integrate and hold amplifiers on
L CH Out 330pF CREF 0.1µF
9 V COM +VCC 12 each output channel. This allows a single, very fast DAC to
330pF
10 R CH Out +VCC 11
feed both amplifiers and reduce circuit complexity. It also
R CH Out
+ 100µF serves to block the output glitch from the DAC to the
CCOM individual channel outputs and effectively makes the PCM66P
outputs “glitch-free.” The PCM66P is a single +5V supply
3.3µF
+VCC device with a voltage output swing of 2.8Vp-p. The outputs
+5V swing asymmetrically around VCOM (+VCC – 2.33V). See
Table II for exact input/output relationships. Since true
FIGURE 3. PCM66P Connection Diagram. CMOS amplifiers are used on the PCM66P, the load resis-
tance on the outputs should not be less than 100kΩ and the
TWO DAC TWO-CHANNEL OPERATION capacitive loads should not exceed 100pF. For maximum
low-distortion performance, output buffer amplifiers should
In phase, two-channel output can be obtained by using two be considered.
PCM66Ps and choosing the single DAC mode (setting SDM
SEL high). With the use of a high or low input level on
LRDAC (P left/right DAC select), each DAC can have its
right channel output dedicated to either left or right data

5 PCM66P
 DIGITAL INPUT ANALOG OUTPUT performance is typically indicative of 14-bit to 15-bit inte-
Binary Two’s Voltage (V)
gral linearity in the DAC depending on the grade specified.
Complement (Hex) DAC Output (V) VOUT Mode The relationship between THD + N and linearity, however,
is not such that an absolute linearity specification for every
7FFF +FS +3.5629443
0000 BPZ +2.1629871
individual output code can be guaranteed.
8000 –FS +0.7630299
2E5B VCOM +2.6700000
IDLE CHANNEL SNR
TABLE II. PCM66P Input/Output Relationships.
Another appropriate spec for a digital audio converter is idle
channel signal-to-noise ratio (idle channel SNR). This is the
ratio of the noise on either DAC output at bipolar zero in
DISCUSSION OF relation to the full scale range of the DAC. The output of the
SPECIFICATIONS DAC is band limited from 20Hz to 20kHz and an A-
weighted filter is applied to make this measurement.
TOTAL HARMONIC DISTORTION + NOISE
The key specification for the PCM66P is total harmonic
distortion plus noise. Digital data words are read into the OFFSET, GAIN, AND TEMPERATURE DRIFT
PCM66P at four times the standard audio sampling fre- The PCM66P is specified for other important parameters
quency of 44.1kHz or 176.4kHz for each channel, such that such as channel separation and gain mismatch between
a sine wave output of 991Hz is realized. For production output channels. And although the PCM66P is primarily
testing, the output of the DAC goes to a programmable gain meant for use in dynamic applications, typical specs are also
amplifier to provide gain at lower signal output test levels given for more traditional DC parameters such as gain error,
and then through a 20kHz low pass filter before being fed bipolar zero offset error, and temperature gain drift.
into an analog type distortion analyzer. Figure 4 shows a
block diagram of the production THD + N test setup.
In terms of signal measurement, THD + N is the ratio of TIMING CONSIDERATIONS
DistortionRMS + NoiseRMS/SignalRMS expressed in dB. For the The data format of the PCM66P is binary two’s complement
PCM66P, THD + N is 100% tested at three different output (BTC) with the most significant bit (MSB) being first in the
levels using the test setup shown in Figure 4. It is significant serial input bit stream. Table II describes the exact input data
to note that this circuit does not include any output deglitching to voltage output coding relationship. Any number of bits
circuitry. This means the PCM66P meets even its –60dB can precede the 16 bits to be loaded, as only the last 16 will
THD + N specification without use of external deglitchers. be transferred to the parallel DAC register on the first
positive edge of CLK (clock input) after WDCLK (word
ABSOLUTE LINEARITY clock) has gone low. All inputs to the PCM66P are TTL
level compatible.
Even though absolute integral and differential linearity specs
are not given for the PCM66P, the extremely low THD + N

Use 400Hz High-Pass Low-Pass

Distortion Meter Programmable
Filter and 30kHz Filter
(Shiba Soku Model Gain Amp
Low-Pass Filter (Toko APQ-25
725 or Equivalent) 0dB to 60dB
Meter Settings or Equivalent) LOW-PASS FILTER
CHARACTERISTIC
0
–20
Gain (dB)

–40
Binary Digital Code Parallel-to-Serial DUT –60
Counter (EPROM) Conversion (PCM60P/66P)
(PCM66P) –80
–100
–120 1 2 3 4 5
Clock 1 10 10 10 10 10
Latch Enable Frequency (Hz)

Sampling Rate = 44.1kHz x 4 (176.4kHz)

Timing Output Frequency = 991Hz
Logic

FIGURE 4. THD + N Test Setup Diagram.

PCM66P 6
WDCLK DUTY CYCLE 60ns min
WDCLK is the input signal that controls when data is loaded
and how long each output is in the integrate mode. It is P3 (CLK)

therefore recommended that a 50% (high) duty cycle be

maintained on WDCLK. This will ensure that each output P4 (DATA)
will have enough time to reach its final output value, and that
the output level of each channel will be within the gain
P2 (WDCLK) 15ns min
mismatch specification. Refer to Figure 1 for exact timing
relationships of WDCLK to CLK and LRCLK and the
outputs of the PCM66P. The WDCLK can be high longer P1 (LRCLK)
than 50%, as long as setup and hold times shown in Figure
5 are observed and the time high is roughly equivalent for 15ns min
both left and right channels. FIGURE 5. PCM66P Setup and Hold Timing Diagram.

SETUP AND HOLD TIME 100µF decoupling capacitor as shown in Figure 3 should be
The individual serial data bit shifts, the serial to parallel data used regardless of how good the +5V supply is to maximize
transfer, and left/right control are triggered on positive CLK power supply rejection. All grounds should be connected to
edges. The setup time required for DATA, WDCLK, and the analog ground plane as close to the PCM66P as possible.
LRCLK to be latched by the next positive going CLK is
15ns minimum. A minimum hold time of 15ns is also
FILTER CAPACITOR REQUIREMENTS
required after the positive going CLK edge for each data bit
to be shifted into the serial input register. Refer to Figure 5 As shown in Figure 3, CREF and VREF SENSE should have
for the timing relationship of these signals. decoupling capacitors of 0.1µF (C4) and 10µF (C5) to +VCC
respectively with no special tolerance being required. To
maximize channel separation between left and right chan-
MAXIMUM CLOCK RATE nels, 5% 300pF capacitors (C2 and C3) between VCOM and left
The 100% tested maximum clock rate of 8.47MHz for the and right channel outputs are required in addition to a 5%
PCM66P is derived by multiplying the standard audio sample 3µF capacitor (C1) between VCOM and +5V. The ratio of 10k
rate of 44.1kHz times eight (4X oversampling times two to 1 is the important factor here for proper circuit operation.
channels) times the standard audio word bit length of 24 Placement of all capacitors should be as close to the appro-
(44.1kHz x 4 x 2 x 24 = 8.47MHz). Note that this clock rate priate pins of the PCM66P as possible to reduce noise
accommodates a 24-bit word length, even though only 16 pickup from surrounding circuitry.
bits are actually being used.

“STOPPED-CLOCK” OPERATION APPLICATIONS

The PCM66P is normally operated with a continuous clock Probably the most popular use of the PCM66P is in applica-
input signal. If the clock is to be stopped between input data tions requiring single power supply operation. For example,
words, the last 16 bits shifted in are not actually shifted from the PCM66P is ideal for automotive compact disk (CD) and
the serial register to the latched parallel DAC register until digital audio tape (DAT) playback units. To use a more
the first clock after the one used to input bit 16 (LSB). This complex bipolar DAC requiring ±5V supplies in the +12V
means the data is not shifted into the DHC latch until the application, for example, would require driving a stable
start of the next 16-bit data word input, unless at least one “floating” ground and regulating the +12V to +10V. The
additional clock accompanies the 16 used to serially shift in single supply CMOS PCM66P would only require a +5V
data in the first place. In either case, the setup and hold times zener diode to regulate its 50mW max supply. The outputs
for DATA, WDCLK, and LRCLK must still be observed. could be AC coupled to the rest of the circuit for perfectly
acceptable high dynamic performance. The PCM66P is ideal
in any application requiring a minimum of additional cir-
INSTALLATION cuitry as well as ultra-low-power CMOS performance.
The PCM66P only requires a single +5V supply. The +5V Of course, the PCM66P is the D/A converter of choice in
supply, however, is used in deriving the internal reference. any application requiring very low power dissipation. Por-
It is therefore very important that this supply be as “clean” table battery powered test and measurement equipment re-
as possible to reduce coupling of supply noise to the outputs. quiring very low distortion digital to analog converters
If a good analog supply is available at greater than +5V, a would be an ideal application for the CMOS PCM66P with
zener diode can be used to obtain a stable +5V supply. A its 50mW max power dissipation.

7 PCM66P
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