set ndm_file ..

/ref/Clib # real path of ndm file

set ndm [glob -directory $ndm_file *.ndm]

set tech_file "../ref/tech/saed32nm_1p9m_mw.tf" #### path of tech file

create_lib orca_design_semicon_batch -technology $tech_file -ref_libs $ndm

set VERILOG "../ref/ORCA_TOP_designdata/ORCA_TOP.v" #####3verilog path

read_verilog -top ORCA_TOP $VERILOG

current_lib
save_lib

source ../ref/ORCA_TOP_designdata/ORCA_TOP.upf

initialize_floorplan -side_length {2800 2800} -core_offset {10} -core_utilization 0.6

source ../ref/ORCA_TOP_designdata/ORCA_TOP.VA ## soure voltage area

create_utilization_configuration config1 -capacity core_area

report_utilization -config config1

#do macro placement manualy

set_attribute -objects [get_cells -hierarchical -filter "is_hard_macro==true"] -name physical_status -value locked

########### creating keepouts around the all macros ############################

create_keepout_margin -outer {1 1 1 1} -type hard [get_cells -physical_context -filter "is_hard_macro==true"]

####### creating soft blockages between macro channels #####################

derive_placement_blockages #use swith -type hard/soft

############# inserting boundary cells ########################################

set_boundary_cell_rules -left_boundary_cell saed32_rvt|saed32_rvt_std/SHFILL2_RVT -right_boundary_cell saed32_rvt|
saed32_rvt_std/SHFILL2_RVT
compile_boundary_cells

################################ Tap cell insertion ####################################

create_tap_cells -lib_cell saed32_rvt|saed32_rvt_std/SHFILL2_RVT -distance 150 -offset 130 -pattern stagger

save_block -as fp

dp_pre_create_placement_abstract

dp_pre_block_shaping

dp_pre_macro_placement

dp_pre_power_insertion

dp_pre_pin_placement

dp_pre_create_timing_abstract

dp_pre_timing_estimation

dp_pre_budgeting

dp_floorplan_rules

################ Setting Macro Constraints #######################

set macro_cells [get_cells -physical_context -filter “is_hard_macro && !is_physical_only” -quiet]

set_macro_constraints -allowed_orientations {R0 R180} $macro_cells

report_macro_constraints

######################### floorplan initialization ###########################

#initialize_floorplan -core_utilization 0.60 -core_offset 15. – – – → Sqaure shape

#initialize_floorplan -core_utilization 0.6 -shape U -orientation N -side_ratio {2 1 1 1 1 1} -core_offset 15 -coincident_boundary true –
– -> U shape

#initialize_floorplan -core_utilization 0.6 -shape L -orientation N -core_offset 15 -coincident_boundary true -side_ratio {1 1 1 1} – – ->
L shape

#initialize_floorplan -core_utilization 0.6 -shape T -orientation N -core_offset 15 -coincident_boundary true -side_ratio {1 1 2 1 2 1} –

– -> T shape

#initialize_floorplan -core_utilization 0.6 -shape R -orientation N -core_offset 15 -coincident_boundary true -side_ratio {10 3} -
boundary {{0 0} {150 300}} – – -> R shape

#initialize_floorplan -control_type die -boundary {{0 0} {0 3000} { 1000 3000} {1000 2000} {2000 2000} { 2000 3000} {3000 3000}
{ 3000 0} {2000 0} { 2000 1000} { 1000 1000} {1000 0}} -core_offset 100. – – > H shape

########################## tap cell insertion #######################

get_lib_cells TAP

create_tap_cells -lib_cell saed14rvt_frame_timing_ccs/SAEDRVT14_TAPDS -pattern stagger -distance 15

################################ boundary cells insertion #######################

get_lib_cells BOUND

create_boundary_cells -tap_distance 20 -left_boundary_cell <cell name> -right_boundary_cell <cell names>

write_floorplan -output floorplan.tcl

report_design -floorplan. (or) report_design -all

report_global_timing

get_cells -filter “design_type==physical_only”

get_cells -filter “design_type==fill”

########################### pin placement #################################

set_app_options -name plan.pins.incremental -value false -block [current_block]

#set_app_options -name plan.pins.layer_range -value 2 -block [current_block]

#set_app_options -name plan.pins.pin_range -value 3 -block [current_block]

set_block_pin_constraints -self -allowed_layers {M3} -pin_spacing 3 -sides {1 3} -width {0.07} -corner_keepout_num_tracks 1 -self –
– – > for inputs

place_pins -ports [get_ports -filter {direction == in }] (or) place_pins -ports [all_inputs]

set_block_pin_constraints -self -allowed_layers {M2} -pin_spacing 3 -sides {2 4} -width {0.07} -corner_keepout_num_tracks 1 -self –
– -> for outputs

place_pins -ports [get_ports -filter {direction == out}] (or) place_pins -ports [all_outputs]

place_pins -legalize -ports [all_inputs]

place_pins -legalize -ports [all_outputs]

check_pin_placement

set_fixed_objects [get_flat_cells -filter “is_hard_macro “] – – – → to fix the status

############################# IO filler cells #######################

create_io_filler_cells -prefix filler_reference_cells {{ FILLER20A FILLER10A FILLER5A

FILLER1A FILLER05A FILLER0005A }}

####################### powerplan1 ##########################

##### create ports vdd vss #####

create_port -port_type ground -direction in VSS

create_port -port_type power -direction in VDD

###### create nets vdd vss #####

create_net -power VDD

create_net -ground VSS

#### connect ports to nets. #####

connect_pg_net -net VDD [get_port VDD]

connect_pg_net -net VSS [get_port VSS]

connect_pg_net. -net VDD [get_pins -hierarchical */VDD]

connect_pg_net. -net VSS [get_pins -hierarchical */VSS]

###### to dissable via connection during compile pg

set_app_options -name plan.pgroute.disable_via_creation -value true

###### to create rail ######

create_pg_std_cell_conn_pattern rail_pattern -layers M1 -rail_width 0.15

set_pg_strategy M1_rails -core -pattern {{name: rail_pattern} nets: VDD VSS}

compile_pg. -strategies M1_rails

###### define pg mesh for m2 t0 m7 layers (only core region) ######

create_pg_mesh_pattern M4toM7 -layers {{{vertical_layer: M4} {spacing: minimum} {pitch: 2.2} {width: 0.22} {offset: 0.6}}
{{vertical_layer: M6} {spacing: minimum} {pitch: 2.4} {width:0.24} {offset: 0.6}} {{horizontal_layer: M5} {spacing: minimum} {pitch:
2.6} {width:0.26} {offset: 0.6}} {{horizontal_layer: M7} {spacing: minimum} {pitch: 3} {width:0.5} {offset: 0.6}}}

set_pg_strategy pg_mesh -core -pattern. {{name: M4toM7 } {nets: VDD VSS }} -extension {{stop: 0.2} {layers: M4}}

compile_pg -strategies. pg_mesh

############ define pg for M9 M8. ##################

create_pg_mesh_pattern. M9 -layers {{horizontal_layer: M9} {width: 1.0} {pitch: 3} {spacing: minimum} {offset: 0.9}}

set_pg_strategy ring_pg_M9 -design_boundary -pattern {{name: M9 } {nets: VDD VSS }} -extension {{stop:
design_boundary_and_generate_pin}}

compile_pg -strategies ring_pg_M9

create_pg_mesh_pattern. M8 -layers {{vertical_layer: M8 } {width: 1.0} {pitch: 6} {spacing: minimum} {offset: 1.4}}

set_pg_strategy ring_pg_M8 -design_boundary -pattern {{name: M8 } {nets: VDD VSS }} -extension {{stop: 1} {layers: M9}}

compile_pg -strategies ring_pg_M8

###### checks after pg mesh #####

check_pg_drc

##### create via creation ########

### m4 to m1. ####

set_pg_via_master_rule M4_M1 -contact_code {VIA12_LONG_H VIA23_1cut_V VIA34_LONG_HH}

create_pg_vias -nets. {VDD VSS} -from_layers M4 -to_layers M1 -via_masters M4_M1 -allow_parallel_objects -within_bbox
[get_attribute [current_block] bbox]

check_pg_drc

check_pg_missing_vias

#M5_M4#33

set_pg_via_master_rule M5_M4 -contact_code {VIA45_LONG_V}

create_pg_vias -nets {VDD VSS} -from_layers M5 -to_layers M4 -via_masters M5_M4 -allow_parallel_objects -within_bbox
[get_attribute [current_block] bbox]

check_pg_drc

check_pg_missing_vias

# M6_M5

set_pg_via_master_rule M6_M5 -contact_code {VIA56_1cut_V}

create_pg_vias -nets {VDD VSS} -from_layers M6 -to_layers M5 -via_masters M6_M5 -allow_parallel_objects -within_bbox
[get_attribute [current_block] bbox]

check_pg_drc

check_pg_missing_vias

#M7_M6

set_pg_via_master_rule M7_M6 -contact_code {VIA67_1cut}

create_pg_vias -nets {VDD VSS} -from_layers M7 -to_layers M6 -via_masters M7_M6 -allow_parallel_objects -within_bbox
[get_attribute [current_block] bbox]

check_pg_drc

check_pg_missing_vias

# M8_M7

set_pg_via_master_rule M8_M7 -contact_code {VIA78_1cut}

create_pg_vias -nets {VDD VSS} -from_layers M8 -to_layers M7 -via_masters M8_M7 -allow_parallel_objects -within_bbox
[get_attribute [current_block] bbox]

check_pg_drc

check_pg_missing_vias
#M9_M8

set_pg_via_master_rule M9_M8 -contact_code {VIA89_1cut}

create_pg_vias -nets {VDD VSS} -from_layers M9 -to_layers M8 -via_masters M9_M8 -allow_parallel_objects -within_bbox
[get_attribute [current_block] bbox]

check_pg_drc

check_pg_missing_vias

############################# powerplan 2. ###########################

remove_pg_via_master_rules -all

remove_pg_patterns -all

remove_pg_strategies -all

remove_pg_strategy_via_rules -all

create_net -power VDD

create_net -ground VSS

create_pg_ring_pattern ring_pattern -horizontal_layer M9 -horizontal_width {3} -horizontal_spacing {1} -vertical_layer M9 -

vertical_width {3} -vertical_spacing {1}

set_pg_strategy core_ring -pattern {{name: ring_pattern} {nets: {VDD VSS }} {offset: {1 1}}} -core -extension {{stop:
design_boundary_and_generate_pin}}

compile_pg -strategies core_ring

###### 1st level grid######

create_pg_mesh_pattern mesh_pattern -layers {{{vertical_layer: M6} {width: 1.5} {pitch: 5} {offset: 5} { trime: true }}
{{horizontal_layer: M5} {width: 1.2} {pitch: 5} {offset: 5} {trim : true}}}
set_pg_strategy M5M6_mesh -pattern {{name: mesh_pattern} {nets: VDD VSS }} -core -extension {{stop: design_boundary}}

compile_pg -strategies M5M6_mesh

###### 2nd level grid ########

create_pg_mesh_pattern mesh_pattern -layers {{{vertical_layer: M5} {width: 1} {pitch: 3} {offset: 1.7} { trime: true }}
{{horizontal_layer: M4} {width: 0.89} {pitch: 1.7} {offset: 1.5} {trim : true}}}

set_pg_strategy M4M5_mesh -pattern {{name: mesh_pattern} {nets: VDD VSS }} -core -extension {{stop: core_ring}}

compile_pg -strategies M4M5_mesh

##### rails ############

create_pg_std_cell_conn_pattern rail_pattern -layers M1 -rail_width 0.9

set_pg_strategy M1_rails -core -pattern {{name: rail_pattern} nets: VDD VSS}

compile_pg. -strategies M1_rails

############## checks after powerplan ##############

check_pg_drc -nets {VDD VSS}

analyze_power_plan -report_track_utilization_only

check_pg_missing_vias

#before placement we should do

######### buffer adding at each ports#######################

remove_from_collection [get_port *] {clk I1 I2 VDD VSS}

report_utilization

check_design -checks pre_placement_stage

add_buffer -lib_cell <tcbn28hpcplusbwp40p140hvt_c/BUFFD4BWP40P140HVT> [remove_from_collection [all_inputs] {clk I1 I2 VDD
VSS}]

legalize_placement

add_buffer -lib_cell <tcbn28hpcplusbwp40p140hvt_c/BUFFD4BWP40P140HVT> [all_outputs]

legalize_placement

set_placement_status fixed [get_cell eco_cell*]

#avoid overlapps

legalize_placement

#to set dont touch on net & cell

get_cells eco_cell*

set_dont_touch [get_cell eco_cell*]

get_nets eco_net*

set_dont_touch [get_nets eco_net*]

check_pg_drc

sizeof_collection [get_cells eco*]

connect_pg_net. -net VDD [get_pins -hierarchical */VDD]

connect_pg_net. -net VSS [get_pins -hierarchical */VSS]

check_pg_drc
### prefixing the newly added cells. during place_opt ######

set_app_options -name opt.common.user_instance_name_prefix -value “newly_added”

#opt.common.user_instance_name_prefix newly_added

#### do not use CK buff during placements ###

set_lib_cell_purpose -include none [get_lib_cells /CK]

####### do not use high drive strength cell for better utilization###################

set_lib_cell_purpose -include none [get_lib_cells {/*D12 /*D16/*D20 /*D24}]

############ checks before place cells ####################

report_qor -summary

report_design

report_utilization -verbose

check_pg_drc

check_pg_missing_vias

check_legality

check_boundary_cells

report_scenarios

report_parasitic_parameters

report_utilization

####################### placement ##########################

set_app_options -name time.disable_recovery_removal_checks -value false

set_app_options -name time.disable_case_analysis -value false

set_app_options -name place.coarse.continue_on_missing_scandef -value true

set_app_options -name plan.place.auto_create_blockages -value auto

set_app_options -name opt.common.user_instance_name_prefix -value place

set_app_options -name place.coarse.auto_density_control -value true

##### magnetic placement #######

magnet_placement [get_cells “INST_1"] – → performs magnet placement on the INST_1 cell

magnet_placement -mark_fixed [get_cells “INST_2"] – -→ performs magnet placement. and. marks. the. moved cells as fixed
afterwards

magnet_placement -logical_levels 2. [get_cells “INST_2"] – -→ pulls two levels of cells to INST_2

. ##### bounds creation ###########

create_bound -effort high -name bound1 {cell1 cell2 cell3 … celln} – -→ Create a group bound for the collection of island of
cells/macros

create_bound -name “movebound1" -boundary {{50 60} { 40 80}} -type hard -exclusive {invA1 reset} – -→ creates a hard exclusive
move bound named “move bound1" with. square bound. shape. The. bound contains the invA1 cell and reset port.

######### keepout margin / cell padding ###########

create_keepout_margin -type soft -outer {10 10 10 10} [get_cells MY_LEAF_CELL]

#### to reduce congestion b/w hard macros & perform. coarse placement ####

set_app_options -name plan.place.congestion_driven_mode -value macro

create_placement -floorplan -congestion -congestion_effort high

#### timing-driven placement only to standard cells ######

set_app_options -name plan.place.timing_driven_mode -value std_cell

create_placement -floorplan -timing_drivenmagnet_placement INST_3 -cells {Cel_1 Cel_2 Cel_3}

####### Combined Congestion-Driven and Timing-Driven Placement ########

set_app_options -name plan.place.congestion_driven_mode -value both

set_app_options -name plan.place.timing_driven_mode -value both

create_placement -timing_driven -buffering_aware_timing_driven -congestion -effort high -congestion_effort high -incremental

########## individual stages placement #########

place_opt -from initial_place -to. initial_place

report_utilization

place_opt -from initial_drc -to. initial_drc

report_utilization

place_opt -from initial_opto -to initial_opto

report_utilization

place_opt -from final_place -to final_place

report_utilization

place_opt -from final_opto -to final_opto

report_utilization
legalize_placement -incremental

check_legality -verbos

report_congestion

report_utilization