V.

Control Unit
The Control Unit is part of the computer’s central processing unit (CPU),
which directs the operation of the processor. It was included as part of the
Von Neumann Architecture by John von Neumann. It is the responsibility of
the control unit to tell the computer’s memory, arithmetic/logic unit, and
input and output devices how to respond to the instructions that have been
sent to the processor. It fetches internal instructions of the programs from the
main memory to the processor instruction register, and based on this register
contents, the control unit generates a control signal that supervises the
execution of these instructions.
Examples of devices that require a CU are:
 Control Processing Units(CPUs)
 Graphics Processing Units(GPUs)

Functions of the Control Unit

It coordinates the sequence of data movements into, out of, and between a
processor’s many sub-units.
It interprets instructions.
It controls data flow inside the processor.
It receives external instructions or commands to which it converts to a
sequence of control signals.
It controls many execution units (i.e. ALU , data buffers and registers )
contained within a CPU.
It also handles multiple tasks, such as fetching, decoding, execution handling
and storing results.

VI.Bus interconnection structure

Computers comprise of many internal components and in order for these
components to communicate with each other, a ‘bus’ is used for that purpose.
A bus is a common pathway through which information flows from one
component to another. This pathway is used for communication purpose and
can be
established between two or more computer components. We are going to
review different computer bus architectures that are used in computers.
Different Types of Computer Buses

Functions of Buses in Computers

The functions of buses can be summarized as below:
1. Data sharing - All types of buses found on a computer must be able to
transfer data
between the computer peripherals connected to it.
The data is transferred in either serial or parallel, which allows the exchange
of 1, 2, 4 or even 8 bytes of data at a time. (A byte is a group of 8 bits). Buses
are classified depending on how many bits they can move at the same time,
which means that we have 8-bit, 16-bit, 32-bit or even 64-bit buses.
2. Addressing - A bus has address lines, which match those of the processor.
This allows data to be sent to or from specific memory locations.
3. Power - A bus supplies power to various peripherals that are connected to
it.
4. Timing - The bus provides a system clock signal to synchronize the
peripherals attached to it with the rest of the system. The expansion bus
facilitates the easy connection of additional components and devices on
a computer, for example the addition of a TV card or sound card.

A computer consists of a set of components or modules. A module is a

separate unit of software and hardware. Information is exchanged through
these modules. Basically, there are three types of modules:
Processor module
The processor reads instructions and data, writes out data after processing
and uses control signals to control the overall operations of the system. It also
receives interrupt signals.
Memory module
It consists of N words of equal length. Each word is assigned a unique
numerical address(0, 1, 2…..N-1). A word of data can be read from or written
into the memory. The nature of the operation is indicated by the read and
write control signals. The location for the operation is specified by an
address.
I/O module
There are two operations, read and write. I/O module may control more than
one external device. A user can refer to each of the interfaces to an external
device as port and each can be assigned a unique address. There are also
external data paths for the input and output of data with an external device.
I/O module may be able to send interrupt signals to the processor.
VII. Instruction Set Architecture & Instruction Execution Cycle
Computer function:
The basic function performed by a computer is execution of a program,
which consists of a set of instructions stored in memory. Instruction
processing consists of two steps: The processor reads (fetches) instructions
from memory one at a time and executes each instruction. Program execution
consists of repeating the process of instruction fetch and instruction
execution.
A program residing in the memory unit of a computer consists of a sequence
of instructions. These instructions are executed by the processor by going
through a cycle for each instruction.
In a basic computer, each instruction cycle consists of the following phases:
1. Fetch instruction from memory.
2. Decode the instructions.
3. Read the effective address from memory.
4. Execute the instructions.
This image represents the basic operation cycle of a computer’s central
processing unit (CPU), often referred to as the instruction cycle or fetch-
decode-execute cycle. Let's break it down:
Components:
1. SC (Sequence Counter): Initialized to 0 to start the cycle.
2. PC (Program Counter): Contains the address of the next instruction
to be executed.
 3. AR (Address Register): Holds the memory address of data to be
accessed.
4. IR (Instruction Register): Contains the current instruction fetched
from memory.
5. I: Denotes the indirect bit. It is set if the instruction involves indirect
addressing.
6. D0-D7: Instruction decoder lines, which identify the specific
instruction (based on bits 12-14).
7. D7: A control signal for memory reference instructions.
Phases of Operation:
1. Fetch Phase (T0 - T1):
o The CPU starts by setting the AR = PC (program counter is
loaded into the address register).
o The CPU fetches the instruction from memory: IR = M[AR], and
increments the PC by 1: PC = PC + 1.
2. Decode Phase (T2):
o The instruction is decoded:
 The indirect bit I is extracted from IR[15].
 The operation code is decoded using the instruction
decoder D0…D7, taking bits IR[12-14].
 The address part of the instruction AR = IR[0-11] is
updated.
1. Execution Phase (T3 - onward):
o Based on the instruction, the control goes through several
branches:
 I = 1 and D7 = 1: Execute I/O or Register Reference
instruction.
 I = 0 and D7 = 1: Execute Memory Reference Instruction
(Direct Addressing).
 I = 1 and D7 = 0: Do nothing.
 I = 0 and D7 = 0: Execute memory instruction (with
indirect addressing, if applicable).
Key Steps:
 I/O or Register Reference Instructions (left side):
o If the instruction is related to input/output or register
manipulation, execute these operations.
 Memory Reference Instructions (right side):
 o If the instruction is a memory reference (e.g., load/store), the
address is computed and memory is accessed.
Combinations:
 Green (Fetch Phase): Highlights the steps where the instruction is
fetched from memory.
 Blue (Decode Phase): Shows the decoding of the instruction.
 Orange (Execute Phase): Where the actual operation based on the
instruction is performed.
 Conditions: Represent the decision-making points that guide the flow
of execution based on the type of instruction.
 

Instruction Fetch and Execute:

At the beginning of each instruction cycle, the processor fetches an
instruction from
memory. The program counter (PC) holds the address of the instruction to be
fetched next, the processor always increments the PC after each instruction
fetch so that it will fetch the next instruction in sequence.
For example, consider a computer in which each instruction occupies one 16-
bit word of
memory. If the program counter is set to location 300. The processor will
next fetch the instruction at location 300. On next instruction cycles, it will
fetch instructions from locations 301,302,303,and so on.
The fetched instruction is loaded into a register in the processor known as the
instruction
register (IR). The processor interprets the instruction and performs the
required action. In general, these actions fall into four categories:
 Processor-memory: Data may be transferred from processor to memory
or from memory to processor.
 Processor-I/O: Data may be transferred to or from a peripheral device by
transferring between the processor and an I/O module.

Interrupts and the instruction cycle:

Interrupts are provided primarily as a way to improve processing efficiency.
In the interrupt cycle, the processor checks to see if any interrupts have
occurred. If no
interrupts are pending, the processor proceeds to the fetch cycle and fetches
the next instruction of the current program. If an interrupt is pending, the
processor does the following:
• It suspends execution of the current program being executed and saves its
context

• It sets the program counter to the starting address of an interrupt handler

routine.
The processor now proceeds to the fetch cycle and fetches the first instruction
in the interrupt handler program, which will service the interrupt. When the
interrupt handler routine is completed, the processor can resume execution of
the user program at the point of interruption.
Types of Interrupts:
 Program Interrupts: Generated by some condition that occurs as a result
of an instruction execution, such as arithmetic overflow, division by zero,
attempt to execute an illegal machine instruction, or reference outside a
user’s allowed memory space.

 Timer Interrupts: Generated by a timer within the processor. This allows

the operating system to perform certain functions on a regular basis.

 I/O Interrupts: Generated by an I/O controller, to signal normal

completion of an operation or to signal a variety of error conditions.

Performance:
The most important measure of the performance of a computer is how
quickly it can execute programs. The speed with which a computer executes
program is affected by the design of its hardware. For best performance, it is
necessary to design the compiles, the machine instruction set, and the
hardware in a coordinated way.

Processor clock:

Processor circuits are controlled by a timing signal called clock. The

clock designer the regular time intervals called clock cycles. To execute a
machine instruction the processor divides the action to be performed into a
sequence of basic steps that each step can be completed in one clock cycle.
The length P of one clock cycle is an important parameter that affects the
processor performance.

VIII. Register Transfer Language

Computer registers:
 Data Register(DR) : hold the operand(Data) read from memory.
 Accumulator Register(AC): general purpose processing register.
 Instruction Register(IR): hold the instruction read from memory.
 Temporary Register(TR): hold a temporary data during processing.
 Address Register(AR): hold a memory address, 12 bit width.
 Program Counter(PC): It hold the address of the next instruction to be read
from memory after the current instruction is executed.
o Instruction words are read and executed in sequence unless a branch
instruction is encountered »A branch instruction calls for a transfer to a
nonconsecutive instruction in the program.
o address part of a branch instruction is transferred to PC to become the
address of the next instruction.
 Input Register(INPR): receive an 8-bit character from an input device.
 Output Register(OUTR): hold an 8-bit character for an output device.
 A digital computer system exhibits an interconnection of digital
modules such as registers, decoders, arithmetic elements, and Control logic.
These digital modules are interconnected with some common data and
control paths to form a complete digital system.
Moreover, digital modules are best defined by the registers and the operations
that are performed on the data stored in them.
The operations performed on the data stored in registers are called Micro-
operations.

The internal hardware organization of a digital system is best defined by

specifying:
o The set of registers and the flow of data between them.
o The sequence of micro-operations performed on the data which are
stored in the registers.
o The control paths that initiates the sequence of micro-operation

The Register Transfer Language is the symbolic representation of notations

used to specify the sequence of micro-operations.
In a computer system, data transfer takes place between processor registers
and memory and between processor registers and input-output systems.
These data transfer can be represented by standard notations given below:
o Notations R0, R1, R2..., and so on represent processor registers.
 o The addresses of memory locations are represented by names such as
LOC, PLACE, MEM, etc.
o Input-output registers are represented by names such as DATA IN,
DATA OUT and so on.
o The content of register or memory location is denoted by placing
square brackets around the name of the register or memory location.

Register Transfer
The term Register Transfer refers to the availability of hardware logic circuits
that can perform a given micro-operation and transfer the result of the
operation to the same or another register.
Most of the standard notations used for specifying operations on various
registers are stated below.

oThe memory address register is designated by MAR.

o Program Counter PC holds the next instruction's address.
o Instruction Register IR holds the instruction being executed.
o R1 (Processor Register).
o We can also indicate individual bits by placing them in parenthesis. For
instance, PC (8-15), R2 (5), etc.
o Data Transfer from one register to another register is represented in
symbolic form by means of replacement operator. For instance, the
following statement denotes a transfer of the data of register R1 into
register R2.
R2 ← R1

o Typically, most of the users want the transfer to occur only in a

predetermined control condition. This can be shown by following if-
then statement:
If (P=1) then (R2 ← R1); Here P is a control signal generated in the
control section.
o It is more convenient to specify a control function (P) by separating the
control variables from the register transfer operation. For instance, the
following statement defines the data transfer operation under a specific
control function (P).
P: R2 ← R1

The following image shows the block diagram that depicts the transfer of
data from R1 to R2.

Here, the letter 'n' indicates the number of bits for the register. The 'n' outputs
of the register R1 are connected to the 'n' inputs of register R2.
A load input is activated by the control variable 'P' which is transferred to the
register R2.
Bus and Memory Transfers
A digital system composed of many registers, and paths must be
provided to transfer information from one register to another. The number of
wires connecting all of the registers will be excessive if separate lines are
used between each register and all other registers in the system.
A bus structure, on the other hand, is more efficient for transferring
information between registers in a multi-register configuration system.
A bus consists of a set of common lines, one for each bit of register, through
which binary information is transferred one at a time. Control signals
determine which register is selected by the bus during a particular register
transfer.
The following block diagram shows a Bus system for four registers. It is
constructed with the help of four 4 * 1 Multiplexers each having four data
inputs (0 through 3) and two selection inputs (S1 and S2).

We have used labels to make it more convenient for you to understand the
input-output configuration of a Bus system for four registers. For instance,
output 1 of register A is connected to input 0 of MUX1.
The two selection lines S1 and S2 are connected to the selection inputs of all
four multiplexers. The selection lines choose the four bits of one register and
transfer them into the four-line common bus.
When both of the select lines are at low logic, i.e. S1S0 = 00, the 0 data
inputs of all four multiplexers are selected and applied to the outputs that
forms the bus. This, in turn, causes the bus lines to receive the content of
register A since the outputs of this register are connected to the 0 data inputs
of the multiplexers.
Similarly, when S1S0 = 01, register B is selected, and the bus lines will
receive the content provided by register B.
The following function table shows the register that is selected by the bus for
each of the four possible binary values of the Selection lines.
A bus system can also be constructed using three-state gates instead of
multiplexers.
The three state gates can be considered as a digital circuit that has three
gates, two of which are signals equivalent to logic 1 and 0 as in a
conventional gate. However, the third gate exhibits a high-impedance state.
The most commonly used three state gates in case of the bus system is
a buffer gate.
The graphical symbol of a three-state buffer gate can be represented as:

Memory Transfer
Most of the standard notations used for specifying operations on memory
transfer are stated below.

o The transfer of information from a memory unit to the user end is

called a Read operation.
o The transfer of new information to be stored in the memory is called
a Write operation.
o A memory word is designated by the letter M.
o We must specify the address of memory word while writing the
memory transfer operations.
o The address register is designated by AR and the data
register by DR.
o Thus, a read operation can be stated as:

Read: DR ← M [AR]

o The Read statement causes a transfer of information into the data

register (DR) from the memory word (M) selected by the address
register (AR).
o And the corresponding write operation can be stated as:
 Write: M [AR] ← R1

The Write statement causes a transfer of information from register R1 into

the memory word (M) selected by address register (AR).

Arithmetic Micro-operations:
In general, the Arithmetic Micro-operations deals with the operations
performed on numeric data stored in the registers.
The basic Arithmetic Micro-operations are classified in the following
categories:

1. Addition
2. Subtraction
3. Increment
4. Decrement
5. Shift

Symbolic Representation Description

The contents of R1 plus

R3 ← R1 + R2
R2 are transferred to R3.

The contents of R1 minus

R3 ← R1 - R2
R2 are transferred to R3.

R2 ← R2' Complement the contents

 of R2 (1's complement)

2's complement the

R2 ← R2' + 1
contents of R2 (negate)

R1 plus the 2's

R3 ← R1 + R2' + 1 complement of R2
(subtraction)

Increment the contents of

R1 ← R1 + 1
R1 by one

Decrement the contents of

R1 ← R1 – 1
R1 by one

Binary Adder:
The Add micro-operation requires registers that can hold the data and
the digital components that can perform the arithmetic addition.
A Binary Adder is a digital circuit that performs the arithmetic sum of two
binary numbers provided with any length.
A Binary Adder is constructed using full-adder circuits connected in series,
with the output carry from one full-adder connected to the input carry of the
next full-adder.
The following block diagram shows the interconnections of four full-adder
circuits to provide a 4-bit binary adder.
 o The augend bits (A) and the addend bits (B) are designated by subscript
numbers from right to left, with subscript '0' denoting the low-order bit.
o The carry inputs starts from C0 to C3 connected in a chain through the
full-adders. C4 is the resultant output carry generated by the last full-
adder circuit.
o The output carry from each full-adder is connected to the input carry of
the next-high-order full-adder.
o The sum outputs (S0 to S3) generates the required arithmetic sum of
augend and addend bits.
o The n data bits for the A and B inputs come from different source
registers. For instance, data bits for A input comes from source register
R1 and data bits for B input comes from source register R2.
o The arithmetic sum of the data inputs of A and B can be transferred to a
third register or to one of the source registers (R1 or R2).

Binary Adder-Subtractor:
The Subtraction micro-operation can be done easily by taking the 2's
compliment of addend bits and adding it to the augend bits.
The Arithmetic micro-operations like addition and subtraction can be
combined into one common circuit by including an exclusive-OR gate with
each full adder.
The block diagram for a 4-bit adder-subtractor circuit can be represented as:
 o When the mode input (M) is at a low logic, i.e. '0', the circuit act as an
adder and when the mode input is at a high logic, i.e. '1', the circuit act
as a subtractor.
o The exclusive-OR gate connected in series receives input M and one of
the inputs B.
o When M is at a low logic, we have B⊕ 0 = B.
The full-adders receive the value of B, the input carry is 0, and the
circuit performs A plus B.
o When M is at a high logic, we have B⊕ 1 = B' and C0 = 1.
The B inputs are complemented, and a 1 is added through the input
carry. The circuit performs the operation A plus the 2's complement of
B.

Binary Incrementer
The increment micro-operation adds one binary value to the value of
binary variables stored in a register. For instance, a 4-bit register has a binary
value 0110, when incremented by one the value becomes 0111.
The increment micro-operation is best implemented by a 4-bit combinational
circuit incrementer. A 4-bit combinational circuit incrementer can be
represented by the following block diagram.
 o A logic-1 is applied to one of the inputs of least significant half-adder,
and the other input is connected to the least significant bit of the
number to be incremented.
o The output carry from one half-adder is connected to one of the inputs
of the next-higher-order half-adder.
o The binary incrementer circuit receives the four bits from A0 through
A3, adds one to it, and generates the incremented output in S0 through
S3.
o The output carry C4 will be 1 only after incrementing binary 1111.

IX. Addressing Modes

The term addressing modes refers to the way in which the operand of
an instruction is specified. The addressing mode specifies a rule for
interpreting or modifying the address field of the instruction before the
operand is actually executed.
Implied/ Implicit Addressing Mode
The operands are implicitly specified in the instruction’s definition.
Consider the example, the instruction “complement accumulator” is an
implied-mode instruction as the operand in the accumulator register is
implied in the instruction definition. All register reference the instructions
that use an accumulator are implied-mode instructions. Zero-address
instructions in a stack-organized computer are also implied-mode instructions
because the operands are implied to be on top of the stack.
Immediate Addressing Mode
The operand is defined in the instruction itself. This mode instruction has an
operand field instead of an address field. The operand field contains the
actual operand used with the specified operation in the instruction. The
immediate-mode instructions help initialize registers to a constant value.

Register Direct Addressing Mode

The operands that reside within the CPU are stored in the registers. The
specific register is selected from a register field in the instruction. No
reference to the memory is required to fetch the operand. The only difference
between the Direct addressing mode and the register direct addressing mode
is that the instruction address field refers to a CPU register instead of the
main memory.

Register Indirect Addressing Mode

The instruction defines a register in the CPU that stores the effective address
of the operand in memory. Only one reference to the memory is required to
fetch the operand. The specified register contains the address of the operand
instead of the operand. The only difference between the Indirect addressing
mode and the register indirect addressing mode is that the instruction address
field refers to a CPU register.

Direct Addressing Mode

The effective address of the operand resides in the address field of the
instruction.
The operand resides in the memory, and the address field of the instruction
gives its address. Only one reference to the memory is required to fetch the
operand, and no additional calculations need to be done to find the effective
address of the operand. It is also known as absolute addressing mode.

Indirect Addressing Mode

The address field of the instruction gives the address of the memory location
that contains the effective address of the operand. Two references to the
memory are required to fetch the operand: The control fetches the instruction
from memory and uses its address part to reaccess the memory that stores the
effective address. This addressing mode slows down the execution as it
requires multiple memory lookups to find the operand.