Numerical Part-5 Updated

Q.
The band diagram of a p-type semiconductor with a band-gap of 1 eV

is shown, using this semiconductor, a MOS capacitor having VTH of -
0.16 V, of 100 nF/cm2 and a metal work function of 3.87 eV is
fabricated. There is no charge within the oxide. If the voltage across the
capacitor is VTH, the magnitude of depletion charge per unit area (in
C/cm2) is (GATE – 20)
Vacuum level
(a) 1.4110-8 4 eV
(b) 1.70  10-8 Ec

0.5 eV
(c) 0.52  10-8 Ef
(d) 0.93  10-8 0.2 eV

EFe
Ev
Q. For an n-channel silicon MOSFET with 10nm gate oxide thickness, the
substrate sensitivity (VT/|VBS|) is found to be 50m V/V at a substrate
voltage |VBS| = 2V, where VT is the threshold voltage of the MOSFET.
Assume that, |VBS| > > 2B, where qB is the separation between the
Fermi energy level EF and the intrinsic level Ei in the bulk. Parameters
given are
Electron charge (q) = 1.610-19 C
Vaccum permittivity (0) = 8.8510-12 F/m
Relative permittivity of silicon (si) = 12
Relative Permittivity of oxide (ox) = 4
The doping concentration of the substrate is (GATE – 21)
(a) 4.37  1015 cm-3 (b) 7.37  1015 cm-3
(c) 2.37  1015 cm-3 (d) 9.37  1015 cm-3
Q. For the NMOSFET in the circuit shown, the threshold voltage is Vth,
where Vth> 0. The source voltage VSS is varied from 0 to VDD. Neglecting
the channel length modulation, the drain current ID as a function of VSS is
represented by
(GATE-15) (Set-1)
Q. For the MOSFET M1 shown in the figure, assume W/L =2, VDD = 2.0 V, n Cox = 100
micro units and VTH =0.5 V. The transistor M1 switches from saturation region to linear
region when Vin (in Volts) is _________
(GATE - 14)(Set3)
Common Data for Q.No 14 & 15
In the three dimensional view of a silicon n-channel MOS transistor shown
below,  = 20nm. The transistor is of width 1 m. The depletion width
formed at every p-n junction is 10 nm. The relative permittivities of Si and
SiO2, respectively, are 11.7 and 3.9, and 0 = 8.9 10-12 F/m.
(GATE - 12)
Q. The source-body junction capacitance is approximately
(a) 2 fF
(b) 7 fF
(c) 2 pF
(d) 7 pF
Q. The gate-source overlap capacitance is approximately
(a) 0.7 fF
(b) 0.7 pF
(c) 0.35 fF
(d) 0.24 pF
Q. An ideal MOS capacitor (p-type semiconductor) is shown in the figure.
The MOS capacitor is under strong inversion with V G = 2V.
The corresponding inversion charge density (QIN) is 2.2 C/cm2. Assume
oxide capacitance per unit area as COX = 1.7 F/cm2. For VG = 4 V, the
value of QIN is ______ C/cm2 (rounded off to one decimal place)
( G ATE - 22)
Q. A one-sided abrupt pn junction diode has a depletion capacitance
CD of 50 pF at a reverse bias of 0.2V. The plot of 1/C2D versus the
applied voltage V for this diode is a straight line as shown in figure
below. The slope of the plot is ______  1020 F2 V1
(a)  5.7 1/CD2
(b) 0.4
(c) 1.2 V
0
(d) 3.8
Q. Consider an ideal long channel nMOSFET (enhancement-mode)
with gate length 10 m. The product of electron mobility (n) and
oxide capacitance per unit area (COX) is n Cox= 1mA/V2. The
threshold voltage of the transistor is 1V. For a gate-to-source
voltage VGS = [2  sin (2t)] V and drain-to source voltage VDS = 1V
(substrate connected to the source), the maximum value of the
drain-to-source current is _____
(a) 40 mA
(b) 20 mA
(c) 15 mA
(d) 5 mA
Q. An enhancement MOSFET of threshold voltage 3 V is being used in
the sample and hold circuit given below. Assume that the substrate
of the MOS device is connected to 10V. If the input voltage V1 lies
between  10V, the minimum and the maximum values of VG
required for proper sampling and holding respectively, are
(a) 13V and 7V V1 V0
(b) 10V and 13V
(c) 10V and 10V
VG
(d) 3V and 3V
Q. Consider a long-channel MOSFET with a channel length 1m and
width 10 mm. The device parameters are acceptor concentration
NA = 5  1016 cm3, electron mobility n = 800 cm2/V-s, oxide
capacitance/area Cox = 3.45 107 F/cm2, threshold voltage VT =
0.7V. The drain saturation current (Idsat) for a gate voltage of 5V is
________ mA (rounded off to two decimal places). [0 = 8.854
1014F/cm, si = 11.9]
Q. A CMOS inverter, designer to have a mid-point voltage V1 equal to
half of Vdd, as shown in the figure, has the following parameters:
Vdd = 3V
n Cox = 100 A/V2 ; Vm = 0.7V for nMOS
p Cox = 40 A/V2; |Vtp| = 0.9V for pMOS
The ratio of (W/L)n to (W/L)p is equal to _____(rounded off to 3
decimal places).
Vout
Vdd
Vdd/2
Vin
V1=Vdd/2 Vdd
Q. In the circuits shown, the threshold voltage of each nMOS
transistor is 0.6V. Ignoring the effect of channel length modulation
and body bias, the values of Vout1 and Vout2, respectively, in volts,
are
(a) 1.8 and 2.4 Vout
3V 
(b) 2.4 and 2.4 3V
(c) 1.8 and 1.2 
(d) 2.4 and 1.2

3V 3V
Vout
3V

Q. A depletion type N-channel MOSFET is biased in its linear region for use as a
voltage controlled resistor. Assume threshold voltage VTH = 0.5V, VGS = 2.0 V,
VDS = 5V, W/L = 100, COX = 108 F/cm2 and mn = 800 cm2/V-s. The value of the
resistance of the voltage controlled resistor (in W) is ______.
Consider a MOS capacitor made with p-type
silicon. It has an oxide thickness of 100 nm. A
fixed positive oxide charge of 10-8 C/cm2
at the
oxide-silicon interface, and a metal work function
of 4.6 eV. Assume that the relative permittivity of

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Q.

The band diagram of a p-type semiconductor with a band-gap of 1 eV

(b) 1.70  10-8 Ec

(d) 0.93  10-8 0.2 eV

(d) 2.4 and 1.2

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