EC4010Digital Design - Boolean Logic
EC4010Digital Design - Boolean Logic
logic gates.
Boolean algebra
• Contains variables, which take two discrete values (1 or 0).
• Binary logic.
• Consists of binary variables and a set of logical
operations.
2. Identity:
0 is an identityelementto “+”
1 is an identityelementto “-”
3. Commutative laws
𝑥+ 𝑦=𝑦 + 𝑥
𝑥 .𝑦 = 𝑦 .𝑥
4. Distributive laws
𝑥 " (𝑦 + 𝑧) = (𝑥 " 𝑦) + (𝑥 " 𝑧)
𝑥 + (𝑦 " 𝑧) = (𝑥 + 𝑦) " (𝑥 + 𝑧)
2. Theorem 2
𝑥+1 = 1
𝑥. 0 = 0
3. Theorem 3 (Involution)
𝑥! ! = 𝑥
4. Theorem 4 (Associative)
𝑥+ (𝑦 + 𝑧) = (𝑥+ 𝑦) + 𝑧
𝑥. 𝑦 𝑧 = 𝑥 𝑦 . 𝑧
5. Theorem 5 (DeMorgan)
(𝑥 + 𝑦)’ = 𝑥!𝑦′ (𝑥 + 𝑦) = 𝑥. 𝑦
(𝑥𝑦)!= 𝑥! + 𝑦!
𝑥. 𝑦 = 𝑥 + 𝑦
6. Theorem 6 (Absorption)
𝑥 + 𝑥𝑦 = 𝑥
𝑥 𝑥+𝑦= 𝑥
Postulates and Theorems
Logic Gates
𝒙 𝒚 𝒛 𝑭𝟏
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
Gate Level Implementation of Boolean
expression
• A Boolean expression can be represented by a circuit diagram.
• The gate level implementation of the Boolean expression 𝐹( is
given below.
𝐹= 𝑥 + 𝑦‘𝑧
Gate Level Implementation of Boolean
expression
𝐹+ = 𝑥‘𝑧 + 𝑥𝑦′
Truth table of Boolean expression
𝐹1 = 𝑥 + 𝑦‘𝑧
𝐹2= 𝑥‘𝑧 + 𝑥𝑦′
Exercise.
𝑎) 𝑥. 𝑥‘ + 𝑦 = 𝑥. 𝑥‘+ 𝑥. 𝑦 (𝑑𝑖𝑠𝑡𝑟𝑖𝑏𝑢𝑡𝑖𝑣𝑒)
= 0 + 𝑥. 𝑦(𝑐𝑜𝑚𝑝𝑙𝑒𝑚𝑒𝑛𝑡)
= 𝑥. 𝑦 (𝑖𝑑𝑒𝑛𝑡𝑖𝑡𝑦)
b) 𝑥 + 𝑥‘𝑦 = 𝑥 + 𝑥‘𝑦
= 𝑥 + 𝑥+ . 𝑥 + 𝑦 𝑑𝑖𝑠𝑡𝑟𝑖𝑏𝑢𝑡𝑖𝑣𝑒
= 1. x + y complement
= x + y (identity)
Canonical and standard forms.
Minterms
𝒙 𝒚 𝒛
Term Designation
0 0 0 𝑥*𝑦*𝑧′ 𝑚0
0 0 1 𝑥 * 𝑦* 𝑧 𝑚1
0 1 0 𝑥*𝑦𝑧′ 𝑚2
0 1 1 𝑥*𝑦𝑧 𝑚3
1 0 0 𝑥𝑦′𝑧′ 𝑚4
1 0 1 𝑥𝑦′𝑧 𝑚5
1 1 0 𝑥𝑦𝑧′ 𝑚6
1 1 1 𝑥𝑦𝑧 𝑚7
Minterms and Maxterms.
Minterms and maxterms of three binary variables, x, y,
and z.
Maxterms
𝒙 𝒚 𝒛
Term Designation
0 0 0 𝑥+𝑦+𝑧 𝑀0
0 0 1 𝑥 + 𝑦 + 𝑧′ 𝑀1
0 1 0 𝑥 + 𝑦* + 𝑧 𝑀2
0 1 1 𝑥 + 𝑦* + 𝑧′ 𝑀3
1 0 0 𝑥* + 𝑦 + 𝑧 𝑀4
1 0 1 𝑥* + 𝑦 + 𝑧′ 𝑀5
1 1 0 𝑥* + 𝑦* + 𝑧 𝑀6
1 1 1 𝑥* + 𝑦* + 𝑧′ 𝑀7
Sum of minterms
Maxterms
Minterms
Minterms
𝐴+𝐵+𝐶+ 𝐴𝐵+𝐶++ 𝐴𝐵+𝐶 +
𝐹𝐴,𝐵,𝐶 = 𝐴𝐵𝐶+ + 𝐴𝐵𝐶
𝐹𝐴,𝐵,𝐶 = A + B + C (A++ B + C′)(A+ + B + C)
Maxterms
Design circuit
𝐹( = 𝑦) + 𝑥)𝑦𝑧) + 𝑥𝑦
Design circuit
• Fan-out
• Number of standard loads that the output of a typical gate that can drive
without impairing its normal operation.
• Fan-in
• The number of inputs available in a gate.
• Power dissipation
• The power consumed by the gate.
• Propagation delay
• The average transition delay time for a signal to propagate from input to
output.
• Noise margin
• The maximum external noise voltage added to an input signal that does not
cause an undesirable change in the circuit output.
Integrated circuits
• Various circuits are interconnected inside the chip to create the required
circuit.
• External pins are welded with the circuit, which may range from low
number to several thousands.
Levels of Integration.
NOT gate
DL OR Gate
Schematic, and truth table DL OR gate
X Y Z
0 0 0
0 1 1
1 0 1
1 1 1
TTL NOT Gate
Schematic of TTL NOT gate
RTL NOR Gate
Schematic, and truth table RTL NOR gate
X Y Z
0 0 1
0 1 0
1 0 0
1 1 0
TTL NAND Gate
Schematic of TTL NAND gate