Tamkang University Examination Paper (Academic Year: 112 Semester: 1 Exam: Midterm Graduation Final）

Course Title: Computer Organization Class No. Code: E0334

Test Date: 11/10 (mm/dd), 3 （period） Class Instructor： Hung, Fu-Yi Total pages: 6
Please mark what is allowed to bring in:  Calculators  Textbooks  Notebooks  Electronic dictionary  Dictionary  Other:

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Multiple-choice Questions (100%)

( D )1. (7%) The five classic components of a computer are .
(A) memory, input, output, central processing unit, and datapath
(B) central processing unit, memory, input, output, and control
(C) input, output, central processing unit, datapath, and control
(D) control, datapath, memory, input, and output
(Question 2~3) Consider the following MIPS loop:
LOOP: slt $t2, $0, $t1
beq $t2, $0, DONE
subi $t1, $t1, 1
addi $s2, $s2, 1
j LOOP
DONE:
( D ) 2. (7%) Assume that the register $t1 is initialized to the value 10. What is the value in register $s2
assuming $s2 is initially zero?
(A) 30 (B) 20 (C) 15 (D) 10
( B ) 3. (7%) Assume that the registers $s1, $s2, $t1, and $t2 are integers A, B, i, and temp, respectively.
What is the corresponding C code?
(A) (B) (C) (D)
i = 15; i = 15; i = 15; i = 15;
While (i < 0) { While (i > 0) { do { do {
i = i – 1; i = i – 1; i = i – 1; i = i – 1;
B += 1; B += 1; B += 1; B += 1;
} } } while (i < 0) } while (i > 0)
(Question 4~6) Consider three different processors P1, P2, and P3 executing the same instruction set.
P1 has a 4.0 GHz clock rate and a CPI of 2.2.
P2 has a 3.0 GHz clock rate and a CPI of 1.5.
P3 has a 2.5 GHz clock rate and a CPI of 1.0.
( C ) 4. (7%) Which processor has the highest performance expressed in instructions per second?
(A) P1 (B) P2
(C) P3 (D) They have the same performance
( A ) 5. (7%) If the processor P2 executes a program in 10 seconds, the number of instructions is .
(A) 20 x 10E9 (B) 25 x 10E9
(C) 30 x 10E9 (D) 45 x 10E9
( B ) 6. (7%) We are trying to reduce the execution time by 30% but this leads to an increase of 20% in the
CPI. What clock rate of the processor P2 should we have to get this time reduction?
(A) 4.28 GHz (B) 5.14 GHz
(C) 6.75 GHz (D) 7.42 GHz
( B ) 7. (7%) Two integers A (11011001two) and B (01010011two) are stored in an 8-bit two’s complement
format. If C = A – B, what is C? Does an overflow occur?
(A) C = 10000110, an overflow occurs (B) C = 10000110, no overflow
(C) C = 110000110, an overflow occurs (D) C = 110000110, no overflow

Attention: 1. For fairness and justice, students should be self-disciplined to maintain school’s and students’ honor.
2. Chatting, taking examination papers out, peeping, and other misconduct are prohibited during the
examination. Violators will be seriously punished.
ATRX-Q03-001-FM256-01
( C ) 8. (7%) Supposed the program counter (PC) is set to 0x2000 2000. Is it possible to use the jump (j) and
branch-on-equal (beq) MIPS assembly instructions to set the PC to the address 0x2000 0000?
(A) jump – yes, beq – no (B) jump – no, beq – no
(C) jump – yes, beq – yes (D) jump – no, beq – yes
( D ) 9. (7%) Multiply 10ten x 11ten (1010two x 1011two) using the hardware described in Figure-1. Assume
these two numbers are unsigned 4-bit integers. What is the value in the Product field in Table-1 after
the 2nd iteration?
(A) P2 = 0101 0101 (B) P2 = 0111 0101
(C) P2 = 0101 1010 (D) P2 = 0111 1010
( A ) 10. (7%) In which of the following situations does an overflow never occur?
(A) Adding a negative integer to a positive integer
(B) Subtracting a negative integer from a positive integer
(C) Adding a negative integer to a negative integer
(D) Subtracting a positive integer from a negative integer
(Question 11~12) For the following C statement:
int leaf_example (int g, int h, int i, int j)
{
int f;
f = (g + h) – (i + j);
return f;
}
The parameter variables g, h, i, and j correspond to the argument registers $a0, $a1, $a2, and $a3, and
f corresponds to $s0. Please finish the MIPS assembly code for this C segment.
MIPS code:
X # adjust stack to make room for 1 items
Y # save register $s0 for use afterwards
add $t0,$a0,$a1 # register $t0 contains g + h
add $t1,$a2,$a3 # register $t1 contains i + j
sub $s0,$t0,$t1 # f = $t0 – $t1, which is (g + h)–(i + j)
add $v0,$s0,$zero # returns f ($v0 = $s0 + 0)
Z # restore register $s0 for caller
W # adjust stack to delete 1 items
jr $ra # jump back to calling routine
( A ) 11. (8%) What are the MIPS assembly codes in the blank X and W?
(A) X: addi $sp, $sp, –4 (B) X: addi $sp, $sp, –2
W: addi $sp, $sp, 4 W: addi $sp, $sp, 2
(C) X: sll $sp, $sp, 4 (D) X: sll $sp, $sp, 2
W: srl $sp, $sp, 4 W: srl $sp, $sp, 2

( B ) 12. (8%) What are the MIPS assembly codes in the blank Y and Z?
(A) Y: lw $s0, 0($sp) (B) Y: sw $s0, 0($sp)
Z: sw $s0, 0($sp) Z: lw $s0, 0($sp)
(C) Y: lw $s0, 4($sp) (D) Y: sw $s0, 4($sp)
Z: sw $s0, 4($sp) Z: lw $s0, 4($sp)
( A ) 13. (7%) Which of the following is the MIPS instruction of the binary value: 0000 0000 0001 0000
0101 0001 0000 0000
(A) sll $t2, $s0, 4 (B) add $s0, $t2, $0
(C) sll $t2, $s0, 2 (D) add $0, $s0, $t2
( C ) 14. (7%) Divide 11ten by 2ten (1011two / 0010two) using the hardware described in Figure-2. Assume these
two numbers are unsigned 4-bit integers. What is the value in the Quotient and Remainder fields in
Table-2 after 3rd iteration?
(A) Q3 = 0010; R3 = 0000 0011 (B) Q3 = 0010; R3 = 0000 0001
(C) Q3 = 0001; R3 = 0000 0011 (D) Q3 = 0001; R3 = 0000 0001

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 Figure-1
Table-1
Multiplicand
Iteration Step Product (& Multiplier)
(Mcand)
0 Initial values 1 0 1 0 0 0 0 0 1 0 1 1
1a: M0 = 1 → Prod(LH) = Prod(LH) + Mcand
1
1b: M0 = 0 → No operation
2: Shift right product
1a: M0 = 1 → Prod(LH) = Prod(LH) + Mcand
2
1b: M0 = 0 → No operation
2: Shift right product P2 = ?
⚫ M0 = Rightmost bit of the Product (& Multiplier) register
⚫ Prod(LH) = Left-Hand side of the Product (& Multiplier) register

Figure-2
Table-2
Iter Step Quotient Divisor Remainder
0 Initial values 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 1

1 1: rem = rem - div 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 0 1 0 1 1

2a: rem>=0 → sll Q, Q0= 1
0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 1
2b: rem<0 → +div, sll Q, Q0= 0
3: shift div right 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 1

2 1: rem = rem - div

2a: rem>=0 → sll Q, Q0= 1
2b: rem<0 → +div, sll Q, Q0= 0
3: shift div right
3 1: rem = rem - div
2a: rem>=0 → sll Q, Q0= 1
2b: rem<0 → +div, sll Q, Q0= 0
3: shift div right Q3 = ? R3 = ?

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◼ CPU (Execution) Time
= CPU Clock Cycles  Clock Cycle Time
= CPU Clock Cycles / Clock Rate
= Instruction Count (IC)  Cycles per Instruction (CPI)  Clock Cycle Time
= Instruction Count (IC)  Cycles per Instruction (CPI) / Clock Rate

◼ If different instruction classes take different numbers of cycles

n
◼ Clock Cycles =  (CPI i  Instruction Count i )
i =1

Clock Cycles n
 Instruction Count i 
◼ Weighted average CPI = =   CPI i  
Instruction Count i =1  Instruction Count 

◼ MIPS (Millions of Instructions Per Second)

Instruction count Instruction count Clock rate
MIPS = = =
Execution time  10 6
Instruction count  CPI CPI  106
 106
Clock rate
◼ Amdahl’s Law:
Execution time after improvement
Execution time affected by improvement
= + Execution time unaffected
Amount of improvement

◼ Execution time before improvement

Speedup =
Execution time after improvement

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 Category Instruction Format Syntax Example Meaning

add R add rd, rs, rt add $s1, $s2, $s3 $s1＝$s2＋$s3

subtract R sub rd, rs, rt sub $s1, $s2, $s3 $s1＝$s2－$s3

Arithmetic
add immediate I addi rt, rs, immediate addi $s1, $s2, 20 $s1＝$s2＋20

add unsigned R addu rd, rs, rt addu $s1, $s2, $s3 $s1＝$s2＋$s3

load word I lw rt, offset(rs) lw $s1, 20($s2) $s1＝Memory[$s2＋20]

store word I sw rt, offset(rs) sw $s1, 20($s2) Memory[$s2＋20]＝$s1

load half unsigned I lhu rt, offset(rs) lhu $s1, 20($s2) $s1＝Memory[$s2＋20]
Data transfer
store half I sh rt, offset(rs) sh $s1, 20($s2) Memory[$s2＋20]＝$s1
load byte
I lbu rt, offset(rs) lbu $s1, 20($s2) $s1＝Memory[$s2＋20]
unsigned
store byte I sb rt, offset(rs) sb $s1, 20($s2) Memory[$s2＋20]＝$s1

AND R and rd, rs, rt and $s1, $s2, $s3 $s1＝$s2 & $s3

AND immediate I andi rt, rs, immediate andi $s1, $s2, 100 $s1＝$s2 & 100

OR R or rd, rs, rt or $s1, $s2, $s3 $s1＝$s2 ｜ $s3

OR immediate I ori rt, rs, immediate ori $s1, $s2, 100 $s1＝$s2 ｜ 100

Logical NOR R nor rd, rs, rt nor $s1, $s2, $s3 $s1＝ ~ ($s2 ｜ $s3)

XOR R xor rd, rs, rt xor $s1, $s2, $s3 $s1＝$s2 ^ $s3

shift left logical R sll rd, rt, shamt sll $s1, $s2, 10 $s1＝$s2 << 10

shift right logical R srl rd, rt, shamt srl $s1, $s2, 10 $s1＝$s2 >> 10
Shift right
R sra rd, rt, shamt sra $s1, $s2, 10 $s1＝$s2 >> 10
arithmetic
if ($s1＝＝$s2)
branch on equal I beq rs, rt, offset beq $s1, $s2, 25
go to (PC＋4＋100)
branch on not if ($s1!＝$s2)
I bne rs, rt, offset bne $s1, $s2, 25
equal go to (PC＋4＋100)
Conditional if ($s2 < $s3) $s1＝1;
set on less than R slt rd, rs, rt slt $s1, $s2, $s3
branch else $s1＝0
set less than if ($s2 < 100) $s1＝1;
I slti rt, rs, immediate slti $s1, $s2, 100
immediate else $s1＝0
set less than if ($s2 < $s3) $s1＝1;
R sltu rd, rs, rt sltu $s1, $s2, $s3
unsigned else $s1＝0

jump J j target_address j 2500 go to 10000

Unconditional
jump and link J jal target_address jal 2500 $ra＝PC＋4; go to 10000
jump
jump register R jr rs jr $ra go to $ra