Tamkang University Examination Paper (Academic Year: 112 Semester: 1 Exam: Midterm Graduation Final）

Course Title: Computer Organization Class No. Code: E0334

Test Date: 12/29 (mm/dd), 4 （period） Class Instructor： Hung, Fu-Yi Total pages: 4
Please mark what is allowed to bring in:  Calculators  Textbooks  Notebooks  Electronic dictionary  Dictionary  Other:

Name: Student No. :

(姓名) (學號)

Multiple-choice Questions (100%)

( D ) 1. Which of the following statements is generally wrong?
(A) Memory hierarchies take advantage of spatial locality.
(B) Most of the capacity of the memory hierarchy is at the lowest level.
(C) Memory hierarchies take advantage of temporal locality.
(D) The larger the cache block, the shorter the memory latency.
( C ) 2. We have a program code consisting of eight conditional branches. The branch outcomes are
N, N, T, T, T (T for taken, N for not taken). What is the accuracy of always-taken predictors
for this sequence of branch outcomes?
(A) 20% (B) 40%
(C) 60% (D) 80%
(Questions 3~5) A direct-mapped cache contains 128 blocks, and a block size of 64 bytes. (one address per byte)
( C ) 3. What is the size of the index?
(A) 5 bits (B) 6 bits
(C) 7 bits (D) 8 bits
( A ) 4. What is the size of the tag?
(A) 19 bits (B) 20 bits
(C) 21 bits (D) 22 bits
( B ) 5. To what block number does byte address 1200 map? [ 1200 (in decimal) = 0000 0000 0000 0000
0000 0100 1011 0000 (in binary) ]
(A) 9ten (B) 18ten
(C) 37ten (D) 75ten
( A ) 6. If a pipelined processor has 6 stages and takes 100 ns to execute N instructions. How long will it
take to execute 2N instructions, assuming the clock rate is 500 MHz and no pipeline stalls occur?
(ns = 10−9 second; MHz = 106 Hz)
(A) 190 ns (B) 200 ns
(C) 192 ns (D) 202 ns
( C ) 7. Increasing the degree of associativity of a cache scheme will decrease
(A) the number of comparators. (B) the number of tag bits.
(C) the miss rate. (D) the hit time
( D ) 8. In a pipelined processor, a control hazard may be reduced by
(A) Stall, forwarding, and delay branch (B) Stall, forwarding, and reordering instructions
(C) Stall and hardware duplication (D) Stall, delay branch, and prediction

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Attention: 1. For fairness and justice, students should be self-disciplined to maintain school’s and students’ honor.
2. Chatting, taking examination papers out, peeping, and other misconduct are prohibited during the
examination. Violators will be seriously punished.
ATRX-Q03-001-FM256-01
(Questions 9~10) Execute the following sequence of instructions in a five-stage pipelined processor.
I1 (Instruction 1): lw $t1, 40($t6)
I2 (Instruction 2): add $t6, $t2, $t2
I3 (Instruction 3): sw $t6, 20($t1)
Assume the following cycle times for each of the options related to forwarding:
Without Forwarding With Full Forwarding With ALU-ALU Forwarding Only
200 ps 300 ps 250 ps

9. (8%) What is the total execution time of this instruction sequence without forwarding?

10. (8%) What is the total execution time of this instruction sequence with full forwarding?
(Questions 11~12) Consider a 2-way set associative cache with eight one-word blocks as shown in Figure 1.
Assume that the cache is initially empty. Use least recently used (LRU) replacement. The memory
access sequence in block address is 0, 8, 6, 0, 8, and 6.
( B ) 11. For the second reference to the block address 8 as shown in Figure 1, find the tag (X1) and
the index (Y1).
(A) X1 = 0000100, Y1 = 0 (B) X1 = 000010, Y1 = 00
(C) X1 = 00001, Y1 = 000 (D) X1 = 0000, Y1 = 1000
( A ) 12. How many misses does this address sequence exhibit?
(A) 3 (B) 4
(C) 5 (D) 6
( A ) 13. According to the single-cycle MIPS implementation in Figure 4.24, if the input of the sign-extend is
1000 1000 1000 1000 (in binary), what is the output?
(A) 1111 1111 1111 1111 1000 1000 1000 1000
(B) 0000 0000 0000 0000 1000 1000 1000 1000
(C) 1000 1000 1000 1000 0000 0000 0000 0000
(D) 1000 1000 1000 1000 1000 1000 1000 1000
( B ) 14. Referring to Figure 4.24, assume that data memory is all zeros and that the processor’s registers have
the following values at the beginning of the cycle in which the following instruction word is fetched:
beq $22, $23, 40. Which of the following is wrong?
$0 $16 $17 $18 $19 $20 $21 $22 $23 $24
0 2 44 25 14 200 8 25 25 32
(A) The input value for “Read register 1” of the “Registers” unit is 22.
(B) The new PC address for the next instruction is (PC + 4) + 40.
(C) The output values for “ALU result” of the “ALU” unit is 0.
(D) The output value for “Read data 2” of the “Registers” unit is 25.

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 APPENDIX

Figure 1
Address of memory
Tag Index Hit/ Cache content
block accessed
Decimal Binary (Binary) (Binary) Miss Set 0 Set 0 Set 1 Set 1 Set 2 Set 2 Set 3 Set 3
0 00000000
8 00001000 X1 Y1
6 00000110
0 00000000
8 00001000
6 00000110

◼ Total execution time (T) for N instructions in a K-stages pipelined processor (no pipeline stall):
◼ T = [ K + (N – 1)]  (Clock cycle time for the pipelined processor)
◼ Address subdivision in a direct mapped cache:
◼ The size of offset field: X = log2 ( Number of addresses in a block )
◼ The size of index field: Y = log2 ( Number of blocks or sets in the cache )
◼ The size of tag field: Z = 32 – X – Y
◼ Direct mapped cache:
◼ Block address in memory =  Address in memory / Number of addresses in a block 
◼ Block number in cache = (Block address in memory) modulo (Number of blocks in the cache)

FIGURE 2.18 MIPS instruction formats

Name Fields
Field size 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
R-format op rs rt rd shamt funct
I-format op rs rt address(offset) / immediate (16 bits)
J-format op target address (26 bits)

MIPS assembly language

Category Instruction Format Syntax Example Meaning
add R add rd,rs,rt add $s1,$s2,$s3 $s1＝$s2＋$s3
Arithmetic
subtract R sub rd,rs,rt sub $s1,$s2,$s3 $s1＝$s2－$s3
load word I lw rt,offset(rs) lw $s1,20($s2) $s1＝Memory[$s2＋20]
Data transfer
store word I sw rt,offset(rs) sw $s1,20($s2) Memory[$s2＋20]＝$s1
AND R and rd,rs,rt and $s1,$s2,$s3 $s1＝$s2 & $s3
Logical
OR R or rd,rs,rt or $s1,$s2,$s3 $s1＝$s2 ｜ $s3
Conditional branch on equal I beq rs,rt,offset beq $s1,$s2,25 if ($s1＝＝$s2) go to (PC＋4)＋(254)
branch set on less than R slt rd,rs,rt slt $s1,$s2,$s3 if ($s2<$s3) $s1＝1; else $s1＝0
Unconditional
jump
jump J j target_address j 2500 go to 10000

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 MIPS 5-satge Pipeline: Read and Write Operations on Registers and Memories
IF ID EX MEM WB
R-format IF & (PC+4) Read data from rs & rt Operates the data Write data into rd
lw IF & (PC+4) Read data from rs Base address + offset Read data from memory Write data into rt
sw IF & (PC+4) Read data from rs & rt Base address + offset Write data into memory
(rs – rt) and
beq IF & (PC+4) Read data from rs & rt
(PC+4)+(offset x 4)

Figure 4.24

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