Quiz 2

112-1 Computer Organization

Name Student ID No.

(姓名) (學號)

Multiple choices and fill in the blanks (100%)

( B ) 1. According to the single-cycle MIPS implementation in Figure 4.24,
which of the following instructions requires the resource “sign-extend”?
(A) slt (set on less than) (B) beq (branch on equal)
(C) add (addition) (D) all of them
( A ) 2. Which of the following is true about pipelining?
(A) It increases the instruction throughput rather than reduces the individual instruction latency.
(B) It increases the instruction throughput and reduces the individual instruction latency.
(C) It reduces the individual instruction latency rather than increases the instruction throughput.
(D) It cannot reduce the individual instruction latency, nor increases the instruction throughput.
(Questions 3~4) Execute the following sequence of instructions in a five-stage pipelined processor.
I1 (Instruction 1): lw $t1, 40($t6)
I2 (Instruction 2): add $t6, $t2, $t2
I3 (Instruction 3): sw $t6, 20($t1)
( A ) 3. Which of the following statement is wrong?
(A) WAR(Write After Read) data dependence on $t6 from I1 to I3 instruction
(B) RAW(Read After Write) data dependence on $t6 from I2 to I3 instruction
(C) WAR(Write After Read) data dependence on $t6 from I1 to I2 instruction
(D) RAW(Read After Write) data dependence on $t1 from I1 to I3 instruction
( B ) 4. How many data hazard(s) does (do) occur in this instruction sequence?
(A) 1 (B) 2
(C) 3 (D) 4
( D ) 5. Which of the following is not a state element?
(A) Program counter (B) Register
(C) data memory (D) Multiplexor
(Questions 6~8) The following figure shows the time required for each of the instructions.
Instruction Register ALU Data Register
fetch read operation access write
R-format (add) 300 ps 250 ps 200 ps 250 ps
Load word (lw) 300 ps 250 ps 200 ps 400 ps 250 ps
Store word (sw) 300 ps 250 ps 200 ps 400 ps
Branch (beq) 300 ps 250 ps 200 ps
6. What is the clock cycle time (X1) in a pipelined implementation? 400 ps

X1 = ps
7. What is the execution time (X2) of an add instruction in a pipelined implementation? 2000 ps

X2 = ps
8. What is the total execution time (X3) in a pipelined implementation for the following three
instructions: lw, add, beq? 2800 ps

X3 = ps

1
 ( A ) 9. Referring to Figure 4.24, assume that data memory is all zeros and that the processor’s registers
have the following values at the beginning of the cycle in which the following instruction word is
fetched: lw $21, 24($20). Which of the following is wrong?
$0 $16 $17 $18 $19 $20 $21 $22 $23 $24
0 2 44 25 14 200 8 25 25 32
(A) The input value for “Write data” of the “Registers” unit is 8.
(B) The output value for “Read data 2” of the “Registers” unit is 8.
(C) The input values of the “ALU” unit is 200 and 24.
(D) The input value for “Read register 1” of the “Registers” unit is 20.
( C ) 10. Referring to Figure 4.24, assume that data memory is all zeros and that the processor’s registers
have the following values at the beginning of the cycle in which the following instruction word is
fetched: add $17, $18, $19. Which of the following is wrong?
$0 $16 $17 $18 $19 $20 $21 $22 $23 $24
0 2 44 25 14 200 8 25 25 32
(A) The input value for “Read register 2” of the “Registers” unit is 19.
(B) The output value for “Read data 1” of the “Registers” unit is 25.
(C) The input value for “Write data” of the “Data memory” unit is 14.
(D) The input value for “Write data” of the “Registers” unit is 39.

MIPS assembly language

Category Instruction Format Syntax Example Meaning
add R add rd,rs,rt add $s1,$s2,$s3 $s1＝$s2＋$s3
Arithmetic
subtract R sub rd,rs,rt sub $s1,$s2,$s3 $s1＝$s2－$s3
load word I lw rt,offset(rs) lw $s1,20($s2) $s1＝Memory[$s2＋20]
Data transfer
store word I sw rt,offset(rs) sw $s1,20($s2) Memory[$s2＋20]＝$s1
AND R and rd,rs,rt and $s1,$s2,$s3 $s1＝$s2 & $s3
Logical
OR R or rd,rs,rt or $s1,$s2,$s3 $s1＝$s2 ｜ $s3
Conditional branch on equal I beq rs,rt,offset beq $s1,$s2,25 if ($s1＝＝$s2) go to (PC＋4)＋(254)
branch set on less than R slt rd,rs,rt slt $s1,$s2,$s3 if ($s2<$s3) $s1＝1; else $s1＝0
Unconditional
jump J j target_address j 2500 go to 10000
jump

FIGURE 2.18 MIPS instruction formats

Name Fields
Field size 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
R-format op rs rt rd shamt funct
I-format op rs rt address(offset) / immediate (16 bits)
J-format op target address (26 bits)

2
 MIPS 5-satge Pipeline: Read and Write Operations on Registers and Memories
IF ID EX MEM WB
IF and Read data from rs Write data
R-format Operates the data
(PC+4) and rt into rd
IF and Read data from Write data
lw Read data from rs Base address + offset
(PC+4) memory into rt
IF and Read data from rs Write data into
sw Base address + offset
(PC+4) and rt memory
IF and Read data from rs (rs – rt) and
beq
(PC+4) and rt (PC+4)+(offset x 4)

Figure 4.24