Digital Logic

0907231

Adapted from Dr. Bassam Kahhaleh’ Slides by Prof. Iyad Jafar

 Chapter 5
Combinational
Functional Blocks
Outline
★ Introduction

★ General Concepts

★ Line Decoders

★ Encoders

★ Multiplexors

★ Demultiplexors

2
Introduction
Functions and Functional Blocks
★ The functions considered are those found to be very
useful in design

★ Each of the functions is a combinational circuit

implementation called a functional block

★ In the past, functional blocks were packaged as

small-scale-integrated (SSI), medium-scale integrated
(MSI), and large-scale-integrated (LSI) circuits

★ Today, they are often simply implemented within a

very-large-scale-integrated (VLSI) circuit
4
General Concepts
Rudimentary Logic Functions
★ Functions of one variable Functions of One Variable

★ Four possibilities
0 0 1 0 1
1 0 1 1 0

● Value fixing to 1

● Value fixing to 0

● Transferring

● Inverting
6
Enabling Functions
★ Control when the input is allowed to affect the
output using CONTROL/ENABLE signal
★ Using AND gate

★ Using OR gate

7
BUS
★ Collection of wires carrying information
★ Notation

A0 A0
A1 4 4 A1
A
A2 A2
A3 A3

8
Line Decoders
Decoders
★ An n-to-m line decoder is a CLC that converts an
n-bit code to m-bit code such that
● m ≤ 2n
● One of the outputs is active for any possible input value

D3 0

Decoder
D3 0
Decoder

0 A1

2-to-4
A1
2-to-4

0 D2 0 D2 0
D1 0 1 D1 1
0 A0 A0
D0 1 D0 0

D3 0 1
Decoder

D3

Decoder
A1
2-to-4

1 1 A1

2-to-4
D2 1 D2 0
D1 0 D1 0
0 A0 1 A0
D0 0 D0 0
10
Decoders
★ Enable one out of m things! Only one
lamp will
turn on

0 1
x1 0
Binary
x0 0 Decoder 0
0

11
1-to-2 Line Decoder

Decoder
D1 D1 D0
1-to-2
A 0 0 1
D0 1 1 0

D1(A) = A
D0 (A) =
A’

12
2-to-4 Line Decoder

y3

Decoder
I1
Binary y2
y1
I0 y0

I1 I0 Y3 Y2 Y1 Y0
0 0 0 0 0 1
0 1 0 0 1 0 = m3 = m2
1 0 0 1 0 0
1 1 1 0 0 0 = m1 = m0
13
Decoders
★ 2-to-4 Decoder is two 1-to-2
decoders and four 2-input
AND gates = m3

= m2

★ Generally, we can build an = m1

n-to-m line decoders using
= m0
● n 1-to-2 line decoders
● m n-input AND gates
● Each output is a minterm

14
3-to-8 Line Decoder

= m7
= m6
Y7
= m5
Y6
Y5 = m4
Decoder
Binary

I2 Y4
= m3
I1 Y3
I0 Y2 = m2
Y1 = m1
Y0
= m0

15
Exercise

★ Draw the logic diagram of 4-to-16 decoder

16
 Decoders with Output Enable
★ Sometime, we might need to disable the decoder
output, i.e. input has no effect on the output
E A D1 D0
0 0
D0 0 1
Decoder

D0
1-to-2

1 0
A A 1 1
D1
D1

Decoder
A D0

Binary
E D1
Enable
17
Decoders with Output Enable
★ “Enable” Control
Y3

Decoder
A1
Binary Y2
A0 Y1
E Y0

E I1 I0 Y3 Y2 Y1 Y0
0 x x 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
18
Building Large Decoders from Smaller Ones
★ We can use decoders with output enable to build
larger decoders
★ 2-to-4 Decoder using 1-to-2 decoders

Decoder
I0 A D0 Y0

1-to-2
E D1 Y1
I1 I0 Y3 Y2 Y1 Y0
0 0 0 0 0 1

Decoder
I1 A D0
0 1 0 0 1 0 1-to-2
?? E D1
1 0 0 1 0 0 I0

Decoder
A D0

1-to-2
1 1 1 0 0 0
E D1
Y2
Y3
19
Building Large Decoders from Smaller Ones
★ 3-to-8 Decoder A2 A1 A0

A 2 A1 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
A0 D0 Y0
I0

Decoder
Binary
0 0 0 0 0 0 0 0 0 0 1 D1 Y1
0 0 1 0 0 0 0 0 0 1 0 I1 D2 Y2
0 1 0 0 0 0 0 0 1 0 0 E D3 Y3
0 1 1 0 0 0 0 1 0 0 0
1 0 0 0 0 0 1 0 0 0 0 D0
1 0 1 0 0 1 0 0 0 0 0 I0 Y4

Decoder
Binary
D1
1 1 0 0 1 0 0 0 0 0 0 I1 Y5
D2
1 1 1 1 0 0 0 0 0 0 0 E Y6
D3
Y7
20
Exercise
★ Build 3-to-8 decoder using a single 2-to-4 decoder and as
many as you need of 1-to-2 decoders

A 2 A1
A0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

21
Exercise
★ Build 3-to-6 decoder using 2-to-4 decoders

A 2 A1
A0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

22
Active-high and Active-low Output
★ Active-High / Active-Low
How about adding an
enable to this decoder?
I1 I0 Y 3 Y 2 Y 1 Y 0 I1 I0 Y 3 Y 2 Y 1 Y 0
0 0 0 0 0 1 0 0 1 1 1 0
0 1 0 0 1 0 0 1 1 1 0 1
1 0 0 1 0 0 1 0 1 0 1 1
1 1 1 0 0 0 1 1 0 1 1 1

M3
Y3 Y3
Decoder

Decoder
Binary

Binary

I1 Y2 I1 Y2 M2
M1
Y1 Y1
I0 Y0 I0 Y0 M0

23
Implementation Functions Using Decoders
★ Decoders, with active-high output, are minterm
generators, i.e. each output is a minterm

★ To implement a function of n variables and k

minterms as SOM using
● n-to-m decoder
● k-input OR gate
● Wire the decoders output(s) that correspond to the
minterms to the OR gate

24
Example 8
★ Implement the following two functions using
active-high decoders
S(x, y, z) = ∑(1, 2, 4, 7) Y7 ● ●
C(x, y, z) = ∑(3, 6, 7) Y6 ●

Binary Decoder
Y5
x I2 Y4 ●
y I1 Y3 ●
z I0 Y2 ●
Y1 ●
Y0

25
Example 8 - Continued
★ Using active-low decoders
S(x, y, z) = ∑(1, 2, 4, 7)
= ∏(0, 3, 5, 6)

●
C(x, y, z) = ∑(3, 6, 7)
● ● = ∏(0, 1, 2, 4, 5)
●
●
●
●
● ●

26
Example 9
F(w,x,y,z) = w’x’yz’+ w’x’yz + w’xy’z’ + wxy’z’ + wxy’z
F(w,x,y,z) = ∑(2,3,4,12,13)

z
y
F(w,x,y,z)
x
w

27
Example 10
★ Given the following circuit, then
F(A,B,C) = ∑( )

A B C F
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

28
Exercise
★

0 0 0 1 1
0 0 1 1 0
0 1 0 0 0
0 1 1 0 0
1 0 0 0 0
1 0 1 0 0
1 1 0 1 0
1 1 1 0 1

29
Real Stuff
★ 74HC139
★ Dual 2-to-4 line decoder/demultiplexer

30
Encoders
Encoders
★ An m-to-n encoder is a CLC that performs the
reverse operation of decoder such that
● m ≤ 2n
● It is assumed that one of the inputs is active

0 D3 0 D3

Encoder
Encoder

A1 0 A1 0

4-to-2
4-to-2

0 D2 0 D2
0 D1 1 D1
A0 0 A0 1
1 D0 0 D0

0 D3 1 D3

Encoder
Encoder

A1 1

4-to-2
A1 1
4-to-2

1 D2 0 D2
0 D1 0 D1 1
A0 0 A0
0 D0 0 D0
32
Encoders
★ Put “Information” into code
Only one
switch
x0 should be
activated
at a time
x1
y1
Binary x3 x2 x1 x0 y1 y0
x2 Encoder
y0 0 0 0 1 0 0
0 0 1 0 0 1
x3 0 1 0 0 1 0
1 0 0 0 1 1

33
2-to-1 Encoder

D1 D0 A V

Encoder
D1 2-to-1 0 0 X 0
A
0 1 0 1
D0 V
1 0 1 1
1 1 X 0

D0 D0
X 0 0 1

D1 1 X D1 1 0

34
4-to-2 Encoder

Y3Y2Y1Y0 I1 I0 V
0 0 0 0 X X 0 Y3 I1

Encoder
Binary
0 0 0 1 0 0 1 Y2
0 0 1 0 0 1 1 Y1 I0
0 0 1 1 X X 0
Y0 V
0 1 0 0 1 0 1
0 1 0 1 X X 0
0 1 1 0 X X 0 I1 = Y 3 + Y 2
0 1 1 1 X X 0
1 0 0 0 1 1 1 I0 = Y 3 + Y 1
1 0 0 1 X X 0
1 0 1 0 X X 0
1 0 1 1 X X 0 V = ∑ (1,2,4,8)
1 1 0 0 X X 0
1 1 0 1 X X 0
1 1 1 0 X X 0
1 1 1 1 X X 0
35
Priority Encoder
★ More than one active input?
★ Give priority to one of them!

0 D3 0 D3

Encoder
Encoder

A1 1 A1 0

4-to-2
4-to-2

1 D2 1 D2
0 D1 0 0 D1 0
1 A0 1 D0 A0
D0

High priority Encoder Low priority Encoder

D3 > D2 > D1 > D0 D0 > D1 > D2 > D3

36
Priority Encoders
★ 4-to-2 High Priority Encoder
I3

Encoder
V

Priority
I3 I2 I1 I0 Y1 Y0 V I2 Y1
0 0 0 0 0 0 0 I1 Y0
0 0 0 1 0 0 1 I0
0 0 1 x 0 1 1
0 1 x x 1 0 1
1 x x x 1 1 1
Y1 I1

1 1 1 1
I2
1 1 1 1
I3
1 1 1 1
I0

37
Exercise
★ Design 4-to-2 low priority encoder
Y3 Y2 Y1 Y0 I1 I0 V

I1 =
I0 =
V= 38
Exercise
★ Derive the compact truth table for 6-to-3 high
priority encoder
I2 =
Y5 Y4 Y3 Y2 Y1 Y0 I2 I1 I0 V
I1 =
I0 =
V=

39
Encoder / Decoder Pairs

Binary Binary
Encode Decode
r r
I7 Y7
I6 Y6
I5 Y Y5
I2 Y 4
I4 Y 2
I1 Y 3
I3 Y 1
0 I0 Y 2
I2
I1 Y1
I0 Y0

40
Real Stuff
★ MC54/74F148
★ 8-to-3 Line High Priority Encoder

41
Multiplexors
(Data Selectors)
Multiplexers
★ An m-to-1 multiplexer is a CLC that selects one of
the m inputs and pass it to its single output
★ The input is selected using n select lines such that
m ≤ 2n

I0 2-to-1 I0 2-to-1
MUX
Y Y = I0 MUX
Y Y = I1
I1 I1
S S

0 1
43
2-to-1 MUX

I1
I0 2-to-1 0 1 1 0
Y
I1 MUX S 0 0 1 1
S I0

Y(S, I1, I0) = S’ I0 + S I1

S I1 I0 Y
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
44
2-to-1 MUX
★ 2-to-1 MUX is
● a one 1-to-2 decoder
● two 2-input AND gates
● 2-input OR gate

★ Generally, we can build an m-to-1

MUX
● n-to-m decoder
● m 2-input AND gates (enabling circuit)
● m-input OR gate

45
4-to-1 Mux

I0
I1
MUX Y
I2
I3
S1 S0

46
Exercise
★ Draw the logic diagram of 8-to-1 MUX

47
Building Large Muxes
★ We can build large muxes from smaller ones
★ 4-to-1 Mux using 2-to-1 muxes

I0 I0 2-to-1
Y
S1 S0 Y I1 I1 MUX
S
0 0 I0
I0 2-to-1
0 1 I1 Y Y
I1 MUX
1 0 I2 S
I2 I0 2-to-1
1 1 I3 Y
I3 I1 MUX
S
S0
S1 48
Building Large Muxes
★ 8-to-1 mux using two 4-to-1 and 2-to-1 muxes

S2 S1 S0 Y I0
0 0 0 I0 I1
0 0 1 I1 I2
0 1 0 I2 I3
0 1 1 I3 MUX Y
I4
1 0 0 I4 I5
1 0 1 I5 I6
1 1 0 I6 I7
1 1 1 I7 S2 S1 S0

49
Building Large Muxes
★ 8-to-1 MUX using two 4-to-1 MUX

I0 I0
I1 I1
MUX Y
I2 I2
I3 I3
S1 S0 I0
MUX Y Y
I1
I0 S
I4
I5 I1
MUX Y
I6 I2
I7 I3
S1 S0

S2 S1 S0 50
Exercise
★ Build 8-to-1 MUX using 2-to-1 MUXes only

S2 S1 S0 Y
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7

51
Exercise
★ Build 8-to-1 MUX using 4-to-1 MUXes only

S2 S1 S0 Y
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7

52
Building Larger Muxes
★ A m-to-1 multiplexor is a n-to-m line decoder with m
enabling circuits (AND gates) and m-input OR gate.
★ Is it possible to realize the mux using different type of
enabling circuit and eliminating the need of the OR gate?
★ Tri-State Buffers!

2-to-1 Mux! 53
Implementing Functions Using Multiplexers
★ Muxes can be thought of Switching OR gate that is
controlled by the selection lines
★ Can be used to implement logic functions
● Select the value of the function based on the input value

★ Method I: To implement a function of n variables

● 2n-to-1 multiplexor
● Connect the n input variables to the n selection lines
● Value-fix the mux inputs based on the truth table

54
Example 11
★ F(x, y) = ∑(0, 1, 3)

x y F I0
1
0 0 1 1 I1
MUX Y F
0 1 1 0 I2
1 0 0 1 I3
S1 S0
1 1 1
x y

55
 Example 12
★ F(x, y, z) = ∑(1, 2, 6, 7)

0 I0
x y z F 1 I1
0 0 0 0 1 I2
0 0 1 1 0 I3
Y F
0 1 0 1 0 I4 MUX
0 1 1 0 0 I5
1 I6
1 0 0 0
1 I7
1 0 1 0 S2 S1 S0
1 1 0 1
1 1 1 1 x y z
56
Example 13
★ F(x, y, z) = ∏ (3, 4, 6)

I0
I1
I2
I3
Y F
I4 MUX
I5
I6
I7
S2 S1 S0

57
Implementing Functions Using Multiplexers
★ Method II: To implement a function of n variables
● 2n-1-to-1 multiplexor
● Connect the most significant n-1 input variables to the
n-1 selection lines of th multiplexor
● Pair the rows in the truth table and express each pair in
terms of the least significant variable in the function
● Specify the mux inputs based on the expression obtained
for each pair
● An inverter might be needed

58
 Example 14
★ F(x, y, z) = ∑(1, 2, 6, 7)

x y z F
0 0 0 0 z I0
F=z z I1
0 0 1 1 F
MUX Y
0 1 0 1 0 I2
F=z 1 I3
0 1 1 0 S1 S0
1 0 0 0
F=0 x
1 0 1 0
y
1 1 0 1
F=1
1 1 1 1
59
Example 15
★ F(A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15)

A B C D F
0 0 0 0 0
F=D
D I0
0 0 0 1 1
0 0 1 0 0
D I1
F=D
0 0 1 1 1 D I2
0 1 0 0 1
0 1 0 1 0
F=D 0 I3
0 MUX Y F
0 1 1 0 0
F=0 I4
0 1 1 1 0 D
1 0 0 0 0
I5
1 0 0 1 0 F=0 1 I6
1 0 1 0 0
1 0 1 1 1
F=D 1 I7
1 1 0 0 1 S2 S1 S0
F=1
1 1 0 1 1
1 1 1 0 1
F=1 A B C
1 1 1 1 1
60
Implementing Functions Using Multiplexers
★ Can we use 2-to-1 mux to implement the function
in example 14?
x y z F
0 0 0 0
0 0 1 1
0 1 0 1 I0 2-to-1
Y
0 1 1 0 I1 MUX
S
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
61
Example 16
★ Determine the logic function implemented in the
following circuit
A B C F
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

62
Multiplexers Width Expansion
★ Quad 2-to-1 MUX
A3 I0
B3 MUX Y
I1
S
A3
A2 I0 A2
B2 MUX Y A1
I1 Y3
S A0
Y
MUX 2
Y1
B3
I0 Y0
MUX Y B2
A1 I1 B1
S
B1 B0
S E
I0
MUX Y
I1
S
A0 Only one decoder is
B0 S needed!
63
Real Stuff
★ 74LS153
★ DUAL 4-to-1 DATA SELECTOR/MULTIPLEXER

64
Demultiplexors
Demultiplexers
★ An 1-to-m demultiplexer is a CLC that performs
the inverse operation of multiplexors
★ It passes the single input to one of its m outputs
★ The input is selected using n select lines such that
m ≤ 2n

Y0 = D Y0 = 0
1-to-2 Y0 1-to-2 Y0
D DEMUX D DEMUX
Y1 Y1 = 0 Y1 Y1 = D
S S

0 1 66
1-to-2 Demux

1-to-2 Y0 Y0(S, I) = S’ D
D DEMUX Y1
S Y1(S, I) = SD

S D Y1 Y0
0 0 0 0
0 1 0 1
1 0 0 0
1 1 1 0

67
1-to-2 Demux
★ 1-to-2 Demux is a one
1-to-2 decoder with output
enable
★ Generally, a 1-to-m Demux
is a n-to-m decoder with
output enable such that
● Input D of demux is
connected to the Enable
Y1

Decoder
input of decoder S A D1

1-to-2
● Selection lines of demux are D0 Y0
D E
connected to the address
lines of the decoder
68
DeMultiplexers / Decoders

Y3 Y3

Decoder
A1

Binary
Y2 Y2
D DeMUX Y A0 Y1
1 E Y0
S S Y0
1 0

E A1 A0 Y3 Y2 Y1 Y0
S1 S0 Y3 Y2 Y1 Y0 0 x x 0 0 0 0
0 0 0 0 0 D 1 0 0 0 0 0 1
0 1 0 0 D 0 1 0 1 0 0 1 0
1 0 0 D 0 0 1 1 0 0 1 0 0
1 1 D 0 0 0 1 1 1 1 0 0 0

69
Multiplexer / DeMultiplexer Pairs
MUX DeMUX

I7 Y7
I6 Y6
I5 Y5
I4 Y4
Y D Y3
I3
I2 Y2
I1 Y1
I0 Y0

S2 S1 S0 S2 S1 S0

Synchronize
x2 x1 x0 y2 y1 y0
70
Exercises
Suggested Problems (5th Edition)
★ 5-16

★ 5-17

★ 5-18

★ 5-19

★ 5-22

★ 5-23

72
Exercises
* A combinational circuit is defined by the following three
Boolean functions. Design the circuit with a decoder and
external gates.
F1 = x’ y’ z’ + x z
F2 = x y’ z’ + x’ y
F3 = x’ y’ z + x y

73
Exercises
* Construct a 16 × 1 multiplexer with two 8 × 1 and one
2 × 1 multiplexers. Use block diagrams.

74
Exercises
* Implement the following Boolean function with a
multiplexer:
F(A, B, C, D) = ∑(0, 1, 3, 4, 8, 9, 15)

75