Assignment-14

Computer Architecture (CS F342)

Semester-I, 2024-25
Department of Computer Science and Information Systems (CSIS)
BITS-Pilani, K K Birla Goa Campus, Goa, India.

Due date: Nov 26, 2024: 10:00 AM Marks: 20

Prepare the traces using PIN tool for matrix_multi.cpp and quicksort.cpp by following the instructions from
the guide in the google classroom (Do not edit the source files). Move the traces to the /champsim/traces/
directory inside the container. (Marks 2)

Build Champsim and run the simulation on each of the traces you prepared previously. These will be
the baseline results. Simulation results appear on the terminal. Redirect the output to txt files.

Make sure to store them separately in a directory named as baseline/, as they will be required later on.
The following are the configurations for building and running the simulations

For building,
Use the default champsim_config.json.

For running,
Parameter Value

# of warm-up instructions 2000000

# of simulation instructions 5000000

IMPORTANT: Before attempting the following questions, note down the default values of whatever
you’ll change later on in the champsim_config.json file.

Direct-Mapped Cache at all levels (Marks 2)

Change all the caches to Direct-mapped caches; however, the cache sizes remain constant. Compile the
Champsim again to get the modified caches and run it using the traces, similar to the previous section.

Report your observations after comparing with the results obtained from the baseline configuration (of the
appropriate trace). Did the IPC improve? What about the average miss latency? Why do you think it
happened?

Store the results separately in a separate directory named as direct-mapped/

1
Fully-Associative Cache at all levels (Marks 2)

Reset the changed parameters to their original values. Next, change all the caches to Fully-mapped caches;
however, the cache sizes remain constant. Compile the Champsim again to get the modified caches and run
it using the traces, similar to the previous section.

Report your observations after comparing with the results obtained from the baseline configuration (of the
appropriate trace). Did the IPC improve? What about the average miss latency? Why do you think it
happened?

Store the results separately in a separate directory named as fully-associative/

Halving the size of the caches at all levels (Marks 2)

Reset the changed parameters to their original values. Next, decrease the number of sets in all the caches
by half. Make sure to change the latency in cycles appropriately and mention the values in the report.
Compile the Champsim again to get the modified caches and run it using the traces, similar to the previous
section.

Report your observations after comparing with the results obtained from the baseline configuration (of the
appropriate trace). Did the IPC improve? What about the average miss latency? Why do you think it
happened?

Store the results separately in a separate directory named as reduced-size/

Doubling the size of the caches at all levels (Marks 2)

Reset the changed parameters to their original values. Next, double the number of sets in all the caches.
Make sure to change the latency in cycles appropriately and mention the values in the report. Compile the
Champsim again to get the modified caches and run it using the traces, similar to the previous section.

Report your observations after comparing with the results obtained from the baseline configuration (of the
appropriate trace). Did the IPC improve? What about the average miss latency? Why do you think it
happened?

Store the results separately in a separate directory named as doubled-size/

Halving the number of Miss Status Handling Registers (MSHRs) at all levels (Marks 2)

Reset the changed parameters to their original values. Next, decrease the number of MSHRs in all the
caches by half. Compile the Champsim again to get the modified caches and run it using the traces, similar
to the previous section.

Report your observations after comparing with the results obtained from the baseline configuration (of the
appropriate trace). Did the IPC improve? What about the average miss latency? Why do you think it
happened?

Store the results separately in a separate directory named as reduced-mshr/

Doubling the number of Miss Status Handling Registers (MSHRs) at all levels (Marks 2)

Reset the changed parameters to their original values. Next, double the number of MSHR in all the caches.
Compile the Champsim again to get the modified caches and run it using the traces, similar to the previous
section.
2
Report your observations after comparing with the results obtained from the baseline configuration (of the
appropriate trace). Did the IPC improve? What about the average miss latency? Why do you think it
happened?

Store the results separately in a separate directory named as doubled-mshr/

<your_roll_number_CA_Lab10>/
|-- report.pdf
|-- baseline/ # .txt files of results
|-- direct-mapped/ # .txt files of results
|-- fully-associative/ # .txt files of results
|-- reduced-size/ # .txt files of results

|-- doubled-size/ # .txt files of results

|-- reduced-mshr/ # .txt files of results

|-- doubled-mshr/ # .txt files of results

(Directory structure of your submission)

Find the cache misses for the code matrix.cpp using the tool perf and note it as screenshot and put it in the
report.pdf. Modify the code in matrix.cpp such that cache misses get reduced. Include the modified part
and improved cache misses in the report.pdf. (Marks 6)

Create a zip file <CampusID>_ CA_Lab-14.zip which contains all the files mentioned above, and
submit it in Quanta. Do not create archives in other formats (rar, tar.gz etc). Once uploaded on Quanta,
remember to submit for grading. Please do not leave it as a draft.
No need to define other variables and to modify the other module except the below in the program.

/*###################################################################################
Note: Please don’t upload the assignments, template file/solution and lab. manual on GitHub or
others public repository.
Kindly remove them, if you have uploaded the previous assignments.
It violates the BITS’s Intellectual Property Rights (IPR).
************************************************************************************/