IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO.

11, NOVEMBER 2004 1809

A 1-V 140-W 88-dB Audio Sigma-Delta Modulator

in 90-nm CMOS
Libin Yao, Student Member, IEEE, Michiel S. J. Steyaert, Fellow, IEEE, and Willy Sansen, Fellow, IEEE

Abstract—A single-loop third-order switched-capacitor - 61 accuracy, providing an effective way to implement high-reso-
modulator in 90-nm standard digital CMOS technology is pre- lution ADCs without stringent matching requirements or cali-
sented. The design is intended to minimize the power consumption bration in low-voltage environment. By means of oversampling
in a low-voltage environment. A load-compensated OTA with
rail-to-rail output swing and gain enhancement is chosen in this and noise shaping, the - ADC transfers most of the signal
design, which provides higher power efficiency than the two-stage processing tasks to the digital domain where the power con-
OTA. To lower the power consumption further, class-AB oper- sumption can be drastically reduced by the technology scaling
ation is also adapted in the OTA design. Due to the relatively down and supply voltage decreasing. Meanwhile, the use of
low threshold voltage of the advanced technology, no clock boot- an intrinsically linear single-bit quantizer exempts the stringent
strapping circuits are needed to drive the switches and the power
consumption of the digital circuits is reduced. All the capacitors matching requirement, which is power-hungry. For high-reso-
are implemented using multilayer metal-wall structure, which can lution ADCs, the - ADC is more power-effective and robust
provide high-density capacitance. The modulator achieves 88-dB compared to other architectures.
dynamic range in 20-kHz signal bandwidth with an oversampling While moving into ultra-deep-submicron CMOS technolo-
ratio of 100. The power consumption is 140 W under 1-V supply gies, for low-voltage low-power designs, certain advantages
voltage and the chip core size is 0.18 mm2 .
can be gained. On the other hand, some disadvantages are also
Index Terms—Analog–digital conversion, Sigma-Delta modula- foreseen. Limited by the transistor breakdown voltage, the
tion, switched-capacitor circuits, low voltage, low power, opera- rated supply voltage is low in ultra-deep-submicron CMOS
tional amplifiers.
technologies. As a result, the threshold voltage of the transistor
is also low, which is advantageous to implement low-voltage
I. INTRODUCTION applications. No specially designed low-voltage circuits are
needed, which simplifies the circuits and lowers the power con-
I N RECENT years, portable electronics, such as personal
wireless communication devices, digital cameras, personal
audio devices, etc., find booming markets. Powered by bat-
sumption. Many low-power low-voltage - ADCs reported
to date are implemented in submicron CMOS technologies [2],
teries, their supply voltage is often limited, and the battery [3]. The common point of these works is that they work on a
lifetime is of great importance for these devices. All these reduced supply voltage that is lower than their rated supply
factors address the requirements of low-voltage low-power voltage. To sufficiently drive the switches, clock bootstrapped
system building blocks. At the same time, mainly driven by driving circuits are employed. In this case, some internal node
digital circuits, the feature size of transistors is continuously voltages might be higher than the supply voltage. Damaging
being scaled down. The working voltage is decreased as a the transistor or having a reliability problem are potential risks.
consequence of the size shrinking to avoid transistors breaking Low- technologies can also be used. However, this needs
down, forcing the design to work at lower supply voltage. extra processing steps and is expensive. Some works [4] were
These factors make low-voltage low-power circuits a hot topic implemented with the switched-opamp technique [5], which
recently. However, the decreased supply voltage restricts the solves the driving problem of the sampling switches in the
signal swing in circuits and brings some difficulties for analog succeeding stage, but the first sampling switch still cannot be
designs [1]. In low-voltage environments, the transistor char- driven sufficiently. With ultra-deep-submicron technologies, the
acteristics degrade and some circuit techniques can no longer threshold voltage is reduced as the supply voltage is decreased.
be used, rendering the low-voltage design different from the This makes the driving of the switches possible without boot-
traditional circuit design technique. strapping circuits. Hence, ultra-deep-submicron technologies
As an important building block, analog-to-digital converters help to reduce the power consumption further in a low-voltage
(ADCs) are widely used in various systems. The movement of environment. For the digital part of the converter, the shorter
digital circuits into ultra-deep-submicron technology presents the transistor length, the less power that is consumed. That is
strong demands to low-voltage low-power ADCs. Among dif- the driving force of the technology scaling down. Generally
ferent ADC topologies, - ADCs efficiently trade speed for speaking, in terms of low-power low-voltage, it is advantageous
indeed to move into ultra-deep-submicron technologies.
It is meaningful to explore the possibilities of implementing
Manuscript received March 10, 2004; revised June 16, 2004. high-performance - modulators in a standard digital process
The authors are with the Katholieke Universiteit Leuven, Department of in ultra-deep-submicron technologies. Presented in this paper
Elektrotechniek, ESAT-MICAS, B-3001 Leuven-Heverlee, Belgium (e-mail:
[email protected]). is a single-loop third-order switched-capacitor (SC) -
Digital Object Identifier 10.1109/JSSC.2004.835825 modulator implemented in a standard digital 90-nm CMOS
0018-9200/04$20.00 © 2004 IEEE
1810 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 11, NOVEMBER 2004

Fig. 1. Single-loop third-order topology.

Fig. 3. Normalized output of each integrators of the proposed topology.

Fig. 2. Output spectrum of the proposed topology with a 20-kHz input signal.

technology. The modulator achieves 88-dB dynamic range in

20-kHz signal bandwidth, while consuming 140 W under 1-V
supply voltage.

II. LOW-VOLTAGE LOW-POWER DESIGN CONSIDERATIONS

A. Modulator Topology Selection
Single-loop topology is preferable for low-voltage low-power
designs since it is less sensitive to circuit nonidealities, e.g.,
OTA dc gain and switch on-resistance. The - ADC is known Fig. 4. 6 1 modulator.
SNR versus OTA dc gain of the third-order single-loop -
for its high tolerance for circuit nonidealities compared to other
ADC architectures. However, in a low-voltage environment
topology. The minimum gain requirement for OTAs is 30 dB
and ultra-deep-submicron technologies, circuit nonidealities
to ensure 85-dB SNR of the modulator. This gain requirement
become more severe and their impact on the ADC performance
is drawn only from the noise shaping consideration. However,
should be reconsidered. A third-order single-loop topology was
taking the distortion into consideration, the higher the OTA gain,
chosen in this design, shown in Fig. 1. The loop coefficients
the better the distortion performance that can be achieved.
are set to [0.2 0.3 0.4]. Fig. 2 shows a behavioral simulation
result of the modulator. The behavioral simulation was done by
B. OTA Topology Selection
setting all of the OTA gains to 40 dB and the oversampling ratio
to 100. Compared to loop coefficients in [6], the modulator The OTA composes the main building block of the - mod-
with these coefficients has the same noise-shaping ability but ulator. It determines the main power consumption of the modu-
higher overload level, which is good for expanding the dynamic lator. The requirements for the OTA are mainly output swing, dc
range in low-voltage environments. More importantly, this gain, and gain bandwidth (GBW). The output swing is of great
topology is quite tolerant to the inaccurate coefficients caused importance in low-voltage designs, as mentioned before. It de-
by capacitance mismatches. Fig. 3 shows the output swing of termines the reference voltage, hence the sampling capacitance
each integrator of the modulator normalized to the reference and finally the power consumption. For a noise-dom-
voltage while feeding a 3-dB input signal. The output swings inated modulator, the dynamic range can be written as
reach 80% of the reference voltage, which means the reference
voltage should be almost the same as the output swing of the (1)
integrator. If distortion performance is taken into considera-
tion, then the reference voltage should be even smaller. Fig. 4 where is the maximum input amplitude of the modulator
shows the obtained SNR versus the OTA gains in the proposed and is the sampling capacitance of the first integrator. The
YAO et al.: A 1-V 140- W 88-dB AUDIO SIGMA-DELTA MODULATOR IN 90-nm CMOS 1811

Fig. 5. Miller compensated two-stage OTA. Fig. 6. Current mirror OTA.

maximum input amplitude of the modulator is defined by the Similarly, for the same GBW and load capacitance , the cur-
output swing of the OTA, as can be seen in Fig. 3. For certain dy- rent drawn by fully differential class-A single-stage OTAs is cal-
namic range, an increase in the output swing can result in a large culated as follows. The current drawn by the the single-stage
reduction of sampling capacitance and hence power consump- telescopic cascode OTA is
tion. The importance of the output swing can be clearly seen (8)
here in (1). An OTA topology that can provide the rail-to-rail
output swing is absolutely required in low-voltage low-power For the folded cascode OTA, there are two current branches and
designs. normally the current of both current branches are the same. The
In ultra-deep-submicron technology, the intrinsic voltage current drawn by the single-stage folded cascode OTA is
gain of the transistor is low due to the lower output impedance.
The low-voltage environment and output swing constraint (9)
prohibit the usage of the cascoding transistors to increase the
voltage gain. The natural solution is two-stage or multistage The current drawn by a current mirror OTA with a current ratio
topologies. However, the two-stage OTA is not load compen- of , shown in Fig. 6, can be calculated as follows. For the
sated. Extra compensation capacitance is needed to ensure the given GBW and , we have
closed-loop stability. For a given GBW and load capacitance
, the current drawn by a fully differential class-A Miller (10)
OTA, shown in Fig. 5, can be calculated.
then
(2)
(11)
where is the Miller compensation capacitance. Combining
And for the current mirror OTA, we have
this with the MOSFET equation
(12)
(3)
Then the total current of the current mirror OTA is
gives
(13)
(4)
It is clearly seen that for the same condition, the single-stage
The nondominant pole, which is created by the load capacitance, OTA is more power efficient than the two-stage OTA, since no
should be placed beyond the three times of the GBW. This cri- power is wasted in driving the compensation capacitance in the
teria single-stage OTA.
According to the above discussion, the single-stage OTA
(5) is preferred in terms of power-efficiency. In the low-voltage
environment, the rail-to-rail output swing for the OTA is
gives highly preferred. The only single-stage topology that can
provide rail-to-rail output swing is the current mirror OTA.
(6) However, the voltage gain of the current mirror OTA is only
in the order of , which is normally around 20–40 dB in
Assuming all transistors have the same overdrive voltage, the ultra-deep-submicron technologies. According to behavioral
total current of the Miller OTA is then simulations, the requirement of the OTA dc gain is above 40
dB. To ensure enough gain, a gain enhancement technique is
(7) used, which can enhance the gain for 10–20 dB without extra
1812 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 11, NOVEMBER 2004

Fig. 7. Current mirror OTA with gain enhancement.

Fig. 8. Class-AB operation of the output stage. (a) Class-AB biasing of the
output PMOS transistor. (b) Implementation of the class-AB biasing.
power consumption [7], shown in Fig. 7. The gain of the current
mirror OTA can be expressed as
To maintain a reasonably safe phase margin, the nondominant
(14) pole has to be placed more than three times of the GBW [8]:

where is the channel length modulation coefficient and is (21)

the current ratio of the current mirror.
Suppose the overdrive voltages of the transistors are the same,
(15) and then the following criteria can be obtained:

Then the gain of the current mirror OTA can be written as (22)

(16) Equation (22) shows the maximum gain enhancement that can
be achieved. The smaller the ratio, the more gain en-
When we shunt a portion of currents from the current mirror, hancement can be achieved. If the OTA drives a large capaci-
for example, , shown in Fig. 7, the current mirrored to tran- tance load, then higher gain can be reached.
sistor M3 is reduced to The class-AB output stage is considered to be more power
efficient than the class-A output stage in SC circuits [9]. Higher
(17)
slew rate can be obtained from the class-AB output stage with
Note that the factor is between 0 and 1. Then, finally, the gain less power consumption. To save power, a class-AB output
of the OTA is given by stage should be adopted in this low-voltage low-power design.
Shown in Fig. 8(a), the class-AB operation is made by driving
the PMOS transistor M4 by a floating voltage source .
(18)
This is a very crude class-AB output scheme. The class-AB
characteristics are not so good. But here in SC circuits, high
Equation (18) clearly shows the gain enhancement. It is seen slew rate is more important than good class-AB output char-
that the gain has been boosted times. If the factor acteristics. As long as the output settles to the required final
is set to near one, then the gain can be enhanced largely. value, the settling procedure is not important. This class-AB
This technique actually increases the impedance of the in- stage increases the current sourcing ability of the output stage.
ternal node C. As a result, the nondominant pole frequency, As a result, the slew rate of the OTA is increased. The floating
which is created in this node, is decreased. Doing this may cause voltage source is implemented by a level-shifter, shown
degradation of the phase margin of the OTA and cause a stability in Fig. 8(b). The transistors M5 and M6 are identical and have
problem. A closer look reveals relations between the factor the same drain current. As a result, their gate-source voltages
and related parameters. are also identical. By properly biasing M5, a certain can
Suppose the parasitic capacitance of node C is , which is be obtained.
mainly composed of and , the gate-source capaci- Common-mode feedback is essential to fully differential cir-
tance of transistor M2 and M3. The nondominant pole in node cuits. A switched-capacitor common-mode feedback (CMFB)
C can be given by is the best solution in terms of power consumption.

(19) C. Transistor Biasing

The biasing of a transistor determines the most important
while the GBW of the OTA can be written as specifications of the transistor. Generally speaking, the tran-
sistor reaches the maximum ratio and low saturation
(20)
voltage when it operates in the weak inversion region, hence
YAO et al.: A 1-V 140- W 88-dB AUDIO SIGMA-DELTA MODULATOR IN 90-nm CMOS 1813

the maximum power efficiency is achieved. However, the fre-

quency response is degraded and the silicon area occupied is
larger when in the weak inversion region. A compromise is
made here between speed and power consumption. The spec-
ifications of the whole modulator should be taken into consid-
eration in making tradeoffs among speed, power, and area. In
this design, the main transistors in the OTAs are biased in the
moderate inversion region, e.g., V.

D. Scaling of Integrators
One of the most interesting property of - modulators is
the noise suppression inside the loop. Utilizing this feature can Fig. 9. Schematic of the gain enhanced current mirror OTA.
result in a large amount of power saving. For a single-loop -
modulator, the noise suppression in node can be calculated by
[10]

(23)

where is the noise suppression factor, is the oversam-

pling ratio, and denotes the loop coefficient of the th stage.
For the proposed topology, the noise suppression of the first,
second, and third stage is 41, 63, and 86 dB, respectively. This
allows the sampling capacitances of these stages to be scaled Fig. 10. Schematic of the switched-capacitor CMFB circuit.
down proportionally to corresponding ratios. The only restric-
tion is from the matching requirements. Reducing the sampling
capacitance results in a reduction of the load capacitance of the
OTA and hence reduces the power consumption.

III. BUILDING BLOCK CIRCUITS

A. Low-Voltage Low-Power OTAS
Depicted in Fig. 9, the OTA used in this design is the cur-
rent mirror OTA with gain enhancement. This OTA features
rail-to-rail output swing and class-AB operation. And most im-
portantly, it is a single-stage structure, which reduces the power
consumption effectively.
As mentioned in Section II-B, the factor determines the gain
reached and the phase margin. In this design, the factor was
set to 0.8 and the current mirror ratio was 10. These ratios can
be realized by sizing the relevant transistors. Matching issues
Fig. 11. Simulated OTA frequency response.
should be taken into consideration here. Two identical transis-
tors, M5 and M6, function as a voltage level-shifter. The shifted
signal drives transistor M4, providing extra current to the load GBW is 57 MHz while the phase margin is kept at 57 degrees,
when large signal presents. The biasing voltage defines the with a power consumption of only 80 W.
class-AB operating point of the output stage. The switched-ca-
pacitor CMFB circuit is presented in Fig. 10. The precharged B. One-Bit Quantizer Circuits
capacitor senses the output common-mode voltage and shift The one-bit quantizer is realized with a dynamic comparator
the voltage to proper level in node CMFB. Capacitor pe- and an SR latch, shown in Fig. 12 [11]. While clock C1 is low,
riodically recharges the sensing capacitor to provide a constant nodes P and Q are precharged to . While clock C1 goes
voltage in the sensing capacitor. The main feature of this CMFB high, the precharged parasitic capacitances of nodes P and Q are
circuit is that it is very power efficient. To ensure that the speed discharged by transistors M1a and M1b, respectively. The dis-
of the common-mode loop is faster than the differential loop charge rate of each branch depends on the input voltage. When
in the OTA, the transconductance of transistor M4c should be the voltage of node P or Q drops to the threshold voltage of the
higher than that of transistor M1 in Fig. 9. latch formed by two cross-coupled inverters, the regeneration
The simulated frequency response of the proposed OTA with process starts. Finally, the voltage of nodes P and Q reaches
a 6-pF load is depicted in Fig. 11. The gain reaches 50 dB and the the rail voltage according to the decision made. The result is
1814 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 11, NOVEMBER 2004

Fig. 12. Schematic of the comparator and latch.

Fig. 14. Schematic of the clock generator.

Fig. 13. Switch implementation and the local driver.

then latched by the SR latch following. The whole comparator

is a pure dynamic circuit, which is very power efficient. For a Fig. 15. Different feedback configurations.
single-bit - modulator, the requirement for the quantizer is
quite relaxed as nonidealities in this stage can be largely sup-
pressed (see Section II-D). The offset voltage is mainly defined second and third integrators can be scaled down to reduce the
by matching of the input transistors. power consumption. The thermal noise level of the modulator
determines the value of the first sampling capacitor, hence the
C. Switch Driving Circuits power consumption of the first integrator. The value of the first
sampling capacitor is 6 pF, which is sufficient to provide 95-dB
All switches are implemented with transmission gates. As the
peak SNR with 0.6-V reference level. Considering the matching
circuit is working on its rated supply voltage, there is no need to
property of the capacitors, both the second and third sampling
use any clock bootstrapping circuit to boost the driving voltage.
capacitors are set to 0.4 pF.
Simple inverters are employed to drive switching transistors,
Another practical low-power consideration is the feedback
shown in Fig. 13. The maximum driving voltage is the supply
scheme of the integrator. Fig. 15 shows two different feedback
voltage. So no node inside the whole circuits is exposed to a
schemes. The left one directly connects the feedback signal to
voltage higher than or lower than , which is essential
one terminal of the sampling capacitor during clock period C2,
for high-reliability operation of the circuit.
i.e., the integration phase of the integrator. The right one uses
D. Other Circuits two sampling capacitors to sample the input signal and feedback
signal, respectively, and then sums these two signals during the
The on-chip clock generator is shown in Fig. 14 [6]. The ex-
integration phase of the integrator. Both of these two schemes
ternal clock input signal is buffered and then two nonoverlap-
have the same function, while the right scheme uses more ca-
ping clock signals are generated. To avoid the signal dependent
pacitors and switches. On the left circuit, the sampling capac-
charge injection, two delayed clocks, i.e., C1d and C2d, are also
itor is discharged to either Vrefp or Vrefn during the integration
generated [12].
phase, and during the sampling phase the sampling capacitor is
charged to the input voltage. During the charge and discharge
IV. IMPLEMENTATION
cycle, the voltage change on the sampling capacitor is from ei-
The ultimate goal of this design is to reduce the power con- ther Vrefp or Vrefn to Vin, which is quite large. Most impor-
sumption as much as possible. To lower the power consumption, tantly, the charge current is provided by the preceding OTA.
the main consideration is to lower the power consumption in This large signal charge requires a high slew rate of the OTA and
the first integrator. Since in - modulators, the first integrator consumes power. On the right circuit, the large charge current
dominates the overall performance of the modulator and most of is provided by the reference voltage. The OTA only charges the
the power is consumed here. As mentioned in Section II-D, the sampling capacitor from 0 to the input voltage, which is smaller.
YAO et al.: A 1-V 140- W 88-dB AUDIO SIGMA-DELTA MODULATOR IN 90-nm CMOS 1815

Fig. 16. Schematic of the proposed third-order 6-1 modulator.

Fig. 17. Proposed metal-wall capacitor structure.

Fig. 18. Chip micrograph.

So the right circuit relaxes the requirement for the preceding

the unit capacitance can be large. Calculation shows the unit ca-
OTA and consumes less power.
pacitance is around fF m in the technology used, which
The common-mode input and output voltages are chosen
is higher than that of normal MIM capacitors. However, the
differently in a low-voltage environment. For signal swing
matching property is worse than that of MIM capacitor. As the
consideration, the output common-mode voltage is set to the
loop coefficients are defined by the capacitance ratios, robust
middle of the supply voltage, i.e., 0.5 V. However, if the input
loop coefficients are chosen to be more tolerant to the mis-
common-mode voltage is set to the middle of the supply
matched capacitance. This kind of capacitance is widely used
voltage, rail-to-rail input capability is required for the OTA,
in this design as decoupling capacitors around the chip.
which cannot be offered by the normal differential input stage.
The chip was fabricated in a standard digital 90-nm CMOS
If the input common-mode voltage is set near the supply rail,
technology. The power supply voltage was 1 V and the reference
the normal OTA can be used without the rail-to-rail input
voltage was 0.6 V. The chip core size was 0.42 mm 0.42 mm,
requirement. In this design, the common-mode input voltage is
as illustrated in Fig. 18. The analog part is separated from the
set to be 0.2 V. The whole circuit is shown in Fig. 16.
digital part by guard rings. To reach the maximum common-
As the process technology used is a standard digital tech-
mode rejection ratio, all the analog parts are laid out symmetri-
nology, no standard metal–insulator–metal (MIM) capacitor is
cally. The surroundings of the unit capacitances are identical to
available. All capacitances are implemented by metal wall struc-
ensure good matching.
ture, shown in Fig. 17 [13]. This structure uses the lateral ca-
pacitance instead of the vertical capacitance normally used. In
V. MEASUREMENT RESULTS
ultra-deep-submicron technologies, the lateral spaces between
metal lines in the same layer are smaller than the vertical spaces To shield the chip from the external interferences, the chip
between metal layers, and the lateral spaces are well controlled. is mounted on a thick-film ceramic substrate and then encap-
Only one metal layer is occupied for connecting, and the re- sulated in a copper–beryllium box. Separate power supplies for
maining layers can be used to build the capacitor, which means analog and digital parts and the output buffer are used in the
1816 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 11, NOVEMBER 2004

Fig. 19. Measured output spectrum of an 11-kHz sinusoidal input. Fig. 21. Measured SNR and SNDR versus input amplitude.

TABLE I
MEASURED PERFORMANCE SUMMARY

voltage is less than 1.5 V. The figure-of-merit (FOM) is defined

as [2]

Fig. 20. Measured noise floor of the modulator with inputs short-circuited. (24)

where is Boltzmann’s constant; is the absolute tempera-

measurement. Local decoupling capacitors are used in power ture; and are the signal bandwidth and power consump-
supplies and biasing sources. tion of the - ADC, respectively. The FOM is a measure of the
Clocked at 4 MHz, the output data of the modulator is power efficiencies of - ADCs, taking signal bandwidth and
captured by a logic analyzer and processed by software. Fig. 19 dynamic range into consideration. However, the supply voltage
shows the measured output spectrum of an 11-kHz sinusoid is not taken into consideration here. To make a fair comparison,
signal. Fig. 20 shows the output spectrum with the inputs all converters should be operating at the same supply voltage.
short-circuited to ground. Fig. 21 shows the measured SNR and This work achieves the highest FOM among these - ADCs.
SNDR versus the input signal amplitudes normalized by refer- There are two reasons for the high power efficiency of this
ence voltage. The peak SNR reaches 85 dB while peak SNDR work. One is the specially designed building blocks, especially
reaches 81 dB. The dynamic range is 88 dB in a 20-kHz signal the OTAs, and the other is the use of the advanced 90-nm
bandwidth. The analog core power consumption is 130 W. technology. Following the low-voltage and low-power design
The digital power consumption is 10 W, excluding the power strategies described in Section III, the power consumption of
consumption of the output buffer. Table I gives the summary of the whole converter has been effectively decreased. For digital
the performance. parts, the smaller transistor feature size helps to decrease the
Table II shows the performance comparison of recently pub- power consumption. Clocked at 4 MHz, the total digital part of
lished low-voltage low-power - modulators whose supply this modulator consumes only 10 W.
YAO et al.: A 1-V 140- W 88-dB AUDIO SIGMA-DELTA MODULATOR IN 90-nm CMOS 1817

TABLE II
PERFORMANCE COMPARISON

VI. CONCLUSION [11] T. B. Cho and P. R. Gray, “A 10 b, 20 Msample/s, 35 mW pipeline

A/D converter,” IEEE J. Solid-State Circuits, vol. 30, pp. 166–172, Mar.
A low-voltage low-power switched-capacitor - modulator 1995.
[12] D. Haigh and B. Singh, “A switching scheme for switched capacitor
has been presented. By proper topology selection, the modulator filters which reduces the effects of parasitic capacitances associated with
enables the usage of single-stage OTAs with rail-to-rail output switch control terminals,” in Proc. IEEE Int. Symp. Circuits and Systems,
swing in ultra-deep-submicron CMOS technology. A gain en- May 1983, pp. 586–589.
[13] R. Aparicio and A. Hajimiri, “Capacity limits and matching proper-
hancement technique has been adopted in the OTA to satisfy the ties of integrated capacitors,” IEEE J. Solid-State Circuits, vol. 37, pp.
distortion requirements of the modulator. A metal-wall structure 384–393, Mar. 2002.
has been employed to implement the capacitance in this stan- [14] M. Keskin, U. Moon, and G. C. Temes, “A 1-V 10-MHz clock-rate 13-bit
dard digital technology. This capacitance has good matching
CMOS 16 modulator using unity-gain-reset opamps,” IEEE J. Solid-
State Circuits, vol. 38, pp. 817–824, July 2002.
properties and higher unity capacitance, which helps to reduce [15] J. Sauerbrey, T. Tille, D. Schmitt-Landsiedel, and R. Thewes, “A
chip area. Special measures were taken in the circuit design to 0.7-V MOSFET-only switched-opamp 16 modulator in standard
digital CMOS technology,” IEEE J. Solid-State Circuits, vol. 37, pp.
reduce power consumption. The design has been verified by 1662–1669, Dec. 2002.
measurements. The results have proven the possibility of imple-
menting high-performance - ADCs in ultra-deep-submicron
standard digital CMOS technologies. Compared to other CMOS
technologies, ultra-deep-submicron CMOS technologies (e.g.,
Libin Yao (S’01) received the B.Sc. degree from the
90-nm technology) have advantages in the implementation of University of Electronic Science and Technology of
low-power low-voltage - modulators. China in 1989 and the M.Eng. degree from the Nan-
jing University of Science and Technology in 2000.
He is currently working toward the Ph.D. degree at
the Katholieke Universiteit Leuven, Belgium.
ACKNOWLEDGMENT From 1989 to 2000, he was a Researcher with the
Kunming Institute of Physics, China. Since 2000, he
The authors would like to thank D. Draxelmayr and Infineon has been a Research Assistant in the ESAT-MICAS
Technologies for technical support and processing of the circuit. Laboratory, Katholieke Universiteit Leuven. His re-
search interest is mainly in the area of high-perfor-
mance analog-to-digital converters in deep-submicron CMOS technologies.
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[2] S. Rabii and B. A. Wooley, “A 1.8-V digital-audio Sigma-Delta was born in Aalst, Belgium, in 1959. He received
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[3] M. Dessouky and A. Kaiser, “Very low-voltage digital-audio 16 modu- the Katholieke Universiteit Leuven (K.U.Leuven),
lator with 88-dB dynamic range using local switch-bootstrapping,” IEEE Heverlee, Belgium, in 1983 and 1987, respectively.
J. Solid-State Circuits, vol. 36, pp. 349–355, Mar. 2001. From 1983 to 1986, he obtained an IWNOL fel-
[4] V. Peluso, P. Vancorenland, A. M. Marques, M. S. J. Steyaert, and W. lowship (Belgian National Fundation for Industrial
Sansen, “A 900-mV low-power A/D converter with 77-dB dynamic Research) which allowed him to work as a Research
range,” IEEE J. Solid-State Circuits, vol. 33, pp. 1887–1897, Dec. 1998. Assistant at the Laboratory ESAT at K.U. Leuven.
[5] M. Steyaert and J. Crols, “Switched-opamp: An approach to realize full In 1987, he was responsible for several industrial
CMOS switched-capacitor circuits at very low power supply voltages,” projects in the field of analog micropower circuits at the Laboratory ESAT as
IEEE J. Solid-State Circuits, vol. 29, pp. 936–942, Aug. 1994. an IWONL Project Researcher. In 1988, he was a Visiting Assistant Professor
[6] A. Marques, V. Peluso, M. Steyaert, and W. Sansen, “Optimal parame- at the University of California at Los Angeles. In 1989, he was appointed by
ters for Delta-Sigma modulator topologies,” IEEE Trans. Circuits Syst., the National Fund of Scientific Research (Belgium) as Research Associate,
vol. 45, pp. 1232–1241, Sept. 1998. in 1992 as a Senior Research Associate and in 1996 as a Research Director
[7] L. Yao, M. Steyaert, and W. Sansen, “A 0.8-V, 8-W CMOS OTA with at the Laboratory ESAT, K.U.Leuven. Between 1989 and 1996, he was also a
50-dB gain and 1.2-MHz GBW in 18-pF load,” in Proc. Eur. Solid-State part-time Associate Professor. He is now a Full Professor at the K.U.Leuven.
Circuits Conf., Sept. 2003, pp. 297–300. His current research interests are in high-performance and high-frequency
[8] K. R. Laker and W. M. Sansen, Design of Analog Integrated Circuits analog integrated circuits for telecommunication systems and analog signal
and Systems. New York: McGraw-Hill, 1994. processing.
[9] F. Wang and R. Harjani, “Power analysis and optimal design of opamps Prof. Steyaert received the 1990 and 2001 European Solid-State Circuits Con-
for oversampled converters,” IEEE Trans. Circuits Syst. II, vol. 46, pp. ference Best Paper Award. He received the 1991 and the 2000 NFWO Alcatel-
359–369, Apr. 1999. Bell-Telephone award for innovative work in integrated circuits for telecom-
[10] S. Norsworthy, R. Schreier, and G. Temes, Delta-Sigma Data Con- munications. Prof.Steyaert received the 1995 and 1997 IEEE-ISSCC Evening
verters: Theory, Design, and Simulation. New York: IEEE Press, Session Award, the 1999 IEEE Circuit and Systems Society Guillemin-Cauer
1996. Award and is currently an IEEE-Fellow.
1818 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 11, NOVEMBER 2004

Willy Sansen (S’66–M’72–SM’86–F’95) has re-

ceived the M.Sc. degree in electrical engineering
from the Katholieke Universiteit Leuven in 1967 and
the Ph.D. degree in electronics from the University
of California at Berkeley in 1972.
In 1972, he was appointed by the National Fund
of Scientific Research (Belgium) at the ESAT Labo-
ratory of the K.U.Leuven, where he has been a Full
Professor since 1980. During 1984–1990, he was the
head of the Electrical Engineering Department. Since
1984, he has headed the ESAT-MICAS Laboratory
on analog design, which counts about 60 members and which is mainly active
in research projects with industry. He is a member of several boards of directors.
In 1978, he was a Visiting Professor at Stanford University, in 1981 at the EPFL
Lausanne, in 1985 at the University of Pennsylvania, Philadelphia, in 1994 at
the T.H. Ulm, and in 2004 at Infineon, Villach. He has been involved in design
automation and in numerous analog integrated circuit designs for telecommu-
nications, consumer electronics, medical applications and sensors. He has been
supervisor of over 50 Ph.D. theses in these fields. He has authored and coau-
thored 12 books and more than 550 papers in international journals and confer-
ence proceedings.
Prof. Sansen is a member of several editorial and program committees of
journals and conferences. He is cofounder and organizer of the workshops on
Advances in Analog Circuit Design in Europe. He is a member of the executive
and program committees of the IEEE ISSCC conference, and was program chair
of the ISSCC 2002 conference.