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L10 Verilog - Expressing Sequential-Cct

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7 views16 pages

L10 Verilog - Expressing Sequential-Cct

Uploaded by

Moazzam Nafees
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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EE-421: Digital Systems Design

Expressing Sequential Circuits

Instructor: Dr. Rehan Ahmed [[email protected]]


Quick Review: Sequential Circuits

2
Combinational + Memory = Sequential

Sequential Circuit

outputs
inputs

Combinational
Circuit

Storage
Element

3
Review: Sequential Logic
• In a combinational circuit, the values of the outputs
are determined solely by the present values of its
inputs.

• A sequential circuit has states, which in conjunction


with the present values of inputs determine its
behavior:
– Such circuits include storage elements that store the
values of logic signals
– The contents of the storage elements are said to
represent the state of the circuit

4
Review: Gated D Latch

5
Review: Master Slave D-flip flop

6
Level-Sensitive vs Edge-Triggered
Storage Elements

A flip-flop is a storage element that can have its output state changed
only on the edge of the controlling clock signal

7
Discussion: Level-Sensitive vs Edge-Triggered
Storage Elements
• Ref to fig in the previous slide:

• The D input changes its values more than once during


each half of the clock cycle.

• Observe that:
– the gated D latch follows the D input as long as the clock is
high.
– The positive-edge-triggered flip-flop responds only to the
value of D when the clock changes from 0 to 1
– The negative-edge-triggered flip-flop responds only to the
value of D when the clock changes from 1 to 0.

8
Expressing Sequential Circuits in
Verilog-HDL

9
Sequential Logic in Verilog
• Define blocks that have memory:
– Flip-Flops, Latches, Finite State Machines

• Sequential Logic state transition is triggered by a


“CLOCK” signal:
– Latches are sensitive to level of the signal
– Flip-flops are sensitive to the transitioning of signal

• Combinational constructs are not sufficient:


– We need new constructs:
▪ always_ff
▪ posedge/negedge

10
Recall: The “always” Block

always @ (sensitivity list)


statement;

Whenever the event in the sensitivity list occurs,


the statement is executed

12
Describing a Positive-Edge D-Flip Flop

module flop(input clk,


input [3:0] d,
output [3:0] q);

always_ff @ (posedge clk)


q <= d; // pronounced “q gets d”

endmodule

◼ posedge defines a rising edge (transition from 0 to 1).

◼ Statement executed when the clk signal rises (posedge of clk)

◼ Once the clk signal rises: the value of d is copied to q

13
Describing a Positive-Edge D-Flip Flop
module flop(input logic clk,
input logic d,
output logic q);

always_ff @ (posedge clk)


q <= d; // pronounced “q gets d”

endmodule

• Also note:
◼ assign statement is not used within an always block
◼ <= describes a non-blocking assignment

◼ clk is the only input that can cause an event on the output
◼ Therefore clk is the only signal in the sensitivity list

◼ Special sensitivity list @(posedge Clock):


◼ This event expression tells the Verilog compiler that any reg variable assigned a
value in the always construct is the output of a D flip-flop
14
Describing a Positive-Edge D-Flip Flop
module flop(input logic clk,
input logic d,
output logic q);

always_ff @ (posedge clk)


q <= d; // pronounced “q gets d”

endmodule

◼ Assigned variables need to be declared as reg


◼ The name reg does not necessarily mean that the value is a
register (It could be, but it does not have to be)
◼ We have seen examples before while doing combinational
ccts!!!
15
Recommended Reading
• Digital System Design with Verilog HDL, 3/e, b Stephen
Brown and Zvonko Vranesic. [S&Z]
– S&Z,
▪ Chapter-5

16
THANK YOU

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