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L06 - Verilog - Combinational-Cct Building Blocks - Adder

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13 views17 pages

L06 - Verilog - Combinational-Cct Building Blocks - Adder

Uploaded by

Moazzam Nafees
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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EE-421: Digital System Design

Combinational Circuit Building Blocks


Using CAD Tools - Adder

Instructor: Dr. Rehan Ahmed [[email protected]]


Recap: What have we seen so far . . .
Verilog

Structural Behavioral
Modeling Modeling ❑ Using Expressions

❑ Concurrent Statements
❑ assign net_assignment • Using Behavioral constructs (if-else etc)
aka Procedural Statements
• Required to be enclosed inside an
always block

always @(sensitivity_list)
[begin]
[procedural assignment statements]
[if-else statements]
[case statements]
[while, repeat, and for loops]
[task and function calls]
[end]

2
Design of Arithmetic Circuits –
Full Adder

3
Review: Half-Adder

4
Review: Full-Adder

5
Review: Full-Adder using Half-Adders

ci s si
s HA c
xi
HA c ci + 1
yi

(a) Block diagram

ci
si
xi
yi

ci + 1

(b) Detailed diagram

6
Full-Adder using Gate-Level Primitives

module fulladd (Cin, x, y, s, Cout);


input Cin, x, y;
output s, Cout;

xor (s, x, y, Cin);


and (z1, x, y);
and (z2, x, Cin);
and (z3, y, Cin);
or (Cout, z1, z2, z3);

endmodule

7
Full-Adder using Continuous Assignment

module fulladd (Cin, x, y, s, Cout);


input Cin, x, y;
output s, Cout;

assign s = x ^ y ^ Cin;
assign Cout = (x & y) | (x & Cin) | (y & Cin);

endmodule

8
Full-Adder at Behavioral

module fulladd (Cin, x, y, s, Cout);


input Cin, x, y;
output reg s, Cout;

always @(x, y, Cin)


{Cout, s} = x + y + Cin;

endmodule

9
Design of Arithmetic Circuits –
Multi-bit Adder

10
Four-bit Adder –
Using Hierarchical Design Approach
module adder4 (carryin, x3, x2, x1, x0, y3, y2, y1, y0, s3, s2, s1, s0, carryout);
input carryin, x3, x2, x1, x0, y3, y2, y1, y0;
output s3, s2, s1, s0, carryout;

fulladd stage0 (carryin, x0, y0, s0, c1);


fulladd stage1 (c1, x1, y1, s1, c2);
fulladd stage2 (c2, x2, y2, s2, c3);
fulladd stage3 (c3, x3, y3, s3, carryout);

endmodule

module fulladd (Cin, x, y, s, Cout);


input Cin, x, y;
output s, Cout;

assign s = x ^ y ^ Cin,
assign Cout = (x & y) | (x & Cin) | (y & Cin);

endmodule

11
Code Improvement using Vectors

module adder4 (carryin, X, Y, S, carryout);


input carryin;
input [3:0] X, Y;
output [3:0] S;
output carryout;
wire [3:1] C;

fulladd stage0 (carryin, X[0], Y[0], S[0], C[1]);


fulladd stage1 (C[1], X[1], Y[1], S[1], C[2]);
fulladd stage2 (C[2], X[2], Y[2], S[2], C[3]);
fulladd stage3 (C[3], X[3], Y[3], S[3], carryout);

endmodule

12
Code Improvement using Parametrization

module addern (carryin, X, Y, S, carryout);


parameter n=32;
input carryin;
input [n-1:0] X, Y;
output reg [n-1:0] S;
output reg carryout;
reg [n:0] C;
integer k;

always @(X, Y, carryin)


begin
C[0] = carryin;
for (k = 0; k < n; k = k+1)
begin
S[k] = X[k] ^ Y[k] ^ C[k];
C[k+1] = (X[k] & Y[k]) | (X[k] & C[k]) | (Y[k] & C[k]);
end
carryout = C[n];
end

endmodule

13
Alternate Style using CASE
module fulladd (Cin, x, p_state, s, Cout);
input Cin, x, p_state;
output reg s, Cout;

always @(Cin, x, p_state)


begin
case ( {Cin, x, p_state} )
3'b000: {Cout, s} = 'b00;
3'b001: {Cout, s} = 'b01;
3'b010: {Cout, s} = 'b01;
3'b011: {Cout, s} = 'b10;
3'b100: {Cout, s} = 'b01;
3'b101: {Cout, s} = 'b10;
3'b110: {Cout, s} = 'b10;
3'b111: {Cout, s} = 'b11;
endcase
end

endmodule

14
Code Improvement using Generate

module addern (carryin, X, Y, S, carryout);


parameter n = 32;
input carryin;
input [n-1:0] X, Y; module fulladd (Cin, x, y, s, Cout);
output [n-1:0] S;
output carryout; input Cin, x, y;
wire [n:0] C; output s, Cout;
assign s = x ^ y ^ Cin,
genvar i;
assign C[0] = carryin; Cout = (x & y) | (x & Cin) | (y & Cin);
assign carryout = C[n]; endmodule
generate
for (i = 0; i <= n-1; i = i+1)
begin:addbit
fulladd stage (C[i], X[i], Y[i], S[i], C[i+1]);
end
endgenerate
endmodule

15
Recommended Reading
• Digital System Design with Verilog HDL, 3/e, b Stephen
Brown and Zvonko Vranesic. [S&Z]
– S&Z,
▪ Chapter-3 for review
▪ 3.5 for Verilog

16
THANK YOU

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