Daffodil International University

Department of Electrical and Electronic Engineering

EEE-226/ 312 Digital Electronics Laboratory

SL No. Experiment Name

01 Familiarization with Digital Electronics Laboratory and Verification of the Basic
Logic Gates Characteristics
02 Experimental Study of De Morgan’s Laws using the Logic Gates.

03 Design and Implementation of AND-OR-INVERTER (A-O-I) Gate & OR-AND-

INVERTER (O-A-I) Gate Circuits
04 Design and Implementation of Half - Subtractor & Full - Subtractor Circuit
05 Design and Implementation of Half - Adder & Full - Adder Circuit
06 Design and Implementation of 2-bit Comparator

07 Design and Implementation of Encoder & Decoder Circuit

08 Design and Implementation of Multiplexer & De-multiplexer Circuit.

09 Design and Implementation of different Flip-flop using basic gates

10 Design and Implementation of 4-bit ripple counter and BCD counter using JK-
FFs
11 Construct a 4-bit register and shift register using DFFs

12 Open Ended Experiment

 Daffodil International University
Department of Electrical and Electronic Engineering
Course Title: EEE 226, Digital Electronics Lab

Experiment No: 01
Name of the Experiment: Familiarization with Digital Electronics Laboratory And
Verification of the Basic Logic Gates Characteristics

Objective:
1. Understanding the symbols and characteristics of various basic logic gates.

Theory:
1. AND Gate:
F= AB
Truth Table
State Input Output
A B
0 0 0 0
1 0 1 0
2 1 0 0
3 1 1 1

2. OR Gate:
F=A+B
Truth Table
State Input Output
A B
0 0 0 0
1 0 1 1
2 1 0 1
3 1 1 1

3. Not Gate:
F=A'
Truth Table
A F
0 1
1 0
Equipments Required:
1. Logic Trainer board
2. AND Gate (7408)
3. OR Gate (7432)
 4. NOT Gate Inverter (7404)
5. Connecting Wires (As required)

Circuit Diagram:

Fig 1-1

Fig 1-2

Working Procedures:
(a) AND Gate Characteristics Verification (IC 7408)
1. Connect 5 V to lead 14 & ground to lead 7.
2. Connect inputs A & B to lead 1 & 2 respectively & output F to lead 3.
3. Then verify the following truth table.

State Inputs Outputs

A B F

0 0 0 0
1 0 1 0
2 1 0 0
3 1 1 1

(b) OR Gate Characteristics Verification (IC 7432)

1. Connect 5 V to lead 14 & ground to lead 7.
2. Connect inputs A & B to lead 1 & 2 respectively & output F to lead 3.
3. Then verify the following truth table.
 State Inputs Outputs
A B F

0 0 0 0
1 0 1 1
2 1 0 1
3 1 1 1

(c) Not Gate Characteristics Verification (IC 7404)

1. Connect 5 V to lead 14 & ground to lead 7.
2. Connect inputs A to lead 1 & output F to lead 2.
3. Then verify the following truth table.

State Inputs Outputs

A F
0 0 1
1 1 0

Student Works:
1. Verify the Basic Gate Characteristics.
 Daffodil International University
Department of Electrical and Electronic Engineering
Course Title: EEE 226, Digital Electronics Lab

Experiment No: 02
Name of the Experiment: Experimental Study of De Morgan’s Laws using the Logic
Gates.

Objective:
1. Understanding the De Morgan’s laws using the logic gates.

Theory:
De Morgan’s theorem states, if in a logic function each +(OR) is replaced by a .(AND) and
each .(AND) is replaced by a +(OR) & each variable is replaced by it’s compliments, the
result is the compliment of the given function i.e.

a. A+B = A . B

b. A.B = A + B

Equipments Required:
1. Trainer Board
2. AND Gate (7408)
3. OR Gate (7432)
4. NAND Gate (7400)
5. NOR Gate (7402)
6. NOT Gate Inverter (7404)
7. Connecting Wires

Circuit Diagram:
Fig 3-1 (De Morgan’s 1st Theorem)
 Fig 3-2

Working Procedures:
1. Connect 5 V to lead 14 & ground to lead 7.
2. Construct the circuit according to the fig 3-1 & prove the De Morgan’s 1st theorem
using the following truth table.
a)

State Inputs Outputs

A B A! B! (A+B)! A! . B!
0 0 0 1 1 1 1
1 0 1 1 0 0 0
2 1 0 0 1 0 0
3 1 1 0 0 0 0

b)

State Inputs Outputs

A B A! B! (A.B)! A! + B!
 0 0 0 1 1 1 1
1 0 1 1 0 1 1
2 1 0 0 1 1 1
3 1 1 0 0 0 0

Student Works:
1. Prove the De-Morgan’s 2nd theorem with the help of NAND gate, OR gate & NOT
gate & verify their truth tables.

Questions:
1. What are the implications of De Morgan’s theorem?
2. Write down one logic expression using four variables & simplify the same with
the
help of de Morgan’s theorems & also draw the simplified logic diagram.
 Daffodil International University
Department of Electrical and Electronic Engineering
Course Title: EEE 226, Digital Electronics Lab

Experiment No: 03
Name of the Experiment: Design and Implementation of AND-OR-INVERTER (A-O-
I) Gate & OR-AND-INVERTER (O-A-I) Gate Circuits

Objective:
1. Understanding the basic principle of combined logic

Theory:
The Boolean expression for the output is
F= (AB+CD)'

Equipments Required:
1. Trainer Board
2. AND Gate (7408)
3. OR Gate (7432)
4. NOT Gate Inverter (7404)
5. Connecting Wires (As required)

Circuit Diagram:

Fig 3-1
 Fig 3-2

Working Procedures:
1. Connect 5 V to lead 14 & ground to lead 7. (All the ICs)
2. Connect the inputs according to the fig 3-1 to the leads of the ICs & verify the
following truth table.
State Inputs Outputs
A B C D F
0 0 0 0 0 1
1 0 0 0 1 1
2 0 0 1 0 1
3 0 0 1 1 0
4 0 1 0 0 1
5 0 1 0 1 1
6 0 1 1 0 1
7 0 1 1 1 0
8 1 0 0 0 1
9 1 0 0 1 1
10 1 0 1 0 1
11 1 0 1 1 0
12 1 1 0 0 0
13 1 1 0 1 0
14 1 1 1 0 0
15 1 1 1 1 0

Student Works:
1. A-O-I gate also be constructed using two AND gates and NOR gate.
2. Construct a “Product of Sum” circuit with F= (A'+B') × (C'+D') and “Sum of
Product” circuit with Y = A’BC+AB’C’+A’B’C’+AB’C+ABC.
3. The output of an A-O-I gate is A'B'+C'D', what is the output if C= A' and D=B'?
 Daffodil International University
Department of Electrical and Electronic Engineering
Course Title: EEE 226, Digital Electronics Lab

Experiment No: 04
Experiment Name: Design and Implementation of Half - Subtractor & Full - Subtractor
Circuit

Objectives:

To study Half - Subtractor & Full - Subtractor Circuit

Apparatus:

Trainer Board, 7486, 7432, 7408, 7404 and LEDs.

Theory:

Subtractor:

In electronics, a subtractor can be designed using the same approach as that of an adder.
The binary subtraction process is summarized below. As with an adder, in the general
case of calculations on multi-bit numbers, three bits are involved in performing the
subtraction for each bit of the difference: the minuend, subtrahend, and a borrow in from
the previous (less significant) bit order position. The outputs are the difference bit and
borrow bit. The subtractor is best understood by considering that the subtrahend and both
borrow bits have negative weights, Subtractors are usually implemented within a binary
adder for only a small cost when using the standard two's complement notation, by
providing an addition/subtraction selector to the carry-in and to invert the second
operand.

Half subtractor:

The half subtractor is a combinational circuit which is used to perform subtraction of two

bits. It has two inputs, the minuend X and subtrahend Y and two outputs the

difference D and borrow out Bout. The borrow out signal is set when the subtractor needs

to borrow from the next digit in a multi-digit subtraction.

Full subtractor:

The full subtractor is a combinational circuit which is used to perform subtraction of three

input bits: the minuend X, subtrahend Y, and borrow in Bin. The full subtractor generates

two output bits: the difference D and borrow out Bout. Bin is set when the previous digit

borrowed from X. Thus, Bin is also subtracted from X as well as the subtrahend Y. Or in

symbols: X-Y-Bin. Like the half subtractor, the full subtractor generates a borrow out

when it needs to borrow from the next digit. Since we are subtracting X by Y and Bin , a

borrow out needs to be generated when X<Y+Bin. When a borrow out is generated, 2 is

added in the current digit.

Circuit Diagram:
Procedure:

1. Give biasing to the ICs and design the half subtractor, and full subtractor using the EX-
OR, OR, NAND and NOT gates.

2. Provide various input combinations by using toggle switches and write down the outputs
with the help LEDs.

3. Finally fill up the truth table shown beside each logic diagram.

REPORT:

1. Show the results in tabular form.

2. Comment on the results obtained and discrepancies (if any).

CAUTIONS:

4. Take care of the reading of the apparatus.

5. Take care of any bare circuit element in energized condition.
 Daffodil International University
Department of Electrical and Electronic Engineering
Course Title: EEE 226, Digital Electronics Lab

Experiment No: 05
Name of the Experiment: Design and Implementation of Half - Adder & Full –
Adder Circuit

Objective:
1. Understanding the characteristics of half - adder & full - adder in the arithmetic unit.

Theory:
Adders are important not only in computers but also in many types of digital systems in
which numerical data are processed. The half adder accepts two binary digits on it's inputs
(A, B) and produces two binary digits on it's output a sum bit and a carry bit (S,Co). The
full adder accepts more than two binary digits as input (Cin, A, B) and generates two binary
digits on its output a sum and a carry (S, Co).

Half – adder Sum: S=AB=AB+AB

And Carry: Co=AB

Truth Table (Half-Adder):

Input Sum Carry

A B S Co
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Equipments Required:
1. Logic Trainer Board
2. AND Gate (7408)
3. XOR Gate (7486)
4. Connecting Wires (As required)

Circuit Diagram:
 Fig 5-1
Truth Table (Full –Adder)

Input Output
A B Ci Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Circuit Diagram:

Figure: Full-Adder Logic Diagram

 Fig 5-2

Working Procedures:
1. Connect 5 V to lead 14 & ground to lead 7.
2. Construct the circuit according to the fig 5-1.
3. Verify the truth table of the Half Adder circuit.

Student Works:
1. Construct truth table for full - adder circuit.
2. Design the full-adder circuit.

Questions:
1. What is parallel adder? How can you add two binary numbers where, A2A1 = 10 &
B2B1= 11. Draw the circuit diagram for the operation.
2. Write down the SOP expression of full adder from the truth table. Minimize the
expression using Karnaugh map. Draw the minimized logic diagram.
 Daffodil International University
Department of Electrical and Electronic Engineering
Course Title: EEE 226, Digital Electronics Lab

Experiment No. : 06
Name of the Experiment: Design and Implementation of 2-bit Comparator

Objective:
1. Understanding the operating principles and construction of comparator.

Theory:
The comparison of two numbers is an operation that determines whether one number is
greater than, less than, or equal to the other number. A comparator is a combinational circuit
that compares two numbers A and B and determines their relative magnitudes. The outcome
of the comparison is specified by three binary variables that indicate where A>B, A=B, and
A<B.
Equipments Required:
1. Logic Trainer Board
2. 2-input AND Gate (7408)
3. NOT Gate Inverter (7404)
4. 2-input XOR Gate (7486)
5. Connecting Wires(As required)

Circuit Diagram:

Figure 6-1: One-bit comparator

 Figure 6-2: Pin diagram of different ICs

Working Procedures:
(a) Constructing a 1-bit comparator with basic logic gates
1. Connect 5 V to lead 14 & ground to lead 7.
2. Construct the circuit according to the fig-1.
3. Compare the results with the following true table.

Student Works:
1. Design & implement a 2-bit comparator.
 Daffodil International University
Department of Electrical and Electronic Engineering
Course Title: EEE 226, Digital Electronics Lab

Experiment No: 07
Name of the Experiment: Design and Implementation of Encoder & Decoder Circuit

Objective:
1. Understanding the operating principles of decoder circuits.
2. Understanding the operating principles of encoder circuits.

Theory:
A decoder is a logic circuit that will detect the presence of a specific binary number or
word. The input to the decoder is a parallel binary number and the output is a parallel binary
number and the output is a binary signal that indicates the presence or absence of that specific
number.

An encoder is a combinational logic gate that accepts one or multiple inputs and
generates a specific output code. Only one input is triggered at a time.

Equipments Required:
4. Logic Trainer Board
5. 3-input AND Gate (7411)
6. NOT Gate Inverter (7404)
7. OR Gate (7432)
8. Connecting Wires

Circuit Diagram:
Decoder: +5V

C B A 0 1 2 3 4 5 6 7
 Fig 4-1

Fig 4-2

Encoder:

D0 D1 D2 D3 D44D5 D6 D7

A = D4 + D5 + D6+ D7

B = D2 + D3 + D6+ D7

C = D1 + D3 + D5+ D7

Fig 4.4

Fig 4-4
Working Procedures:
(a) Constructing a 3-to-8 Decoder with Basic Gates
1. Connect 5 V to lead 14 & ground to lead 7.
2. Construct the circuit according to the fig 7-1.
3. Find the output of the following table.

Inputs Outputs

A B C D7 D6 D5 D4 D3 D2 D1 D0

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1
(b) Constructing a 8-to-3 encoder with basic gates
1. Connect 5 V to lead 14 & ground to lead 7.
2. Construct the circuit according to the fig 6-1.
3. Find the output of the following table.

Inputs Outputs

D7 D6 D5 D4 D3 D2 D1 D0 A B C

0 0 0 0 0 0 0 1

0 0 0 0 0 0 1 0

0 0 0 0 0 1 0 0

0 0 0 0 1 0 0 0

0 0 0 1 0 0 0 0

0 0 1 0 0 0 0 0

0 1 0 0 0 0 0 0

1 0 0 0 0 0 0 0

Questions:
1. What is the purpose of decoder? Draw the logic diagram of 2-to-4 decoder.
2. How many numbers of outputs if the input number is 5 of a decoder?
3. What is the purpose of encoder? Draw the logic diagram of 4-to-2 priority
encoder.
4. How many numbers of outputs if the input number is 12 of an encoder?
 Daffodil International University
Department of Electrical and Electronic Engineering
Course Title: EEE 226, Digital Electronics Lab

Experiment No: 08
Name of the Experiment: Design and Implementation of Multiplexer &
De-multiplexer Circuit.

Objective:
1. Understanding the operating principles and construction of multiplexers.
2. Understanding the operating principles and construction of de-multiplexer circuits

Theory:
Multiplexer, or MUX, is a logic circuit that select and route any number of inputs to a
single output. One of the multiple inputs are selected by the selector gate and routed to the
single output. The number of selector determines the capacity of a multiplexer. For example,
if a certain MUX has only one selector gate, it is referred to as a “2-to-1 MUX" because one
selector can only select from two inputs. A MUX with 3 selector gates is called "8-to-1
MUX", since 3 selectors are capable of selecting an output from 8 inputs (23=8). MUX is also
referred to as "Data Selector" because it selects one output from among many inputs.

A de-multiplexer, or DMUX, is basically a logic circuit that is exact opposite of a

multiplexer. DMUX has a single input and multiple outputs. The input can be connected to
any one of the many outputs through the selector terminal.

Equipments Required:
1. Logic Trainer Board
2. 3-input AND Gate (7411)
3. NOT Gate Inverter (7404)
4. OR Gate (7432)
5. Connecting Wires (As required)

Circuit Diagram:
Data selector
Multiplexer
S1 S0

I0

I1
Data input Data output
I2
I3

Fig: 5-1
 Fig 5-2

De-multiplexer

S1 S0

D0

Data input I D1

D2

D3

Fig 5-3

Fig 5-4
Working Procedures:
a) Constructing a 4-to-1 Multiplexer
1. Connect 5 V to lead 14 & ground to lead 7.
2. Construct the circuit according to the fig 8-2.
3. Find the output of the following table.
 Data Selector Data Output

S1 S0 Y

0 0

0 1

1 0

1 1

(b) Constructing a 1-to-4 line de-multiplexer with basic logic gates

1. Connect 5 V to lead 14 & ground to lead 7.
2. Construct the circuit according to the fig 9-1.
3. Find the output of the following table.

S1 S0 Output

0 0

0 1

1 0

1 1

Student Works:
1. Design & implement a 8-to-1 Multiplexer.

Questions:
1. How many selection lines are required to design a 16-to-1 MUX?
2. Design & implement a 1-to-8 line de-multiplexer.
 Daffodil International University
Department of Electrical and Electronic Engineering
Course Title: EEE 226, Digital Electronics Lab

Experiment No: 09
Experiment Name: Design and Implementation of different Flip-flop using basic gates
Objectives:

To study R-S, J-K, D and T flip-flops.

Introduction:

These circuits do not have memory cells and their output depends only upon the current value
of the input. Memory cells are very important in digital systems. Their usage in digital
circuits provides temporary storage of the outputs produced by a combinational logic
circuit for use at a later time in the operation of a digital system.
Logic circuits that incorporate memory cells are called sequential logic circuits; their output
depends not only upon the present value of the input but also upon the previous values.
Sequential logic circuits often require a timing generator (a clock) for their operation.
The latch (flip-flop) is a basic bi-stable memory element widely used in sequential logic
circuits. Usually there are two outputs, Q and its complementary value. They are called
state variables. State variables which change only between logic 1 and logic 0 are called
binary state variables. There are various types of latches. Some of the most widely used
latches are listed below.
There are mainly four types of flip flops that are used in electronic circuits. They are
1. SR flip flop
2. D flip flop
3. JK flip flop
4. T flip flop

S-R Flip Flop:

The SET-RESET flip flop is designed with the help of two NOR gates and also two NAND
gates. These flip flops are also called S-R Latch. The circuit diagram and truth-table of a
S-R flip flop is shown below.
 (a) Logic Diagram (b) Truth Table

D Flip Flop:
D flip flop is actually a slight modification of the above explained clocked SR flip-flop. From
the figure you can see that the D input is connected to the S input and the complement of
the D input is connected to the R input. The D input is passed on to the flip flop when the
value of CP is ‘1’. When CP is HIGH, the flip flop moves to the SET state. If it is ‘0’, the
flip flop switches to the CLEAR state. The circuit diagram and truth-table of a D flip flop
is shown below.

JK Flip Flop:
A J-K flip flop can also be defined as a modification of the S-R flip flop. The only difference
is that the intermediate state is more refined and precise than that of a S-R flip flop.

The behavior of inputs J and K is same as the S and R inputs of the S-R flip flop. The letter J
stands for SET and the letter K stands for CLEAR.

When both the inputs J and K have a HIGH state, the flip-flop switch to the complement
state. So, for a value of Q = 1, it switches to Q=0 and for a value of Q = 0, it switches to
Q=1. The circuit diagram and truth-table of a J-K flip flop is shown below.
 (a) Logic Diagram (b) Truth Table

T Flip Flop:
This is a much simpler version of the J-K flip flop. Both the J and K inputs are connected
together and thus are also called a single input J-K flip flop. When clock pulse is given to
the flip flop, the output begins to toggle. Here also the restriction on the pulse width can
be eliminated with a master-slave or edge-triggered construction. Take a look at the
circuit and truth table below.

Logic Diagram:
Option 1:
This is a much simpler version of the J-K flip flop. Both the J and K inputs are connected
together and thus are also called a single input J-K flip flop.
 SR flip flop using NAND IC 7476 (JK flip flop)

T flip flop using IC 7476 D flip flop using IC 7476

Option 2:

SR Latch JK Flip Flop using SR latch and master-slave topology

Digital trainer kit and 4 JK flip-flop each IC 7476 (i.e. dual JK flip-flop) and two AND gates
IC 7408.

Procedure:
 1. Give biasing to the ICs and design the converter as per the circuit diagram.
2. Apply the appropriate input combinations and verify the output to form a truth table.

Observation Table:

Precautions:
1. Take care of the reading of the apparatus.
2. Take care of any bare circuit element in energized condition.
 Daffodil International University (DIU)
Dept. of Electrical and Electronic Engineering (EEE)
Course Code: EEE 226
Title: Digital Electronics Laboratory

Experiment No: 10
Experiment Name: Design and Implementation of 4-bit ripple counter and BCD counter
using JK-FFs
Objectives:

To design 4-bit ripple counter and BCD counter using JK-FFs.

Introduction:
Binary Ripple Counter:

A binary ripple counter consists of a series connection of complementing FFs, with the
output of each FF connected to the C input of the next higher order FF. The FF holding the
least significant bit receives the incoming count pulses. Complementing FF: (1) JK FF with
the J and K inputs tied together, (2) T FF, (3) D FF with the complement output.
Example: 4-bit binary ripple counter: Binary count sequence: 4-bit Starts with binary 0 and
increments by 1 with each count pulse input. After the count of 15, the counter goes back to 0
to repeat the count.

BCD counter:

A binary coded decimal (BCD) is a serial digital counter that counts ten digits. And it resets for every
new clock input. As it can go through 10 unique combinations of output, it is also called as “Decade
counter”. A BCD counter can count 0000, 0001, 0010, 1000, 1001, 1010, 1011, 1110, 1111, 0000, and
0001 and so on.

Apparatus:

Trainer Board, IC – 7476, 555-timer and LEDs.

Circuit Diagram:
Construct a 4-bit ripple counter and a BCD counter as show in Figure 1.

Figure 1: Circuit diagram of 4-bit ripple counter and BCD counter

Procedure:

3. Make the connections as per the logic diagram.

4. Provide clock pulse to the clock pin shown in figure 1.
5. Check the output whether it is correct or not.

Observation:
4-bit ripple counter 4-bit BCD counter
Precautions:

3. Take care of the reading of the apparatus.

4. Take care of any bare circuit element in energized condition.
 Daffodil International University (DIU)
Dept. of Electrical and Electronic Engineering (EEE)
Course Code: EEE 226
Title: Digital Electronics Laboratory

Experiment No: 11
Experiment Name: Construct a 4-bit register and shift register using DFFs

Objectives:

To construct a 4-bit register and shift register using DFFs.

Introduction:

Registers:
A register is a group of FFs, each FF shares a common clock and is capable of storing one bit
of information. An n bit register consists of a group of n FFs capable of storing n bits of
binary information. A register may have combinational gates that perform certain data -
processing tasks. The simplest register is containing only FFs.
Example: four DFFs form a 4bit data storage register. The clock positive edge triggers all
FFs, and the binary data at the four inputs are transferred into the register. (I3, I2, I1, I0)
determines (A3, A2, A1, A0) at the clock edge, and the four outputs can be sampled at any
time. Clear is active low to reset FFs asynchronously. The R inputs must be maintained at
logic 1 (i.e., de-asserted) during normal clocked operation.

Shift Registers:

Shift register is a cascaded chain of FFs with the output of each FF connected to the
input of the next FF. It is capable of shifting the binary information held in each FF to its neighboring
FF, in a selected direction. All FFs receive common clock to activate the shift of data. The simplest
possible shift register uses only FFs, as shown below. This shift register is unidirectional (left to right).
The serial input determines what goes into the leftmost FF during the shift. The serial output is taken
from the output of the rightmost FF.
Apparatus:

Trainer Board, IC – 7474 and LEDs.

Circuit Diagram:

Construct a 4-bit register and 4-bit shift resister using D FFs. A 4-bits resister with parallel

load and a 4-bit serial register are show in Figure: 8.1.

Figure 1: Circuit diagram of 4-bit register

Procedure:

6. Make the connections as per the logic diagram.

7. Provide clock pulse to the clock pin shown in figure 1.
8. Check the output whether it is correct or not.
Observation:

Clock Pulse
A0 A1 A2 A3
No.

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

5 0 0 0 0

Data

Input
Clk

A0

A1

A2

A3

Figure 2

Precautions:

5. Take care of the reading of the apparatus.

6. Take care of any bare circuit element in energized condition.