INDEX

Exp. Page
Date Name of the Experiment Marks Signature
No. No.

1 STUDY OF LOGIC GATES

DESIGN OF ADDER AND

2
SUBTRACTOR

DESIGN OF 4-BIT ADDER AND

3
SUBTRACTOR

4 DESIGN AND IMPLEMENTATION OF

CODE CONVERTOR

DESIGN AND IMPLEMENTATION OF

5
MULTIPLEXER AND
DEMULTIPLEXER
DESIGN OF ENCODERS AND
6 DECODERS

7 DESIGN AND IMPLEMENTATION OF

MAGNITUDE COMPARATOR

DESIGN AND IMPLEMENTATION OF 4

8
BIT RIPPLE COUNTER AND MOD10
RIPPLE COUNTER

9 DESIGN AND IMPLEMENTATION OF

SHIFT REGISTER
 STUDY OF LOGIC GATES

EXPT. NO. : 1
DATE :

AIM:
To study about logic gates and verify their truth tables.

APPARATUS REQUIRED:

S. No. COMPONENT SPECIFICATION QTY

1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. NAND GATE 2 I/P IC 7400 1
5. NOR GATE IC 7402 1
6. X-OR GATE IC 7486 1
7. NAND GATE 3 I/P IC 7410 1
8. IC TRAINER KIT - 1
9. PATCH CORD - 14

THEORY:
Circuit that takes the logical decision and the process are called logic gates. Each gate
has one or more input and only one output.
OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as universal gates.
Basic gates can be built from these gates.
AND GATE:
The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs
is low.
OR GATE:
The OR gate performs a logical addition commonly known as OR function. The output is high
when any one of the inputs is high. The output is low level when both the inputs are low.
NOT GATE:

1
The NOT gate is called an inverter. The output is high when the input is low. The output is low
when the input is high.
NAND GATE:
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.
NOR GATE:
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.
X-OR GATE:
The output is high when any one of the inputs is high. The output is low when both the inputs
are low and both the inputs are high.

PROCEDURE:
I. Connections are given as per circuit diagram.
II. Logical inputs are given as per circuit diagram.
III. Observe the output and verify the truth table.

AND GATE:
SYMBOL: PIN DIAGRAM

2
OR GATE:

NOT GATE:
SYMBOL PIN DIAGRAM

3
X-OR GATE:
SYMBOL PIN DIAGRAM

2-INPUT NAND GATE:

SYMBOL PIN DIAGRAM:

4
3-INPUT NAND GATE

NOR GATE:

5
OBSERVATION :

RESULT:

Preparation 5
Conduction &
5
Observation Result Execution

Viva-Voce &
5
Inference
Record 5
Total 20

6
 DESIGN OF ADDER AND SUBTRACTOR

EXPT. NO. : 2
DATE :

AIM:
To design and construct half adder, full adder, half subtractor and full subtractor circuits and
verify the truth table using logic gates.
APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. AND GATE IC 7408 1
2. X-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
4. OR GATE IC 7432 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 23

THEORY:
HALF ADDER:
A half adder has two inputs for the two bits to be added and two outputs one from the sum ‘ S’
and other from the carry ‘ c’ into the higher adder position. Above circuit is called as a carry
signal from the addition of the less significant bits sum from the X-OR Gate the carry out from
the AND gate.
FULL ADDER:
A full adder is a combinational circuit that forms the arithmetic sum of input; it consists of
three inputs and two outputs. A full adder is useful to add three bits at a time but a half adder
cannot do so. In full adder sum output will be taken from X-OR Gate, carry output will be taken
from OR Gate.
HALF SUBTRACTOR:
The half subtractor is constructed using X-OR and AND Gate. The half subtractor has two
input and two outputs. The outputs are difference and borrow. The difference can be applied
using X-OR Gate, borrow output can be implemented using an AND Gate and an inverter.
FULL SUBTRACTOR:

7
The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full subtractor the
logic circuit should have three inputs and two outputs. The two half subtractor put together
gives a full subtractor .The first half subtractor will be C and A B. The output will be difference
output of full subtractor. The expression AB assembles the borrow output of the half subtractor
and the second term is the inverted difference output of first X-OR.

HALF ADDER:
TRUTH TABLE:

A B CARRY SUM
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

K-Map for SUM: K-Map for CARRY:

SUM = A’B + AB’ CARRY = AB

LOGIC DIAGRAM:

8
FULL ADDER USING TWO HALF ADDER
TRUTH TABLE:
A B C CARRY SUM
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

K-Map for SUM:

SUM = A’B’C + A’BC’ + ABC’ + ABC

K-Map for CARRY:

CARRY = AB + BC + AC

9
LOGIC DIAGRAM:

HALF SUBTRACTOR:
TRUTH TABLE:
A B BORROW DIFFERENCE
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

K-Map for DIFFERENCE: K-Map for BORROW:

DIFFERENCE = A’B + AB’ BORROW = A’B

10
LOGIC DIAGRAM:

FULL SUBTRACTOR
TRUTH TABLE:
A B C BORROW DIFFERENCE
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

K-Map for Difference:

Difference = A’B’C + A’BC’ + AB’C’ + ABC

K-Map for Borrow:

11
 Borrow = A’B + BC + A’C

LOGIC DIAGRAM:

FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:

PROCEDURE:
I. Connections are given as per circuit diagram.
II. Logical inputs are given as per circuit diagram.
III. Observe the output and verify the truth table.

OBSERVATION :

RESULT:

Preparation 5
Conduction &
5
Observation Result Execution

Viva-Voce &
5
Inference
Record 5
Total 20

12
 DESIGN OF 4-BIT ADDER AND SUBTRACTOR

EXPT. NO. :3
DATE :

AIM:
To design and implement 4-bit adder and subtractor using IC 7483.

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. IC IC 7483 1
2. EX-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 40

THEORY:
4 BIT BINARY ADDER:
A binary adder is a digital circuit that produces the arithmetic sum of two binary
numbers. It can be constructed with full adders connected in cascade, with the output carry
from each full adder connected to the input carry of next full adder in chain. The augends bits
of ‘A’ and the addend bits of ‘B’ are designated by subscript numbers from right to left, with
subscript 0 denoting the least significant bits. The carries are connected in chain through the
full adder. The input carry to the adder is C0 and it ripples through the full adder to the output
carry C4.
4 BIT BINARY SUBTRACTOR:
The circuit for subtracting A-B consists of an adder with inverters, placed between each
data input ‘B’ and the corresponding input of full adder. The input carry C0 must be equal to 1
when performing subtraction.
4 BIT BINARY ADDER/SUBTRACTOR:
The addition and subtraction operation can be combined into one circuit with one
common binary adder. The mode input M controls the operation. When M=0, the circuit is
adder circuit. When M=1, it becomes subtractor.

13
4 BIT BCD ADDER:
Consider the arithmetic addition of two decimal digits in BCD, together with an input
carry from a previous stage. Since each input digit does not exceed 9, the output sum cannot
be greater than 19, the 1 in the sum being an input carry. The output of two decimal digits must
be represented in BCD and should appear in the form listed in the columns.
ABCD adder that adds 2 BCD digits and produce a sum digit in BCD. The 2 decimal
digits, together with the input carry, are first added in the top 4 bit adder to produce the binary
sum.
PIN DIAGRAM FOR IC 7483:

4-BIT BINARY ADDER:

LOGIC DIAGRAM:

14
4-BIT BINARY SUBTRACTOR:
LOGIC DIAGRAM:

4-BIT BINARY ADDER/SUBTRACTOR:

LOGIC DIAGRAM:

15
TRUTH TABLE:

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

PROCEDURE:
I. Connections were given as per circuit diagram.
II. Logical inputs were given as per truth table
III. Observe the logical output and verify with the truth tables.

OBSERVATION :

RESULT:

Preparation 5

Conduction &
5
Observation Result Execution

Viva-Voce &
5
Inference
Record 5
Total 20

16
 DESIGN AND IMPLEMENTATION OF CODE CONVERTOR

EXPT. NO. :4
DATE :

AIM:
To design and implement 4-bit
I. Binary to gray code converter
II. Gray to binary code converter
III. BCD to excess-3 code converter
IV. Excess-3 to BCD code converter

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. X-OR GATE IC 7486 1
2. AND GATE IC 7408 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. IC TRAINER KIT - 1
6. PATCH CORDS - 35

THEORY:
The availability of large variety of codes for the same discrete elements of information results
in the use of different codes by different systems. A conversion circuit must be inserted between
the two systems if each uses different codes for same information. Thus, code converter is a
circuit that makes the two systems compatible even though each uses different binary code.
The bit combination assigned to binary code to gray code. Since each code uses four
bits to represent a decimal digit. There are four inputs and four outputs. Gray code is a non-
weighted code.
The input variable are designated as B3, B2, B1, B0 and the output variables are
designated as C3, C2, C1, Co. from the truth table, combinational circuit is designed. The
Boolean functions are obtained from K-Map for each output variable.

17
 A code converter is a circuit that makes the two systems compatible even though each
uses a different binary code. To convert from binary code to Excess-3 code, the input lines
must supply the bit combination of elements as specified by code and the output lines generate
the corresponding bit combination of code. Each one of the four maps represents one of the
four outputs of the circuit as a function of the four input variables.
A two-level logic diagram may be obtained directly from the Boolean expressions
derived by the maps. These are various other possibilities for a logic diagram that implements
this circuit. Now the OR gate whose output is C+D has been used to implement partially each
of three outputs.

I. BINARY TO GRAY CODE CONVERTOR:

TRUTH TABLE:
Binary Code I/P Gray Code O/P
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

18
K-Map for G3:

G3 = B3
K-Map for G2:

K-Map for G1:

K-Map for G0:

19
LOGIC DIAGRAM:

II. GRAY CODE TO BINARY CONVERTOR :

TRUTH TABLE:
Gray Code I/P Binary Output
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
1 0 0 0 1 1 1 1

20
 1 0 0 1 1 1 1 0
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 0 1 0 1 1
1 1 1 1 1 0 1 0

K-Map for B3:

B3 = G3
K-Map for B2:

K-Map for B1:

21
K-Map for B0:

LOGIC DIAGRAM:

22
 III. BCD TO EXCESS-3 CONVERTOR
TRUTH TABLE:
BCD I/P Excess 3 O/P
B3 B2 B1 B0 E3 E2 E1 E0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0

K-Map for E3:

23
 E3 = B3 + B2 (B0 + B1)

K-Map for E2:

K-Map for E1:

K-Map for E0:

24
LOGIC DIAGRAM:

IV. EXCESS-3 TO BCD CONVERTOR:

TRUTH TABLE:
Excess - 3 I/P BCD O/P
E3 E2 E1 E0 B3 B2 B1 B0
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0

25
 1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1

K-Map for A :

A = X1 X2 + X3 X4 X1

K-Map for B:

K-Map for C:

26
K-Map for D:

27
LOGIC DIAGRAM:

PROCEDURE:
I. Connections were given as per circuit diagram.
II. Logical inputs were given as per truth table
III. Observe the logical output and verify with the truth tables.

OBSERVATION :

28
RESULT:

Preparation 5

Conduction &
5
Observation Result Execution

Viva-Voce &
5
Inference
Record 5
Total 20

29
DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND DEMULTIPLEXER

EXPT. NO. : 5
DATE :

AIM:
To design and implement multiplexer and demultiplexer using logic gates and study of
IC 74150 and IC 74154.

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. 3 I/P AND GATE IC 7411 2
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
2. IC TRAINER KIT - 1
3. PATCH CORDS - 32

THEORY:
MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a smaller number of
channels or lines. A digital multiplexer is a combinational circuit that selects binary
information from one of many input lines and directs it to a single output line. The selection of
a particular input line is controlled by a set of selection lines. Normally there are 2n input line
and n selection lines whose bit combination determine which input is selected.
DEMULTIPLEXER:
The function of Demultiplexer is in contrast to multiplexer function. It takes
information from one line and distributes it to a given number of output lines. For this reason,
the demultiplexer is also known as a data distributor. Decoder can also be used as
demultiplexer.
In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates. The data
select lines enable only one gate at a time and the data on the data input line will pass through
the selected gate to the associated data output line.
4:1 MULTIPLEXER:

30
BLOCK DIAGRAM:

FUNCTION TABLE:
S1 S0 INPUTS OUTPUT Y
0 0 D0 → D0 S1’ S0’
0 1 D1 → D1 S1’ S0
1 0 D2 → D2 S1 S0’
1 1 D3 → D3 S1 S0
Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0
LOGIC DIAGRAM:

31
TRUTH TABLE:
S1 S0 Y = OUTPUT
0 0 D0
0 1 D1
1 0 D2
1 1 D3

1:4 DEMULTIPLEXER:
BLOCK DIAGRAM:

FUNCTION TABLE:
S1 S0 INPUT OUTPUT
0 0 X → D0 = X S1’ S0’
0 1 X → D1 = X S1’ S0
1 0 X → D2 = X S1 S0’
1 1 X → D3 = X S1 S0
Y = X S1’ S0’ + X S1’ S0 + X S1 S0’ + X S1 S0

32
LOGIC DIAGRAM:

TRUTH TABLE:
INPUT OUTPUT
S1 S0 I/P D0 D1 D2 D3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1

33
PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

OBSERVATION :

RESULT:

Preparation 5
Conduction &
5
Observation Result Execution

Viva-Voce &
5
Inference
Record 5
Total 20

34
 DESIGN OF ENCODERS AND DECODERS

EXPT. NO. : 6
DATE :

AIM:
To design and implement
I. 4 to 2 Encoder using basic gates.
II. 2 to 4 Decoder using basic gates.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. AND GATE IC 7408 2
2. X-OR GATE IC 7486 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. 4-BIT MAGNITUDE IC 7485 2
COMPARATOR
6. IC TRAINER KIT - 1
7. PATCH CORDS - 30

4 to 2 Encoder
Logic Diagram:

35
Truth Table:
Inputs Outputs
Y3 Y2 Y1 Y0 A1 A0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1

2 to 4 Decoder

Logic Diagram:

Truth Table:

Enable Inputs Outputs

E A1 A0 Y3 Y2 Y1 Y0
0 x x 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0

36
PROCEDURE:
I. Connections are given as per circuit diagram.
II. Logical inputs are given as per circuit diagram.
III. Observe the output and verify the truth table.

OBSERVATION :

RESULT:

Preparation 5

Conduction &
5
Observation Result Execution

Viva-Voce &
5
Inference
Record 5
Total 20

37
 DESIGN AND IMPLEMENTATION OF MAGNITUDE COMPARATOR

EXPT. NO. : 7
DATE :

AIM:
To design and implement
III. 2 – bit magnitude comparator using basic gates.
IV. 8 – bit magnitude comparator using IC 7485.

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. AND GATE IC 7408 2
2. X-OR GATE IC 7486 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. 4-BIT MAGNITUDE IC 7485 2
COMPARATOR
6. IC TRAINER KIT - 1
7. PATCH CORDS - 30

THEORY:
The comparison of two numbers is an operator that determine one number is greater
than, less than (or) equal to the other number. A magnitude comparator is a combinational
circuit that compares two numbers A and B and determine their relative magnitude. The
outcome of the comparator is specified by three binary variables that indicate whether A>B,
A=B (or) A<B.
A = A3 A2 A1 A0
B = B3 B2 B1 B0

The equality of the two numbers and B is displayed in a combinational circuit

designated by the symbol (A=B).

38
 This indicates A greater than B, then inspect the relative magnitude of pairs of
significant digits starting from most significant position. A is 0 and that of B is 0.

We have A<B, the sequential comparison can be expanded as

A>B = A3B31 + X3A2B21 + X3X2A1B11 + X3X2X1A0B01

A<B = A31B3 + X3A21B2 + X3X2A11B1 + X3X2X1A01B0

The same circuit can be used to compare the relative magnitude of two BCD digits.
Where, A = B is expanded as,

A = B = (A3 + B3) (A2 + B2) (A1 + B1) (A0 + B0)

x3 x2 x1 x0
2 BIT MAGNITUDE COMPARATOR:
TRUTH TABLE:
A1 A0 B1 B0 A>B A=B A<B
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0

39
K MAP

40
PIN DIAGRAM FOR IC 7485:

LOGIC DIAGRAM:

A1 A0 B1 B0
1

7404
2

3 11 10
2

4
6 A=B
7486 5
4

6 13 12
5

1
3
2
1

7408 3 A>B
2

4 7432
6
5

9
8
10
9

12 8 A<B
10

11
13
U1A
1
3
4

2
6
5

7408

8 BIT MAGNITUDE COMPARATOR:

41
LOGIC DIAGRAM:

TRUTH TABLE:
A7-0 B7-0 A>B A=B A<B
0000 0000 0000 0000 0 1 0
0001 0001 0000 0000 1 0 0
0000 0000 0001 0001 0 0 1
PROCEDURE:
IV. Connections are given as per circuit diagram.
V. Logical inputs are given as per circuit diagram.
VI. Observe the output and verify the truth table.

OBSERVATION :

RESULT:

Preparation 5

Conduction &
5
Observation Result Execution

Viva-Voce &
5
Inference
Record 5
Total 20

42
 DESIGN AND IMPLEMENTATION OF 4 BIT RIPPLE COUNTER AND MOD10
RIPPLE COUNTER
EXPT. NO. :8
DATE :
AIM:
To design and verify 4 bit ripple counter mod 10 ripple counter.
APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. JK FLIP FLOP IC 7473 2
2. NAND GATE IC 7400 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 30

THEORY:
A counter is a register capable of counting number of clock pulse arriving at its clock input.
Counter represents the number of clock pulses arrived. A specified sequence of states appears
as counter output. This is the main difference between a register and a counter. There are two
types of counter, synchronous and asynchronous. In synchronous common clock is given to all
flip flop and in asynchronous first flip flop is clocked by external pulse and then each
successive flip flop is clocked by Q or Q output of previous stage. A soon the clock of second
stage is triggered by output of first stage. Because of inherent propagation delay time all flip
flops are not activated at same time which results in asynchronous operation.

PIN DIAGRAM:

43
4 BIT RIPPLE COUNTER:
LOGIC DIAGRAM:

TRUTH TABLE:

CLK QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1

44
MOD - 10 RIPPLE COUNTER:
LOGIC DIAGRAM:

TRUTH TABLE:
CLK Q3 Q2 Q1 Q0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 0 0 0 0

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

45
OBSERVATION:

RESULT:

Preparation 5
Conduction &
5
Observation Result Execution

Viva-Voce &
5
Inference
Record 5
Total 20

46
 DESIGN AND IMPLEMENTATION OF SHIFT REGISTER

EXPT. NO. : 9
DATE :

AIM:
To design and implement
I. Serial in serial out
II. Serial in parallel out
III. Parallel in serial out
IV. Parallel in parallel out

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. D FLIP FLOP IC 7474 2
2. OR GATE IC 7432 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 35

THEORY:

A register is capable of shifting its binary information in one or both directions is known as
shift register. The logical configuration of shift register consist of a D-Flip flop cascaded with
output of one flip flop connected to input of next flip flop. All flip flops receive common clock
pulses which causes the shift in the output of the flip flop. The simplest possible shift
register is one that uses only flip flop. The output of a given flip flop is connected to the input
of next flip flop of the register. Each clock pulse shifts the content of register one bit position
to right.

47
PIN DIAGRAM:

SERIAL IN SERIAL OUT:

LOGIC DIAGRAM:

TRUTH TABLE:
CLK Serial in Serial out
1 1 0
2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
7 X 1

48
SERIAL IN PARALLEL OUT:
LOGIC DIAGRAM:

TRUTH TABLE:
OUTPUT
CLK DATA QA QB QC QD
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 0
4 1 1 0 0 1

PARALLEL IN SERIAL OUT:

LOGIC DIAGRAM:

A B C D

SHIFT/
LOAD
1 2

74LS04
10

13

12
2

74LS08 74LS08
74LS08
11
3

6
10
2

74LS32 74LS32 74LS32

3

LOGIC 1
10

10
4

Dout
PRE

PRE

PRE

PRE

2 5 12 9 2 5 12 9
Din D Q D Q D Q D Q

3 11 3 11
CLK CLK CLK CLK
CLR

CLR

CLR

CLR

74LS74 74LS74
13

13
1

CLK
LOGIC 1

49
TRUTH TABLE:
CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1

PARALLEL IN PARALLEL OUT:

LOGIC DIAGRAM:

TRUTH TABLE:
DATA INPUT OUTPUT
CLK DA DB DC DD QA QB QC QD
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

50
OBSERVATION :

RESULT:

Preparation 5

Conduction &
5
Observation Result Execution

Viva-Voce &
5
Inference
Record 5
Total 20

51