Digital Systems Design

Mealy & Moore Sequential Circuits

Dr. Aqeel Sahi

 Mealy versus Moore Sequential Circuits
There are two ways to design a clocked sequential circuit:
1. Mealy Machine: Outputs depend on present state and inputs
2. Moore Machine: Outputs depend on present state only

Analysis of Clocked Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 21
 Mealy Machine
! The outputs are a function of the present state and Inputs

! The outputs are NOT synchronized with the clock

! The outputs may change if inputs change during the clock cycle

! The outputs may have momentary false values (called glitches)

! The correct outputs are present just before the edge of the clock

Analysis of Clocked Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 22
 Mealy State Diagram
! An example of a Mealy state
diagram is shown on the right

! Each arc is labeled with:

Input / Output

! The output is shown on the

arcs of the state diagram

! The output depends on the

current state and input

! Notice that State 11 cannot be

reached from the other states
Analysis of Clocked Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 23
 Tracing a Mealy State Diagram

Cycle 0 1 2 3 4 5 6 7 8

Input x 0 1 1 0 1 1 1 1 0

Present ? 0 0 1 0 0 1 1 1
State A B ? 0 1 0 0 1 0 0 0
Output z 0 0 0 0 0 0 1 1 0

! When the circuit is powered, the initial state (AB) is unknown

! Even though the initial state is unknown, the input x = 0 forces

a transition to state AB = 00, regardless of the present state

! Sometimes, a reset input is used to initialize the state to 00

Analysis of Clocked Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 24
 False Output in the Timing Diagram
Cycle 0 1 2 3 4 5 6 7 8
Input x 0 1 1 0 1 1 1 1 0
Present ? 0 0 1 0 0 1 1 1
State A B ? 0 1 0 0 1 0 0 0
Output z 0 0 0 0 0 0 1 1 0

Negative edge-triggered
A

Analysis of Clocked Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 25
 Moore Machine
! The outputs are a function of the Flip-Flop outputs only

! The outputs depend on the current state only

! The outputs are synchronized with the clock

! Glitches cannot appear in the outputs (even if inputs change)

! A given design might mix between Mealy and Moore

Analysis of Clocked Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 26
 Moore State Diagram

0
! An example of a Moore state
0
diagram is shown on the right
00 1 01
0 0
! Arcs are labeled with input only

0 0 1
! The output is shown inside the
state: (State / Output)
11 10
! The output depends on the 1 1 0
current state only
1

Analysis of Clocked Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 27
 Tracing a Moore State Diagram
! When the circuit is powered, the initial 0
state (AB) and output are unknown 0

! Input x = 0 resets the state AB to 00. 00 1 01

0 0
Can also be done with a reset signal.

Cycle 0 1 2 3 4 5 6 7 8 0 0 1

Input x 0 1 1 0 1 1 1 1 0
11 10
Present ? 0 0 1 0 0 1 1 1 1 1 0
State A B ? 0 1 0 0 1 0 1 1
1
Output z ? 0 0 0 0 0 0 1 1
Analysis of Clocked Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 28
 Timing Diagram of a Moore Machine
Cycle 0 1 2 3 4 5 6 7 8
The output is
Input x 0 1 1 0 1 1 1 1 0
synchronized with the
Present ? 0 0 1 0 0 1 1 1
clock. No false output
State A B ? 0 1 0 0 1 0 1 1
(or glitch) can appear.
Output z ? 0 0 0 0 0 0 1 1

Negative edge-triggered
A

Analysis of Clocked Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 29
 The Design Procedure
Given a Description (or Specification) of the Problem

1. Obtain a state diagram for the sequential circuit

2. Assign binary codes to the states and fill the state table

3. Select the type of Flip-Flops and derive the FF input equations

4. Derive the output equations

5. Draw the circuit diagram

6. Verify the correctness of the final design (verification)

Sequential Circuit Design COE 202 – Digital Logic Design © Muhamed Mudawar – slide 3
 The State Diagram
! A state is an abstraction of memory

! A state remembers a history of inputs applied to the circuit

! Examples:

" State S0 represents the fact that the last input is a 0

" State S1 represents the fact that the last input is a 1

" State S2 represents the fact that the last two-input sequence is "11"

! Obtaining the state diagram is the most important step

! Requires experience and good understanding of the problem

Sequential Circuit Design COE 202 – Digital Logic Design © Muhamed Mudawar – slide 4
 Example: Sequence Detector
! A sequence detector is a sequential circuit

! Detects a specific sequence of bits in the input

! The input is a serial bit stream:

One input bit ! is fed to the sequence detector each cycle

! The output is also a bit stream: One output bit " each cycle

Indicates whether a given sequence is detected or not

! Sequence "
Detector

Sequential Circuit Design COE 202 – Digital Logic Design © Muhamed Mudawar – slide 5
 State Diagram for a Sequence Detector
! Example: Design a circuit that detects the input sequence "111"
! Begin in an initial state: call it S0
S0 indicates that a 1 is NOT detected yet
As long as the input # is 0, remain in the initial state S0
! Add a state (call it S1) that detects the first 1 in the input
! Add a state (call it S2) that detects the input sequence "11"
! Add a state (call it S3) that detects the input sequence "111"

0
1 1 1
S0 S1 S2 S3

Sequential Circuit Design COE 202 – Digital Logic Design © Muhamed Mudawar – slide 6
 Complete the State Diagram
Moore Design: Assign Output to States
The output in S0, S1, and S2 should be 0 0
0
The output in S3 should be 1
S0 1 S1
0 0
Now complete the state diagram:
Add transitions from S1, S2, S3 0 0 1
back to S0 if the input is 0
Add transition from S3 to itself if S3 S2
1 1 0
the input is 1 to detect sequences
longer than three 1's
1
Sequential Circuit Design COE 202 – Digital Logic Design © Muhamed Mudawar – slide 7
 State Assignment
! Each state must be assigned a unique binary code

! If there are $ states then

The minimum number of state bits: % = '()2 $

# is the smallest integer ≥ # (ceiling function)

! In our example, there are four states: S0, S1, S2, and S3

Therefore, the minimum number of state bits (Flip-Flops) = 2

! State assignment: S0 = 00, S1 = 01, S2 = 10 and S3 = 11

! If % bits are used, the number of unused states = 2% − $

! In our example, there are NO unused states

Sequential Circuit Design COE 202 – Digital Logic Design © Muhamed Mudawar – slide 8
 From State Diagram to State Table
0
Present Next State Output
0 State ! = 0 ! = 1 "
S0 1 S1
S0 S0 S1 0
0 0 S1 S0 S2 0
S2 S0 S3 0
0 0 1
S3 S0 S3 1

S3 S2 Present Next State Output

State ! = 0 ! = 1 "
1 1 0
00 00 01 0
State Assignment 01 00 10 0
1
S0 = 00, S1 = 01 10 00 11 0
S2 = 10, S3 = 11 11 00 11 1
Sequential Circuit Design COE 202 – Digital Logic Design © Muhamed Mudawar – slide 9
 Structure of a Moore Sequence Detector
Next Current
! Next State State D Flip State Output
"
Logic Flops Logic

clock

! In our design examples, only D-type Flip-Flops will be used

! They are the simplest to analyze and implement

! Next, we need minimal expressions for

1. Next State Logic

2. Output Logic

Sequential Circuit Design COE 202 – Digital Logic Design © Muhamed Mudawar – slide 10
 Derive Next State an Output Equations
# 0. # 0/
Present Next State Output -. -/ 0 1 -. -/ 0 1
State ! = 0 ! = 1 " 00 0 0 00 0 1
00 00 01 0 01 0 1 01 0 0
01 00 10 0 11 0 1 11 0 1
10 00 11 0
10 0 1 10 0 1
11 00 11 1
-. # + -/ # -. # + -/2 #
Two D-type Flips-Flops
Present State = Flip-Flop Outputs -. and -/
Next State = Flip-Flop Inputs 0. and 0/
Next State equations: 0. = -. # + -/ # and 0/ = -. # + -/2 #
Output equation: 3 = -. -/ (from the state diagram)
Sequential Circuit Design COE 202 – Digital Logic Design © Muhamed Mudawar – slide 11
 Draw the Moore Sequence Detector Circuit
0. = -. # + -/ # , 0/ = -. # + -/2 # 3 = -. -/

Next State Logic

Output
Logic

0. -.

-.2

0/ -/

-/2

Sequential Circuit Design COE 202 – Digital Logic Design © Muhamed Mudawar – slide 12
 Mealy Type Sequence Detector
! Let us redesign a Mealy type "111" sequence detector
! The initial state S0 indicates that a 1 is NOT detected yet
As long as the input ! is 0, remain in the initial state S0
Notice that input / output is written on the arc (Mealy type)
! Add a state (call it S1) that detects the first 1 in the input
! Add a state (call it S2) that detects the input sequence "11"

0/0

S0 1/0 S1 1/0 S2

Sequential Circuit Design COE 202 – Digital Logic Design © Muhamed Mudawar – slide 13
 Complete the Mealy State Diagram
! State S2 is reached after detecting the input sequence "11"
! At S2, if the next input is 1 then the output should be 1
Make a transition from S2 back to itself labeled 1 / 1
No need for state S3, because output is on the arc
! Now complete the state diagram
Add transitions from S1 and S2 back to S0 when input is 0

0/0
0/0 1/1 Mealy Machines
0/0 typically use
1/0 1/0 less states than
S0 S1 S2
Moore Machines
Sequential Circuit Design COE 202 – Digital Logic Design © Muhamed Mudawar – slide 14
 State Assignment and State Table
Three States # Minimum number of state bits (Flip-Flops) = 2
Assign: S0 = 00, S1 = 01, and S2 = 10 (State 11 is Unused)

0/0
0/0 1/1
0/0

S0 1/0 S1 1/0 S2

Present Next State Output " Present Next State Output "
State ! = 0 ! = 1 ! = 0 ! = 1 State ! = 0 ! = 1 ! = 0 ! = 1
S0 S0 S1 0 0 00 00 01 0 0
S1 S0 S2 0 0 01 00 10 0 0
S2 S0 S2 0 1 10 00 10 0 1
Sequential Circuit Design COE 202 – Digital Logic Design © Muhamed Mudawar – slide 15
 Derive Next State and Output Equations
0. 0/ 3
# # #
Present Next State Output " -. -/ 0 1 -. -/ 0 1 -. -/ 0 1
State ! = 0 ! = 1 ! = 0 ! = 1 00 0 0 00 0 1 00 0 0
00 00 01 0 0 01 0 1 01 0 0 01 0 0
01 00 10 0 0 11 X X 11 X X 11 X X
10 00 10 0 1
10 0 1 10 0 0 10 0 1
11 XX XX X X
-. # + -/ # -.2 -/2 # -. #

Present State = Flip-Flop Outputs -. and -/ (state 11 is unused)

Next State = Flip-Flop Inputs 0. and 0/
Flip-Flop Input equations: 0. = -. # + -/ # and 0/ = -.2 -/2 #
Output equation: 3 = -. #
Sequential Circuit Design COE 202 – Digital Logic Design © Muhamed Mudawar – slide 16
 Draw the Mealy Sequence Detector Circuit

0. = -. # + -/ # 0/ = -.2 -/2 # 3 = -. #
Output Logic

Next State
Next State
Logic
Logic
-. -/
0. 0/

-.2 -/2

Reset
Sequential Circuit Design COE 202 – Digital Logic Design © Muhamed Mudawar – slide 17
 Mealy versus Moore Sequence Detector
Mealy Sequence Detector Moore
Sequence
0/0 0
0/0 1/1 Detector
0/0 0

1/0 1/0
S0 1 S1
S0 S1 S2
0 0

In general, Moore state diagrams have 0 0 1

more states than corresponding Mealy.

The drawback of Mealy is that glitches S3 S2

1 1 0
can appear in the output if the input is
not synchronized with the clock.
1
Sequential Circuit Design COE 202 – Digital Logic Design © Muhamed Mudawar – slide 18
 Verification
! Sequential circuits should be verified by showing that the
circuit produces the original state diagram
! Verification can be done manually, or with the help of a
simulation program
! All possible input combinations are applied at each state and
the state variables and outputs are observed
! A reset input is used to reset the circuit to its initial state
! Apply a sequence of inputs to test all the state-input
combinations, i.e., all transitions in the state diagram
! Observe the output and the next state that appears after each
clock edge in the timing diagram
Sequential Circuit Design COE 202 – Digital Logic Design © Muhamed Mudawar – slide 19
 Input Test Sequence
! Required to verify the correct operation of a sequential circuit

! It should test each state transition of the state diagram

! Test sequences can be produced from the state diagram

! Consider the Mealy sequence detector, starting at S0 (reset),

we can use an input test sequence to verify all state transitions:
Input test sequence: reset then x = 0, 1, 0, 1, 1, 0, 1, 1, 1, 1

0/0
0/0 1/1
Reset input
0/0
forces initial
state to be S0 reset S0 1/0 S1 1/0 S2

Sequential Circuit Design COE 202 – Digital Logic Design © Muhamed Mudawar – slide 20
 Verifying the Mealy Sequence Detector
0/0
0/0 1/1
0/0

reset S0 1/0 S1 1/0 S2

Input test sequence: reset then x = 0, 1, 0, 1, 1, 0, 1, 1, 1, 1

cc0 cc1 cc2 cc3 cc4 cc5 cc6 cc7 cc8 cc9 cc10
clock
reset
x 0 1 0 1 1 0 1 1 1 1
Q1 S0 S0 S1 S0 S1 S2 S0 S1 S2 S2
Q0 glitch

z 0 0 0 0 0 0 0 0 1 1
Sequential Circuit Design COE 202 – Digital Logic Design © Muhamed Mudawar – slide 21