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Analog Engineer's Circuit

PWM Generator Circuit

Masashi Miyagawa

Design Goals
Input Output Supply
ViMin ViMax VoMin VoMax Vcc Vee Vref
–2.0V 2.0V 0V 5V 5V 0V 2.5V

Design Description
This circuit utilizes a triangle wave generator and comparator to generate a 500kHz pulse-width-modulated
(PWM) waveform with a duty cycle that is inversely proportional to the input voltage. An op amp and comparator
(U3 and U4) generate a triangle waveform which is applied to the inverting input of a second comparator (U2).
The input voltage is applied to the non-inverting input of U2. By comparing the input waveform to the triangle
wave, a PWM waveform is produced. U2 is placed in the feedback loop of an error amplifier (U1) to improve the
accuracy and linearity of the output waveform.
Error Amplifier Comparator Triangle Wave Generator
C3 100p

R4 10k
R7 5.9k
-
C1 100p
Vsin U3 OPA365
Vcc +
+
R3 10k
- Vref
Vcc
U1 OPA365 ++
+
+

+ U2 TLV3501 Vo
Vi -
Vref
Vcc Vtri
Vref V1 -

+ U4 TLV3501
+
R1 10k

Vcc
R2 10k

C2 100n

R6 10k R5 8.45k

Design Notes
1. Use a comparator with push-pull output and minimal propagation delay.
2. Use an op amp with sufficient slew rate, GBW, and voltage output swing.
3. Place the pole created by C1 below the switching frequency and well above the audio range.
4. Vref must be low impedance (for example, output of an op amp).

SBOA212B – JANUARY 2018 – REVISED OCTOBER 2024 PWM Generator Circuit 1

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Design Steps
1. Set the error amplifier inverting signal gain.
R
Gain = − R4 = − 1 V
V
3

Select R3 = R4 = 10kΩ

2. Determine R1 and R2 to divide Vref to cancel the non-inverting gain.

R R2
Vo_dc = 1 + R4 R1 + R2 × Vref
3

R1 = R2 = R3 = R4 = 10kΩ, Vo_dc = 2 . 5V

3. The amplitude of Vtri must be chosen such that it is greater than the maximum amplitude of Vi (2.0V) to avoid
0% or 100% duty cycle in the PWM output signal. Select Vtri to be 2.1V. The amplitude of V1 = 2.5V.
R
Vtri (Amplitude) = R5 × V1 Amplitude
6

Select R6 to be 10kΩ, then compute R5

V Amplitude × R6
R5 = tri = 8 . 4kΩ ≈ 8 . 45kΩ (Standard Value)
V1 Amplitude

4. Set the oscillation frequency to 500kHz.

R
f t = 4 × R ×6R × C
7 5 3

Set C3 = 100pF, then compute R7

R
R7 = 4 × f × 6R × C = 5 . 92kΩ ≈ 5 . 90kΩ (Standard Value)
t 5 3

5. Choose C1 to limit amplifier bandwidth to below switching frequency.

f p = 2 × π ×1R × C
4 1

C1 = 100pF f p = 159kHz

6. Select C2 to filter noise from Vref.

C2 = 100nF (Standard Value)

1
f div = R × R = 320Hz
2 × π × C2 × R1 + R2
1 2

2 PWM Generator Circuit SBOA212B – JANUARY 2018 – REVISED OCTOBER 2024

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Design Simulations
DC Simulation Results
T 5.0

4.5

4.0

3.5

3.0
Output

2.5

2.0

1.5

1.0

500.0m

0.0
-2.0 -1.0 0.0 1.0 2.0
Input voltage (V)

Transient Simulation Results

T 2.0

1.0

VIN 0.0

-1.0

-2.0
5.0

Vout 2.5

0.0
50.0u 60.0u 70.0u 80.0u 90.0u 100.0u
Time (s)

Design References
Texas Instruments, Simulation for PWM Generator Circuit, circuit SPICE simulation file
Texas Instruments, Analog PWM Generator 5V, 500kHz PWM Output, reference design

SBOA212B – JANUARY 2018 – REVISED OCTOBER 2024 PWM Generator Circuit 3

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Design Featured Op Amp

OPA2365
Vss 2.2V to 5.5V
VinCM Rail-to-rail
Vout Rail-to-rail
Vos 100µV
Iq 4.6mA
Ib 2pA
UGBW 50MHz
SR 25V/µs
#Channels 2
OPA2365

Design Comparator
TLV3502
Vss 2.2V to 5.5V
VinCM Rail-to-rail
Vout Rail-to-rail
Vos 1mV
Iq 3.2mA
Ib 2pA
UGBW —
SR —
#Channels 2
TLV3502

Design Alternate Op Amp

OPA2353
Vss 2.7V to 5.5V
VinCM Rail-to-rail
Vout Rail-to-rail
Vos 3mV
Iq 5.2mA
Ib 0.5pA
UGBW 44MHz
SR 22V/µs
#Channels 2
OPA2352

4 PWM Generator Circuit SBOA212B – JANUARY 2018 – REVISED OCTOBER 2024

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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (February 2019) to Revision B (October 2024) Page

• Updated the format for tables, figures, and cross-references throughout the document .................................. 1

Changes from Revision * (January 2018) to Revision A (February 2019) Page

• Downscale the title and changed title role to 'Amplifiers'. Added link to circuit cookbook landing page.............1

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