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Mod 10 Counter For Downloading

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16 views3 pages

Mod 10 Counter For Downloading

Uploaded by

chiku0191chavan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Mod 10 counter for downloading

----------------------------------------------------------------------------------

-- Company:

-- Engineer:

--

-- Create Date: 00:56:39 01/01/2008

-- Design Name:

-- Module Name: vishakha - Behavioral

-- Project Name:

-- Target Devices:

-- Tool versions:

-- Description:

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity count1 is

Port (

clk : in std_logic;

up_down : in STD_LOGIC;

output : out STD_LOGIC_VECTOR (3 downto 0);

rst : in STD_LOGIC);

end count1;

architecture Behavioral of count1 is

signal clk_new: std_logic;

signal count: std_logic_vector(3 downto 0):="0000";

signal divider:std_logic_vector(21 downto 0);

begin

process(rst,clk)

begin

if (rst='0')then

divider<=(others=>'0');

elsif(clk' event and clk='1')then

divider<=divider+1;

end if;
end process;

clk_new<=divider(21);

process(clk_new)

begin

if(clk_new' event and clk_new ='1')then

if(rst='0')then

count<="0000";

elsif(up_down='1')then

if(count="1001")then count<="0000"; else

count <= count+1;

end if;

elsif(up_down='0')then

if(count="0000")then count<="1001"; else

count<= count-1;

end if;

end if;

end if;

end process;

output<= count;

end Behavioral;

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