Proceedings of the Asia-Pacific Microwave Conference 2011

Analysis of IBIS Model Performance in Simulation of Simultaneous

Switching Noise
Yuancheng Ji #1, Koen Mouthaan #2, Neelakantam V. Venkatarayalu *,#3
#
Department of Electrical and Computer Engineering, National University of Singapore
4 Engineering Drive 3, Singapore 117576
1
[email protected]
2
[email protected]
*
EADS Innovation Works
110 Seletar Aerospace View, Singapore 797562
3
[email protected]
Abstract — Input/Output Buffer Information Specification
(IBIS) models are widely used in signal integrity analysis of
digital devices. Advantages of using IBIS models include II. DEFICIENCIES OF IBIS MODEL
protection of proprietary information and reduction of
simulation time. However, compared with Spice models, IBIS The IBIS model is a behavioral model which does not
models have some inherent deficiencies, which can lead to describe the transistor level internal circuit of an IC. The IBIS
inaccurate results in simultaneous switching noise (SSN) model uses static I/V characteristic data, dynamic V/t
simulations. This paper investigates in detail how the characteristic data and package parasitic information.
deficiencies in the IBIS models translate to inaccurate results in
SSN simulations. Methods to improve SSN are briefly discussed Presently, IBIS models have two inherent deficiencies.
and validated. The investigations will be useful to further Firstly, they model I/O buffers under the assumption that the
improve the accuracy of IBIS models and to enhance their wider power rail voltage is constant. This is not a realistic
acceptance. assumption, because, in reality, the power or ground rail are
Index Terms — IBIS, simultaneous switching noise, not ideal conductors but have parasitic inductances. Hence,
overestimation, gate modulation effect. there are always voltage fluctuations on those rails caused by
the current driven by different circuit blocks. Besides the
I. INTRODUCTION signal current modeled by IBIS models, the total power rail
current also includes the pre-driver current, the bypass
With the increasing density of digital integrated circuits, current, the termination current and so on. Thus, IBIS models
the need for a fast and reasonably accurate I/O buffer model cannot accurately model the real power rail current [5].
emerged. The Input-Output Buffer Information Specification The second deficiency is the absence of gate modulation
(IBIS) model was proposed by IBIS open forum and widely effect modeling [3]. In the IBIS models, the I/V data is
accepted by the industry to address this need. Compared with obtained under a fixed gate voltage Vgs. Thus, the output
Spice models, IBIS models provide advantages of proprietary current in IBIS models is only related to the drain voltage.
information protection and faster simulation times. However, However, in real MOSFET devices, the current has a gate
IBIS models have limitations when simulating simultaneous voltage dependency as:
switching noise (SSN), which is a voltage glitch induced in
ௐ ଶ ଵ
power/ground distribution connections within a chip due to ‫ܫ‬ௗ௦ ൌ ‫ܥݑ‬௢௫ ቂ൫ܸ௚௦ െ ܸ௧௛ ൯ܸௗ௦ െ ܸௗ௦ ቃ linear region (1)
௅ ଶ
switching currents passing through either the wire/substrate
ௐ
inductances or package lead inductances associated with ‫ܫ‬ௗ௦ ൌ ‫ܥݑ‬௢௫ ሺܸ௚௦ െ ܸ௧௛ ሻଶ saturation region (2)
ଶ௅
power or ground rails [1].
Though IBIS models based on newly proposed IBIS Fluctuations in the power and ground voltages do occur in
version 5.0 [2] can simulate SSN accurately, these models reality. These, in turn, produce a change in Vgs , that
have not been widely accepted by manufactures and are eventually results in a change in the drain current Ids. This is
currently not available in most CAD tools. Therefore, called the gate modulation effect. Without the model for the
research to investigate the limitations of present IBIS models gate modulation effect, IBIS models cannot properly capture
in simulation of SSN is still ongoing [3][4]. In this paper we this behaviour. Note that this effect is properly modelled
provide a detailed explanation on how the deficiencies of when using Spice models.
IBIS model translate into inaccurate SSN results. The
deficiencies of IBIS models are introduced in section II and III. IBIS MODEL IN SSN SIMULATION
simulation of SSN is carried out in section III, followed by a
detailed explanation to clarify the mechanisms which cause In order to investigate the performance of IBIS model in
inaccurate performance in section IV. Methods to improve SSN simulations, a simulation circuit as in [3] is set up.
IBIS models for better SSN simulations are discussed in Firstly, a buffer consisting of four identical cascading
section V. And final conclusions are provided in section VI. inverting drivers is defined as in Fig. 1. The drivers used here

978-0-85825-974-4 © 2011 Engineers Australia 1007

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 IN OUT 0.06
Spice
0.04 IBIS

Vout1 (V)
Fig. 1. The buffer with four cascaded inverting drivers. 0.02

Vdd 0.00
L=0.1nH R=0.02ȍ
-0.02

-0.04
Vcc Icc 0 10 20 30
Time (ns)
Fig. 3. The quiet line buffer output response Vout1 using the Spice
model (solid line) and the IBIS model (dotted line).
Rload=50ȍ
Vin Vout2 3.40
Spice
3.36 IBIS

Vcc (V)
3.32

Vout1 3.28

3.24
Quiet
Line Vgnd
3.20
0 10 20 30

L=0.1nH R=0.02ȍ
Time (ns)

Ignd Fig. 4. The SSN response at Vcc using the Spice model (solid line)
and the IBIS model (dotted line).

Fig. 2. Circuit for SSN simulation with four parallel buffers. IV. EXPLANATION FOR THE IBIS MODEL PERFORMANCE
According to the definition of SSN, the SSN at the power
are NXP’s 74LVC04A. Then, the circuit for SSN simulation
rail and ground rail can be calculated as
is setup with four identical buffers connected in parallel to the
ௗூ
same power rail and ground rail as shown in Fig. 2. Simple ܸ௡௢௜௦௘ ൌ ‫ ܮ‬ (3)
ௗ௧
RL circuits are added to model the lossy parasitic inductance
Since the inductance is the same in both two models, the
of the power and ground rails. All the buffers are connected
overestimation of the voltage when using the IBIS model
to 50Ω terminations. Three of the four buffers are driven by a
indicates the current switching rate dI/dt is overestimated.
simultaneous switching input and the fourth buffer input,
The current on the supply rail is simulated and is shown in
called the quiet line, is directly connected to ground.
Fig. 5. From Fig. 5, two important observations are made.
The circuit is simulated with the Spice model provided in
The first observation is that the current when using the IBIS
the NXP website [6] and the IBIS model is generated from
model is smaller than the current when using the Spice
the Spice model using S2IBIS3, a tool to obtain IBIS models
model. This is due to the fact that the pre-driver current,
from Spice models [7]. The Spice simulation results serve as
bypass current, termination current and so on are not
the benchmark to assess the accuracy of the IBIS model. The
accounted for when using the IBIS model. The second
output response of the quiet line buffer has significant noise
observation is that the current switching rate dI/dt when using
as observed in Fig. 3. This noise is the SSN due to the other
the IBIS model is indeed larger than the current switching
three buffers switching simultaneously. From Fig. 3, it is
rate when using the Spice model, which is more clearly
observed that the results using IBIS model overestimate the
presented in Fig. 6. Though not shown, similar behaviour is
noise at the quiet line output response. SSN voltage at the
observed for the current on the ground rail.
power rail and ground rail by the IBIS model should also be
In order to find the reason for the overestimation of current
larger than the voltage when using the Spice model. This is
switching rate when using IBIS models, a simple output
confirmed in Fig. 4, where the SSN on the power rail is
driver is analyzed at the switching edge. We use a CMOS
shown. The SSN on the ground rail was also similar to the
inverter as shown in Fig. 7 to represent the output driver and
result shown in Fig. 4. Thus, it can be concluded that IBIS
take the rising edge as an example. In this analysis we only
models tend to overestimate SSN compared with Spice
consider the nMOS transistor effect as the pMOS transistor
models. This conclusion is in agreement with observations
effect is negligible [8].
made in [3].

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 0.5 By (4) and (5), it is found that the Vgnd and Ids affect each other
Spice through Vgs. When the increase of Ids leads to the increase of
0.4
IBIS the dIds/dt, Vgnd is also increased as in (5), so Vgs is reduced
0.3
leading to reduction in Ids as in (4), which is in opposite to its
Icc (A)

0.2 initial trend. Hence this effect called negative feedback effect
0.1
[1]. IBIS models do not incorporate this negative feedback
effect, because it is assumed that Vgs is constant and equal to
0.0
the maximum drain voltage Vdd. Hence, for the IBIS models,
0 10 20 30
the current always is
Time (ns)
ௐ ଶ ௐ
‫ܫ‬ௗ௦ ൌ ‫ܥݑ‬௢௫ ൫ܸ௚௦ െ ܸ௧௛ ൯ ൌ ‫ܥݑ‬௢௫ ሺܸௗௗ െ ܸ௧௛ ሻଶ (6)
ଶ௅ ଶ௅
Fig. 5. The current at the power rail Icc using the Spice model
(solid line) and the IBIS model (dotted line). From (6), it is obvious that dIds/dt in the IBIS models is larger
than in the Spice models.
0.8 If the first few ground bounces happen in the linear region,
0.6
Spice the current is given by
IBIS
0.4 ௐ ଵ
dI/dt (A/ns)

ଶ
‫ܫ‬ௗ௦ ൌ ‫ܥݑ‬௢௫ ቂ൫ܸ௚௦ െ ܸ௧௛ ൯ܸௗ௦ െ ܸௗ௦ ቃ
0.2 ௅ ଶ
0.0 ௐ ଶ ଵ
ൌ ‫ܥݑ‬௢௫ ቂ൫ܸ௜௡ െ ܸ௚௡ௗ െ ܸ௧௛ ൯ܸௗ௦ െ ܸௗ௦ ቃ (7)
-0.2 ௅ ଶ

-0.4 ௗூ೏ೞ ூ೏ೞ

ܸ௚௡ௗ ൌ ‫ܮ‬ଵ ȉ ൌ ‫ܮ‬ଵ ȉ (8)
ௗ௧ ௧
-0.6
0 10 20 30
In this case, the negative feedback effect still exists but does
Time (ns) not apply in IBIS models for the same reason as in the
saturation region. The switching current in IBIS models is
Fig. 6. The power rail current switching rate dI/dt using the Spice given by
model (solid line) and the IBIS model (dotted line).
ܹ ͳ ଶ
‫ܫ‬ௗ௦ ൌ ‫ܥݑ‬௢௫ ൤൫ܸ௚௦ െ ܸ௧௛ ൯ܸௗ௦ െ ܸௗ௦ ൨
‫ܮ‬ ʹ
Vdd =‫ܥݑ‬௢௫
ௐ ଶ
ቂሺܸௗௗ െ ܸ௧௛ ሻܸௗ௦ െ ܸௗ௦ ቃ
ଵ
(9)
L0 ௅ ଶ

which is still larger than the current in reality and causes the
Vout
Vin overestimation of dIds/dt in the IBIS models. Thus, IBIS
Ids models always overestimate the current switching rate due to
Vgnd the absence of a gate modulation effect model, irrespective of
the fact that the first few ground bounces happen in the
L1 saturation region or the linear region. Similarly, the same
conclusion applies to the falling edge.
Fig. 7. Circuit diagram of the CMOS output driver.

At the beginning of the rising edge, the nMOS transistor is V. METHODS FOR IMPROVEMENT
in the cut off region as Vgs<Vth. When the input voltage Vin
There are mainly two methods for improvement for the
gradually increases from logic 0 and the drain voltage
IBIS models in SSN simulations. First method is to add
gradually decreases from logic 1, the nMOS transistor goes
external circuits to the current IBIS models [3] [4], which are
into the saturation region. If Vin further increases until the
obtained from SSN simulations of the Spice circuits. In
drain voltage is smaller than Vin-Vth, the nMOS transistor
general, this is not a practical method. The second method is
moves into the linear region and keeps in this region even
to modify the current IBIS models themselves by adding
after Vin reaches its steady state.
more information internally to the IBIS model [2]. This
The nMOS transistor drain current Ids is also the switching
method is accepted by the IBIS open forum and has led to a
current passing through the wire/substrate inductance or
newly proposed IBISv5 model [2]. However, this new
package lead (represented by L1) associated with the ground
standard has not been widely adopted by manufacturers and
rails. If the first few ground bounces happen in the saturation
EDA tools yet. BIRD95 [9] is one of the internal
region, then
improvement methods, in which the rising and falling edge
ௐ ଶ ௐ ଶ current waveforms (I/t table) from the power reference
‫ܫ‬ௗ௦ ൌ ‫ܥݑ‬௢௫ ൫ܸ௚௦ െ ܸ௧௛ ൯ ൌ ‫ܥݑ‬௢௫ ൫ܸ௜௡ െ ܸ௚௡ௗ െܸ௧௛ ൯ (4)
ଶ௅ ଶ௅ terminal of the buffer are added in the IBIS model. The aim
ௗூ೏ೞ ூ೏ೞ of BIRD95 is to model the current at power supply rails and
ܸ௚௡ௗ ൌ ‫ܮ‬ଵ ȉ ൌ ‫ܮ‬ଵ ȉ (5)
ௗ௧ ௧

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 Vdd compensation is shown in Fig. 9. It is observed that the
Vcc L=0.1nH R=0.02ȍ improved IBIS model circuit models the Vcc fluctuation much
better than the original IBIS model with reference to the
results from Spice model. The comparison for the Vgnd
Icc difference is also simulated and similar to the result shown in
Circuit I supply rail Fig. 9. As the modeling of fluctuations of the gate voltage is
with IBIS
improved, the quiet line buffer output response Vout1 should
models
also be improved using the improved IBIS model. The
Vgnd comparison of difference in Vout1 between the Spice model
and the IBIS models without and with external current
L=0.1nH R=0.02ȍ compensation is shown in Fig. 10. Indeed, it is observed that
Ignd rail Ignd the accuracy of the quiet line buffer output response is
improved significantly with the external current
Fig. 8. Diagram of the improved IBIS model circuits. compensation. Thus, by providing enough information for the
current at the power reference terminal, the modeling of SSN
0.12
performance in IBIS models can be significantly improved.
Spice-IBIS
0.09
Spice-IBIS(impr.)
0.06 VI. CONCLUSION
Vcc (V)

0.03
The limitations in IBIS models in SSN simulations were
0.00 reviewed and investigated in this paper. A significant
-0.03 overestimation of noise is found to be present in IBIS
simulation results. The reason for this behavior is the
-0.06
0 10 20 30 overestimation of current switching rate dI/dt in the IBIS
Time (ns) models, appearing due to the inability of IBIS models to
capture gate modulation effects. The internal mechanisms for
Fig. 9. The Vcc difference between the Spice model and the
original IBIS model (dotted line) and the Vcc difference between the the overestimation of noise performance while using IBIS
Spice model and the improved IBIS model (solid line). models in SSN simulation were demonstrated. Furthermore,
improvements through current compensation were
0.09 investigated and validated.
Spice-IBIS
0.06 Spice-IBIS(impr.)
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V out1 (V)

0.03 [1] Senthinathan, R., Tubbs, G., and Schuelein, M., “Negative
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-0.03
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-0.06
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