Chapter Five

BASIC COMPUTER ORGANIZATION

AND DESIGN
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BASIC COMPUTER ORGANIZATION AND DESIGN

Chapter Outline
• Instruction Codes

• Computer Registers

• Computer Instructions

• Timing and Control

• Instruction Cycle

• Memory Reference Instructions

• Input-Output and Interrupt

• Complete Computer Description

• Design of Basic Computer

• Design of Accumulator Logic

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INTRODUCTION
• Every different processor type has its own design (different
registers, buses, microoperations, machine instructions, etc)
• Modern processor is a very complex device
• It contains
– Many registers
– Multiple arithmetic units, for both integer and floating point calculations
– The ability to pipeline several consecutive instructions to speed execution
– Etc.
• However, to understand how processors work, we will start with a
simplified processor model
• This is similar to what real processors were like ~25 years ago
• M. Morris Mano introduces a simple processor model he calls the
Basic Computer
• We will use this to introduce processor organization and the
relationship of the RTL(Register-Transfer Level) model to the higher
level computer processor

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INTRODUCTION
• The Internal organization of a digital system is defined by the
sequence of microoperations it performs on data stored in its
registers
• The user of a computer can control the process by means of a
program
• A program is a set of instructions that specify the operations,
operands, and the processing sequence.
• A computer instruction is a binary code that specifies a sequence
of micro-operations for the computer. Each computer has its
unique instruction set
• Instruction codes and data are stored in memory
• The computer reads each instruction from memory and places it
in a control register
• The control unit interprets the binary code of the instruction and
proceeds to execute it by issuing a sequence of micro-operations

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INTRODUCTION
• An Instruction code is a group of bits that instructs the computer
to perform a specific operation (sequence of microoperations). It
is divided into parts (basic part is the operation part)
• The operation code of an instruction is a group of bits that defines
certain operations such as add, subtract, shift, and complement.
• The number of bits required for the operation code depends on
the total number of operations available in the computer
• 2n (or little less) distinct operations  n bit operation code

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THE BASIC COMPUTER

• The Basic Computer has two components, a processor
and memory
• The memory has 4096 words in it
– 4096 = 212, so it takes 12 bits to select a word in memory
• Each word is 16 bits long

CPU RAM
0

15 0

4095

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INSTRUCTIONS
• Program
– A sequence of (machine) instructions
• (Machine) Instruction
– A group of bits that tell the computer to perform a specific
operation (a sequence of micro-operation)

• The instructions of a program, along with any

needed data are stored in memory
• The CPU reads the next instruction from memory
• It is placed in an Instruction Register (IR)
• Control circuitry in control unit then translates the
instruction into the sequence of microoperations
necessary to implement it

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INSTRUCTIONS
• An operation must be performed on some data stored in
processor registers or in memory.
• An instruction code must therefore specify not only the
operation, but also the location of the operands (in
registers or in the memory), and where the result will be
stored (registers/memory)
• Memory words can be specified in instruction codes by
their address
• Processor registers can be specified by assigning to the
instruction another binary code of k bits that specifies
one of 2k registers
• Each computer has its own particular instruction code
format
• Instruction code formats are conceived by computer
designers who specify the architecture of the computer

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INSTRUCTION FORMAT
• A computer instruction is often divided into two parts
– An opcode (Operation Code) that specifies the operation for that
instruction
– An address that specifies the registers and/or locations in memory to
use for that operation
• In the Basic Computer, since the memory contains 4096 (= 212)
words, we needs 12 bit to specify which memory address this
instruction will use
• In the Basic Computer, bit 15 of the instruction specifies the
addressing mode (0: direct addressing, 1: indirect addressing)
• Since the memory words, and hence the instructions, are 16 bits
long, that leaves 3 bits for the instruction’s opcode

Instruction Format
15 14 12 11 0
I Opcode Address

Addressing
mode

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ADDRESSING MODES
• The address field of an instruction can represent either
– Direct address: the address in memory of the data to use (the address of the
operand), or
– Indirect address: the address in memory of the address in memory of the data to
use
Direct addressing Indirect addressing
22 0 ADD 457 35 1 ADD 300

300 1350

457 Operand

1350 Operand

+ +
AC AC

• Effective Address (EA)

– The address, that can be directly used without modification to access an
operand for a computation-type instruction, or as the target address for a
branch-type instruction

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PROCESSOR REGISTERS

• Computer instructions are normally stored in consecutive

memory locations and executed sequentially one at a time
• The control reads an instruction from a specific address in
memory and executes it, and so on
• This type of sequencing needs a counter to calculate the
address of the next instruction after execution of the
current instruction is completed
• It is also necessary to provide a register in the control unit
for storing the instruction code after it is read from memory
• The computer needs processor registers for manipulating
data and a register for holding a memory address

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PROCESSOR REGISTERS
• A processor has many registers to hold instructions, addresses,
data, etc
• The processor has a register, the Program Counter (PC) that holds
the memory address of the next instruction to get
– Since the memory in the Basic Computer only has 4096 locations, the PC only
needs 12 bits
• In a direct or indirect addressing, the processor needs to keep
track of what locations in memory it is addressing: The Address
Register (AR) is used for this
– The AR is a 12 bit register in the Basic Computer
• When an operand is found, using either direct or indirect
addressing, it is placed in the Data Register (DR). The processor
then uses this value as data for its operation
• The Basic Computer has a single general purpose register – the
Accumulator (AC)

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PROCESSOR REGISTERS
• The significance of a general purpose register is that it can be
referred to in instructions
– e.g. load AC with the contents of a specific memory location; store the
contents of AC into a specified memory location
• Often a processor will need a scratch register to store
intermediate results or other temporary data; in the Basic
Computer this is the Temporary Register (TR)
• The Basic Computer uses a very simple model of input/output
(I/O) operations
– Input devices are considered to send 8 bits of character data to the processor
– The processor can send 8 bits of character data to output devices
• The Input Register (INPR) holds an 8 bit character gotten from an
input device
• The Output Register (OUTR) holds an 8 bit character to be send to
an output device

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BASIC COMPUTER REGISTERS

Registers in the Basic Computer

11 0
PC
Memory
11 0
4096 x 16
AR
15 0
IR CPU
15 0 15 0
TR DR
7 0 7 0 15 0
OUTR INPR AC

List of BC Registers
DR 16 Data Register Holds memory operand
AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character
OUTR 8 Output Register Holds output character
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COMMON BUS SYSTEM

• The registers in the Basic Computer are connected
using a bus
• This gives a savings in circuitry over complete
connections between registers

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COMMON BUS SYSTEM

S2
S1 Bus
S0
Memory unit 7
4096 x 16
Address
Write Read

AR 1

LD INR CLR

PC 2

LD INR CLR

DR 3

LD INR CLR

E
ALU AC 4

LD INR CLR

INPR
IR 5

LD
TR 6

LD INR CLR

OUTR Clock
LD
16-bit common bus

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COMMON BUS SYSTEM

Read
INPR
Memory Write
4096 x 16

Address E ALU

AC

L I C

L I C L

L I C DR IR L I C

PC TR

AR OUTR LD

L I C

7 1 2 3 4 5 6

16-bit Common Bus

S0 S1 S2

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COMMON BUS SYSTEM

• S2S1S0: Selects the register/memory that would use the bus
• LD (load): When enabled, the particular register receives the data from
the bus during the next clock pulse transition
• E (extended AC bit): flip-flop holds the carry
• DR, AC, IR, and TR: have 16 bits each
• AR and PC: have 12 bits each since they hold a memory address
– When the contents of AR or PC are applied to the 16-bit common bus, the four most
significant bits are set to zeros
– When AR or PC receives information from the bus, only the 12 least significant bits are
transferred into the register
• INPR and OUTR: communicate with the eight least significant bits in the
bus
• INPR: Receives a character from the input device (keyboard,…etc)
which is then transferred to AC
• OUTR: Receives a character from AC and delivers it to an output device
(say a Monitor)
• Five registers have three control inputs: LD (load), INR (increment), and
CLR (clear)
• Register  binary counter with parallel load and synchronous clear
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COMMON BUS SYSTEM

• Three control lines, S2, S1, and S0 control which register the bus
selects as its input

S2 S1 S0 Register
0 0 0 x
0 0 1 AR
0 1 0 PC
0 1 1 DR
1 0 0 AC
1 0 1 IR
1 1 0 TR
1 1 1 Memory

• Either one of the registers will have its load signal activated, or
the memory will have its read signal activated
– Will determine where the data from the bus gets loaded
• When the 8-bit register OUTR is loaded from the bus, the data
comes from the low order 8 bits on the bus

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Memory Address
• The input data and output data of the memory are
connected to the common bus
• But the memory address is connected to AR
• Therefore, AR must always be used to specify a
memory address
• By using a single register for the address, we eliminate
the need for an address bus that would have been
needed otherwise
– Register  Memory: Write operation
– Memory  Register: Read operation (note that AC
cannot directly read from memory!!)
• Note that the content of any register can be applied
onto the bus and an operation can be performed in the
adder and logic circuit during the same clock cycle

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Memory Address
• The transition at the end of the cycle transfers the content of the
bus into the destination register, and the output of the adder and
logic circuit into the AC
• For example, the two microoperations
DR←AC and AC←DR (Exchange)
can be executed at the same time
• This is done by:
1. place the contents of AC on the bus (S2S1S0=100)
2. enabling the LD (load) input of DR
3. Transferring the contents of the DR through the adder and logic circuit into
AC
4. enabling the LD (load) input of AC
• All during the same clock cycle
• The two transfers occur upon the arrival of the clock pulse
transition at the end of the clock cycle

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BASIC COMPUTER INSTRUCTIONS

• Basic Computer Instruction Format

Memory-Reference Instructions (OP-code = 000 ~ 110)

15 14 12 11 0
I Opcode Address

Register-Reference Instructions (OP-code = 111, I = 0)

15 12 11 0
0 1 1 1 Register operation

Input-Output Instructions (OP-code =111, I = 1)

15 12 11 0
1 1 1 1 I/O operation

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BASIC COMPUTER INSTRUCTIONS

Hex Code
Symbol I=0 I=1 Description
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load AC from memory
STA 3xxx Bxxx Store content of AC into memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero

CLA 7800 Clear AC

CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is positive
SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer

INP F800 Input character to AC

OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt on
IOF F040 Interrupt off

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INSTRUCTION SET COMPLETENESS

A computer should have a set of instructions so that the user can
construct machine language programs to evaluate any function that
is known to be computable.

• Instruction Types
Functional Instructions
- Arithmetic, logic, and shift instructions
- ADD, CMA, INC, CIR, CIL, AND, CLA
Transfer Instructions
- Data transfers between the main memory
and the processor registers
- LDA, STA
Control Instructions
- Program sequencing and control
- BUN, BSA, ISZ
Input/Output Instructions
- Input and output
- INP, OUT

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CONTROL UNIT

• Control unit (CU) of a processor translates from

machine instructions to the control signals for the
microoperations that implement them
• Control units are implemented in one of two ways
• Hardwired Control
– CU is made up of sequential and combinational circuits to generate
the control signals
• Microprogrammed Control
– A control memory on the processor contains microprograms that
activate the necessary control signals

• We will consider a hardwired implementation of the

control unit for the Basic Computer

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TIMING AND CONTROL

Control unit of Basic Computer

Instruction register (IR)

15 14 13 12 11 - 0 Other inputs

3x8
decoder
7 6543 210
D0
I Combinational
D7 Control Control
logic signals

T15

T0

15 14 . . . . 2 1 0
4 x 16
decoder

4-bit Increment (INR)

sequence Clear (CLR)
counter
(SC) Clock

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TIMING SIGNALS
- Generated by 4-bit sequence counter and 416 decoder
- The SC can be incremented or cleared.

- Example: T0, T1, T2, T3, T4, T0, T1, . . .

Assume: At time T4, SC is cleared to 0 if decoder output D3 is active.
D3T4: SC  0
T0 T1 T2 T3 T4 T0
Clock

T0

T1

T2

T3

T4

D3

CLR
SC

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INSTRUCTION CYCLE
• In Basic Computer, a machine instruction is
executed in the following cycle:
1. Fetch an instruction from memory
2. Decode the instruction
3. Read the effective address from memory if the instruction
has an indirect address
4. Execute the instruction
• After an instruction is executed, the cycle
starts again at step 1, for the next
instruction
• Note: Every different processor has its own
(different) instruction cycle

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FETCH and DECODE

• Fetch and Decode T0: AR PC (S0S1S2=010, T0=1)
T1: IR  M [AR], PC  PC + 1 (S0S1S2=111, T1=1)
T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)

T1 S2

T0 S1 Bus
S0

Memory 7
unit
Address
Read

AR 1

LD

PC 2

INR

IR 5

LD
Clock
Common bus

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DETERMINE THE TYPE OF INSTRUCTION

Start
SC  0

T0
AR  PC

T1
IR  M[AR], PC  PC + 1

T2
Decode Opcode in IR(12-14),
AR  IR(0-11), I  IR(15)

(Register or I/O) = 1 = 0 (Memory-reference)

D7

(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)

I I

T3 T3 T3 T3
Execute Execute AR  M[AR] Nothing
input-output register-reference
instruction instruction
SC  0 SC  0 Execute T4
memory-reference
instruction
SC  0

D'7IT3: AR M[AR]
D'7I'T3: Nothing
D7I'T3: Execute a register-reference instr.
D7IT3: Execute an input-output instr.
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REGISTER REFERENCE INSTRUCTIONS

Register Reference Instructions are identified when
- D7 = 1, I = 0
- Register Ref. Instr. is specified in b0 ~ b11 of IR
- Execution starts with timing signal T3

r = D7 IT3 => Register Reference Instruction

Bi = IR(i) , i=0,1,2,...,11
r: SC  0
CLA rB11: AC  0
CLE rB10: E0
CMA rB9: AC  AC’
CME rB8: E  E’
CIR rB7: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB6: AC  shl AC, AC(0)  E, E  AC(15)
INC rB5: AC  AC + 1
SPA rB4: if (AC(15) = 0) then (PC  PC+1)
SNA rB3: if (AC(15) = 1) then (PC  PC+1)
SZA rB2: if (AC = 0) then (PC  PC+1)
SZE rB1: if (E = 0) then (PC  PC+1)
HLT rB0: S  0 (S is a start-stop flip-flop)

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MEMORY REFERENCE INSTRUCTIONS

Operation
Symbol Decoder Symbolic Description

AND D0 AC  AC  M[AR]
ADD D1 AC  AC + M[AR], E  Cout
LDA D2 AC  M[AR]
STA D3 M[AR]  AC
BUN D4 PC  AR
BSA D5 M[AR]  PC, PC  AR + 1
ISZ D6 M[AR]  M[AR] + 1, if M[AR] + 1 = 0 then PC  PC+1

- The effective address of the instruction is in AR and was placed there during
timing signal T2 when I = 0, or during timing signal T3 when I = 1
- Memory cycle is assumed to be short enough to complete in a CPU cycle
- The execution of MR instruction starts with T4
AND to AC
D0T4: DR  M[AR] Read operand
D0T5: AC  AC  DR, SC  0 AND with AC
ADD to AC
D1T4: DR  M[AR] Read operand
D1T5: AC  AC + DR, E  Cout, SC  0 Add to AC and store carry in E

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MEMORY REFERENCE INSTRUCTIONS

LDA: Load to AC
D2T4: DR  M[AR]
D2T5: AC  DR, SC  0
STA: Store AC
D3T4: M[AR]  AC, SC  0
BUN: Branch Unconditionally
D4T4: PC  AR, SC  0
BSA: Branch and Save Return Address
M[AR]  PC, PC  AR + 1
Memory, PC, AR at time T4 Memory, PC after execution

20 0 BSA 135 20 0 BSA 135

PC = 21 Next instruction 21 Next instruction

AR = 135 135 21
136 Subroutine PC = 136 Subroutine

1 BUN 135 1 BUN 135

Memory Memory

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MEMORY REFERENCE INSTRUCTIONS

BSA:
D5T4: M[AR]  PC, AR  AR + 1
D5T5: PC  AR, SC  0

ISZ: Increment and Skip-if-Zero

D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T4: M[AR]  DR, if (DR = 0) then (PC  PC + 1), SC  0

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FLOWCHART FOR MEMORY REFERENCE INSTRUCTIONS

Memory-reference instruction

AND ADD LDA STA

D T 4 D 1T 4 D 2T 4 D 3T 4
0
DR  M[AR] DR  M[AR] DR  M[AR] M[AR]  AC
SC  0

D 0T 5 D 1T 5 D 2T 5
AC  AC  DR AC  AC + DR AC  DR
SC  0 E  Cout SC  0
SC  0

BUN BSA ISZ

D 4T 4 D 5T 4 D 6T 4

PC  AR M[AR]  PC DR  M[AR]
SC  0 AR  AR + 1

D 5T 5 D 6T 5

PC  AR DR  DR + 1
SC  0

D 6T 6
M[AR]  DR
If (DR = 0)
then (PC  PC + 1)
SC  0

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INPUT-OUTPUT AND INTERRUPT

• Instructions and data stored in memory must come from some input device
• Computational results must be transmitted to the user through some output
device
• For the system to communicate with an input device, serial information is
shifted into the input register INPR
• To output information, it is stored in the output register OUTR
• INPR and OUTR communicate with a communication interface serially and
with the AC in parallel. They hold an 8-bit alphanumeric information
• I/O devices are slower than a computer system  we need to synchronize
the timing rate difference between the input/output device and the
computer.
• FGI: 1-bit input flag (Flip-Flop) aimed to control the input operation.
• FGI is set to 1 when a new information is available in the input device and is
cleared to 0 when the information is accepted by the computer
• FGO: 1-bit output flag used as a control flip-flop to control the output
operation
• If FGO is set to 1, then this means that the computer can send out the
information from AC. If it is 0, then the output device is busy and the
computer has to wait!

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INPUT-OUTPUT AND INTERRUPT

A Terminal with a keyboard and a Printer
• Input-Output Configuration
Serial Computer
Input-output communication
terminal registers and
interface flip-flops
INPR Input register - 8 bits Receiver
OUTR Output register - 8 bits Printer interface OUTR FGO
FGI Input flag - 1 bit
FGO Output flag - 1 bit
AC
IEN Interrupt enable - 1 bit
Transmitter
Keyboard interface INPR FGI

Serial Communications Path

Parallel Communications Path
- The terminal sends and receives serial information
- The serial info. from the keyboard is shifted into INPR
- The serial info. for the printer is stored in the OUTR
- INPR and OUTR communicate with the terminal
serially and with the AC in parallel.
- The flags are needed to synchronize the timing
difference between I/O device and the computer

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INPUT-OUTPUT AND INTERRUPT

• The process of input information transfer:
– Initially, FGI is cleared to 0
– An 8-bit alphanumeric code is shifted into INPR (Keyboard key strike) and
the input flag FGI is set to 1
– As long as the flag is set, the information in INPR cannot be changed by
another data entry
– The computer checks the flag bit; if it is 1, the information from INPR is
transferred in parallel into AC and FGI is cleared to 0
– Once the flag is cleared, new information can be shifted into INPR by the
input device (striking another key)
• The process of outputting information:
– Initially, the output flag FGO is set to 1
– The computer checks the flag bit; if it is 1, the information from AC is
transferred in parallel to OUTR and FGO is cleared to 0
– The output accepts the coded information (prints the corresponding
character)
– When the operation is completed, the output device sets FGO back to 1
– The computer does not load a new data information into OUTR when FGO is
0 because this condition indicates that the output device is busy to receive
another information at the moment!!
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PROGRAM CONTROLLED DATA TRANSFER

-- CPU -- -- I/O Device --
/* Input */ /* Initially FGI = 0 */ loop: If FGI = 1 goto loop
loop: If FGI = 0 goto loop
INPR  new data, FGI  1
AC  INPR, FGI  0

/* Output */ /* Initially FGO = 1 */ loop: If FGO = 1 goto loop

loop: If FGO = 0 goto loop consume OUTR, FGO 1
OUTR  AC, FGO  0

FGI=0 FGO=1
Start Input Start Output

FGI  0
AC  Data
yes yes
FGI=0
FGO=0
no
no
AC  INPR
OUTR  AC

yes More FGO  0

Character
yes More
no Character
END no
END
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INPUT-OUTPUT INSTRUCTIONS

D7IT3 = p
IR(i) = Bi, i = 6, …, 11

p: SC  0 Clear SC
INP pB11: AC(0-7)  INPR, FGI  0 Input char. to AC
OUT pB10: OUTR  AC(0-7), FGO  0 Output char. from AC
SKI pB9: if(FGI = 1) then (PC  PC + 1) Skip on input flag
SKO pB8: if(FGO = 1) then (PC  PC + 1) Skip on output flag
ION pB7: IEN  1 Interrupt enable on
IOF pB6: IEN  0 Interrupt enable off

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INTERRUPT INITIATED INPUT/OUTPUT

• The process of communication just described is
referred to as Programmed Control Transfer
• The computer keeps checking the flag bit, and when it
finds it set, it initiates an information transform (this is
sometimes called Polling)
• This type of transfer is in-efficient due to the
difference of information flow rate between the
computer and the I/O device
• The computer is wasting time while checking the flag
instead of doing some other useful processing task
• An alternative to the programmed controlled procedure
is to let the external device inform the computer when
it is ready for the transfer
• This type of transfer uses the interrupt facility

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INTERRUPT INITIATED INPUT/OUTPUT

- Open communication only when some data has to be passed --> interrupt.

- The I/O interface, instead of the CPU, monitors the I/O device.

- When the interface founds that the I/O device is ready for data transfer,
it generates an interrupt request to the CPU

- Upon detecting an interrupt, the CPU stops momentarily the task

it is doing, branches to the service routine to process the data
transfer, and then returns to the task it was performing.

* IEN (Interrupt-enable flip-flop)

- can be set and cleared by instructions

- when cleared, the computer cannot be interrupted

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INTERRUPT INITIATED INPUT/OUTPUT

• While the computer is running a program, it does not check the
flags
• Instead:
– When a flag is set, the computer is immediately interrupted from proceeding
with the current program
– The computer stops what it is doing to take care of the input or output transfer
– Then, it returns to the current program to continue what it was doing before
the interrupt

• The interrupt facility can be enabled or disabled via a

flip-flop called IEN
• The interrupt enable flip-flop IEN can be set and
cleared with two instructions (IOF, ION):
– IOF: IEN  0 (the computer cannot be interrupted)
– ION: IEN  1 (the computer can be interrupted)
• Another flip-flop (called the interrupt flip-flop R) is used in the
computer’s interrupt facility to decide when to go through the
interrupt cycle

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INTERRUPT INITIATED INPUT/OUTPUT

• FGI and FGO are different here compared to the way they acted in an
earlier discussion!!
• So, the computer is either in an Instruction Cycle or in an Interrupt
Cycle
• The interrupt cycle is a hardware implementation of a branch and
save return address operation (BSA)
• The return address available in PC is stored in a specific location
where it can be found later when the program returns to the
instruction at which it was interrupted
• This location may be a processor register, a memory stack, or a
specific memory location
• For our computer, we choose the memory location at address 0 as a
place for storing the return address
• Control then inserts address 1 into PC: this means that the first
instruction of the interrupt service routine should be stored in
memory at address 1, or, the programmer must store a branch
instruction that sends the control to an interrupt service routine!!

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FLOWCHART FOR INTERRUPT CYCLE

R = Interrupt f/f
Instruction cycle =0 =1 Interrupt cycle
R

Fetch and decode Store return address

instructions in location 0
M[0]  PC

Execute =0
IEN
instructions
=1 Branch to location 1
PC  1
=1
FGI
=0
=1 IEN  0
FGO R0
=0
R1

- The interrupt cycle is a HW implementation of a branch

and save return address operation.
- At the beginning of the next instruction cycle, the
instruction that is read from memory is in address 1.
- At memory address 1, the programmer must store a branch instruction
that sends the control to an interrupt service routine
- The instruction that returns the control to the original
program is "indirect BUN 0"

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REGISTER TRANSFER OPERATIONS IN INTERRUPT CYCLE

Memory
Before interrupt After interrupt cycle

0 0 256
Example: the computer
1 0 BUN 1120 PC = 1 0 BUN 1120
is interrupted during
Main Main execution of the
255 Program 255 Program
PC = 256
instruction at address
256
1120 1120
255
I/O I/O
Program Program

1 BUN 0 1 BUN 0

Register Transfer Statements for Interrupt Cycle

- R F/F  1 if IEN (FGI + FGO)T0T1T2
 T0T1T2 (IEN)(FGI + FGO): R  1

- The fetch and decode phases of the instruction cycle

must be modified Replace T0, T1, T2 with R'T0, R'T1, R'T2
- The interrupt cycle :
RT0: AR  0, TR  PC
RT1: M[AR]  TR, PC  0
RT2: PC  PC + 1, IEN  0, R  0, SC  0

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FURTHER QUESTIONS ON INTERRUPT

Assignment:
How can the CPU recognize the device
requesting an interrupt ?

Since different devices are likely to require

different interrupt service routines, how can
the CPU obtain the starting address of the
appropriate routine in each case ?

Should any device be allowed to interrupt the

CPU while another interrupt is being serviced ?

How can the situation be handled when two or

more interrupt requests occur simultaneously ?

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COMPLETE COMPUTER DESCRIPTION
Flowchart of Operations
start
SC  0, IEN  0, R  0

=0(Instruction =1(Interrupt
R
Cycle) Cycle)
R’T0 RT0
AR  PC AR  0, TR  PC
R’T1 RT1
IR  M[AR], PC  PC + 1 M[AR]  TR, PC  0
R’T2 RT2
AR  IR(0~11), I  IR(15) PC  PC + 1, IEN  0
D0...D7  Decode IR(12 ~ 14) R  0, SC  0

=1(Register or I/O) D7 =0(Memory Ref)

=1 (I/O) =0 (Register) =1(Indir) =0(Dir)

I I

D7IT3 D7I’T3 D7’IT3 D7’I’T3

Execute Execute AR <- M[AR] Idle
I/O RR
Instruction Instruction
Execute MR D7’T4
Instruction

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COMPLETE COMPUTER DESCRIPTION
Microoperations

Fetch RT0: AR  PC
RT1: IR  M[AR], PC  PC + 1
Decode RT2: D0, ..., D7  Decode IR(12 ~ 14),
AR  IR(0 ~ 11), I  IR(15)
Indirect D7IT3: AR  M[AR]
Interrupt
T0T1T2(IEN)(FGI + FGO): R 1
RT0: AR  0, TR  PC
RT1: M[AR]  TR, PC  0
RT2: PC  PC + 1, IEN  0, R  0, SC  0
Memory-Reference
AND D0T4: DR  M[AR]
D0T5: AC  AC  DR, SC  0
ADD D1T4: DR  M[AR]
D1T5: AC  AC + DR, E  Cout, SC  0
LDA D2T4: DR  M[AR]
D2T5: AC  DR, SC  0
STA D3T4: M[AR]  AC, SC  0
BUN D4T4: PC  AR, SC  0
BSA D5T4: M[AR]  PC, AR  AR + 1
D5T5: PC  AR, SC  0
ISZ D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T6: M[AR]  DR, if(DR=0) then (PC  PC + 1),
SC  0

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COMPLETE COMPUTER DESCRIPTION
Microoperations

Register-Reference
D7IT3 = r (Common to all register-reference instr)
IR(i) = Bi (i = 0,1,2, ..., 11)
r: SC  0
CLA rB11: AC  0
CLE rB10: E0
CMA rB9: AC  AC
CME rB8: E  E
CIR rB7: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB6: AC  shl AC, AC(0)  E, E  AC(15)
INC rB5: AC  AC + 1
SPA rB4: If(AC(15) =0) then (PC  PC + 1)
SNA rB3: If(AC(15) =1) then (PC  PC + 1)
SZA rB2: If(AC = 0) then (PC  PC + 1)
SZE rB1: If(E=0) then (PC  PC + 1)
HLT rB0: S0

Input-Output D7IT3 = p (Common to all input-output instructions)

IR(i) = Bi (i = 6,7,8,9,10,11)
p: SC  0
INP pB11: AC(0-7)  INPR, FGI  0
OUT pB10: OUTR  AC(0-7), FGO  0
SKI pB9: If(FGI=1) then (PC  PC + 1)
SKO pB8: If(FGO=1) then (PC  PC + 1)
ION pB7: IEN  1
IOF pB6: IEN  0

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DESIGN OF BASIC COMPUTER(BC)

Hardware Components of BC
A memory unit: 4096 x 16.
Registers:
AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC
Flip-Flops(Status):
I, S, E, R, IEN, FGI, and FGO
Decoders: a 3x8 Opcode decoder
a 4x16 timing decoder
Common bus: 16 bits
Control logic gates:
Adder and Logic circuit: Connected to AC

Control Logic Gates

- Input Controls of the nine registers
- Read and Write Controls of memory
- Set, Clear, or Complement Controls of the flip-flops
- S2, S1, S0 Controls to select a register for the bus
- AC, and Adder and Logic circuit

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CONTROL OF REGISTERS AND MEMORY

Address Register; AR
Scan all of the register transfer statements that change the content of AR:
R’T0: AR  PC LD(AR)
R’T2: AR  IR(0-11) LD(AR)
D’7IT3: AR  M[AR] LD(AR)
RT0: AR  0 CLR(AR)
D5T4: AR  AR + 1 INR(AR)

LD(AR) = R'T0 + R'T2 + D'7IT3

CLR(AR) = RT0
INR(AR) = D5T4

12 12
From bus AR To bus
D'
7
I
LD Clock
T3
T2 INR
CLR
R
T0
D
T4

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CONTROL OF FLAGS
IEN: Interrupt Enable Flag
pB7: IEN  1 (I/O Instruction)
pB6: IEN  0 (I/O Instruction)
RT2: IEN  0 (Interrupt)

p = D7IT3 (Input/Output Instruction)

D
7
p
I
J Q IEN
B
T3 7

B6
K

R
T2

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CONTROL OF COMMON BUS

x1
x2 S
2
Multiplexer
x3
Encoder S bus select
x4 1
x5 inputs
x6 S
0
x7

selected
x1 x2 x3 x4 x5 x6 x7 S2 S1 S0 register
0 0 0 0 0 0 0 0 0 0 none
1 0 0 0 0 0 0 0 0 1 AR
0 1 0 0 0 0 0 0 1 0 PC
0 0 1 0 0 0 0 0 1 1 DR
0 0 0 1 0 0 0 1 0 0 AC
0 0 0 0 1 0 0 1 0 1 IR
0 0 0 0 0 1 0 1 1 0 TR
0 0 0 0 0 0 1 1 1 1 Memory

For AR D4T4: PC  AR
D5T5: PC  AR

x1 = D4T4 + D5T5

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DESIGN OF ACCUMULATOR LOGIC

Circuits associated with AC 16
Adder and
16 16 16
From DR logic AC
circuit To bus
8
From INPR

LD INR CLR Clock

Control
gates

All the statements that change the content of AC

D0T5: AC  AC  DR AND with DR
D1T5: AC  AC + DR Add with DR
D2T5: AC  DR Transfer from DR
pB11: AC(0-7)  INPR Transfer from INPR
rB9: AC  AC Complement
rB7 : AC  shr AC, AC(15)  E Shift right
rB6 : AC  shl AC, AC(0)  E Shift left
rB11 : AC  0 Clear
rB5 : AC  AC + 1 Increment

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CONTROL OF AC REGISTER

Gate structures for controlling

the LD, INR, and CLR of AC

From Adder 16 16 To bus

and Logic AC
D0 AND LD Clock
T5 INR
D1 ADD CLR

D2 DR
T5
p INPR
B 11
r COM
B9
SHR
B7
SHL
B6
INC
B5
CLR
B 11

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ALU (ADDER AND LOGIC CIRCUIT)

One stage of Adder and Logic circuit

DR(i)
AC(i)

AND

C LD
i ADD
FA I J Q
i
AC(i)
DR
C
i+1
K
INPR
From
INPR
bit(i)
COM

SHR

AC(i+1)
SHL

AC(i-1)

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