FPGA Design and Verification

Project Internship Program

Duration – 5 / 15 Weeks
Training – Offline – 4 WEEKS
Research and Project Guidance Online – 1/ 8 /11 WEEKS

PROGRAM HIGHLIGHTS: SAMPLE PROJECT TITLES:

 Comprehensive knowledge of FPGA design and  Design and Simulation of Digital Controller/CPU
verification. Core/Protocols such as UART, SPI, I2C, AXI4
 Mastery of simulation-based, coverage-driven,  Design, Simulation, Implementation and Verification of
and formal verification. Digital Controllers, ALU Cores and protocols such as
 Hands-on experience with FPGA tools like Vivado, UART, SPI, I2C, AXI4 on FPGA Board.
Quartus, and Model Sim.
 SV Verification of Digital Controller/CPU
 Expertise in debugging and optimizing FPGA
Core/Protocols such as UART, SPI, I2C, AXI4
designs.
 UVM Verification of Digital Controller/CPU
OUTCOMES:
• Design and simulate FPGA systems using Verilog, Core/Protocols such as UART, SPI, I2C, AXI4
VHDL, and System Verilog.
• Implement advanced verification techniques
(System Verilog, UVM).
• Perform in-system FPGA debugging using JTAG TOOLS AND RESOURCES
and logic analysers.  Xilinx Vivado Tool, EDA Playground
• Manage and optimize FPGA timing, performance,
and power.
• Verify complex FPGA designs using UVM and
formal verification.
• Debug real-world FPGA design and performance
issues

Month1 Components of a testbench: Stimulus,response, and

Day 1: Introduction to FPGA Design and verification.
Verification (4 hours)  Writing basic testbenches for Verilog modules.
 Hands-on: Simulating Verilog designs using a
 Introduction to FPGA (1 hour) testbench.
 Basics of FPGA architecture: Logic blocks,  Hands-on: Debugging existing testbenches for
programmable interconnects, and I/O blocks. Verilog/VHDL designs.
 Applications of FPGA in various industries
(telecom, automotive, etc.). Day 3: VHDL for Verification (4 hours)
 Differences between FPGAs and other
programmable logic devices (PLDs, ASICs).  VHDL Overview (2 hours)
 Introduction to VHDL language: Syntax and
 FPGA Development Workflow (1 hour) structure.
 Comparison of Verilog and VHDL for FPGA
 Overview of design flow: Specification, design
design.
entry, synthesis, implementation, verification, and
 Hands-on: Writing basic VHDL modules
debugging.
and simulating them.
 Hands-on: Setting up an FPGA development
environment (Vivado, Quartus, or Model Sim).

Writing Testbenches in VHDL (2 hours)
 Testbench structure in VHDL:
Signals, processes, and clocks.
 Writing Testbenches in Verilog (2 hours)  Writing testbenches for simple
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 VHDL designs. groups and cover points.
 Hands-on: Simulating VHDL  Hands-on: Implementing
designs using testbenches. functional coverage in testbenches.

Day 4: Advanced Testbench Techniques (4 hours)  Code Coverage (2 hours)

 Testbench Reusability and Modularity (2 hours)  Measuring how much of the design code is
 Creating modular and reusable testbenches. exercised by the testbench.
 Instantiating multiple testbenches for  Hands-on: Running a simulation and analysing
complex designs. code coverage reports.
 Hands-on:Rewriting testbenches for
modularity and reuse. Day 8: UVM – Universal Verification Methodology (4
hours)
 Debugging Testbenches (2 hours)
 Introduction to UVM (2 hours)
 Common testbench errors and
debugging strategies.  What is UVM and why is it used in
 Using waveforms for testbench validation. verification?
 Hands-on: Debugging existing testbenches for  Key components: UVM testbenches, agents,
Verilog/VHDL designs. and transactions.
 Hands-on: Installing and setting up UVM
Day 5: Introduction to System Verilog for Verification libraries.
(4 hours)
 System Verilog Overview (2 hours)  UVM Environment and Flow (2 hours)
 Evolution of System Verilog from Verilog.  Building a basic UVM testbench environment.
 Key language features: Enhanced data types,  Hands-on: Writing a simple UVM environment
randomization, and assertions. for a basic module.
 Hands-on: Writing simple modules in System
Verilog. Day 9: UVM Testbench Components (4 hours)

 Assertions in System Verilog (2 hours)  Agents, Drivers, and Monitors in UVM (2 hours)
 Overview of System Verilog assertions
(SVA).  Detailed explanation of UVM components and
 Writing basic assertions to check design their roles.
behaviour. Hands-on: Building UVM agents, drivers, and monitors.
 Hands-on: Adding assertions to System
 Sequences and Sequencers (2 hours)
Verilog testbenches.
 Implementing sequences for driving stimulus.
Day 6: Writing Testbenches in System Verilog (4  Hands-on: Writing UVM sequences and
hours) sequencing transactions.
 Testbench Architecture in System Verilog
Day 10: UVM Score boarding and Reporting (4 hours)
(2 hours)
 Components of a System Verilog testbench:
 UVM Scoreboards (2 hours)
Interfaces, virtual classes, and tasks.
 How to use scoreboards for checking expected
 Hands-on: Writing a System Verilog
outputs.
testbench for a basic design.
 Hands-on: Implementing scoreboards in a
UVM testbench.
 Advanced Testbench Constructs (2 hours)
 Using tasks and functions in System Verilog
 UVM Reporting Mechanism (2 hours)
for stimulus generation.
 Hands-on: Writing tasks and functions in a
 Using UVM reporting for debugging and
System Verilog testbench.
verification.
 Hands-on: Generating and analysing UVM
reports.
Day 7: Coverage-Driven Verification (4 hours)
Day 11: Constrained Random Verification (4 hours)
 Functional Coverage in System Verilog (2 hours)
 Introduction to Constrained Random Testing
 Introduction to functional coverage: Cover
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 (2 hours) hours)
 Using randomization in testbenches for robust  Analyzing FPGA resource utilization: LUTs,
testing. flip-flops, BRAM, DSPs.
 Hands-on: Implementing constrained random  Hands-on: Performance profiling using FPGA
stimulus in System Verilog. tools.

 Advanced Randomization Techniques (2  Power Analysis and Optimization (2 hours)

hours)  Techniques for power-aware verification.
 Setting up random constraints and verifying  Hands-on: Running power analysis and
them. optimizing power consumption in FPGA.
 Hands-on: Building random constraints and
monitoring results. Day 16: Synthesis and Post-Synthesis Verification (4
hours)
Day 12: Formal Verification and ABV (4 hours)  Introduction to FPGA Synthesis (2 hours)
 The synthesis process: RTL to gate-level
 Introduction to Formal Verification (2 hours) netlist.
 Hands-on: Running synthesis in
 Overview of formal verification tools and Vivado/Quartus.
methodologies.
 Hands-on: Running a basic formal verification  Post-Synthesis Verification (2 hours)
on a small design.
 Verifying the design after synthesis: Gate-level
 Assertion-Based Verification (ABV) (2 hours) simulation.
 Integrating assertions into formal verification  Hands-on: Running and analysing post-
flows. synthesis verification results.
 Hands-on: Using assertions to verify different
design properties. Day 17: Hardware Debugging Techniques (4 hours)
On-Chip Debugging with JTAG (2 hours)
Day 13: FPGA Timing Constraints (4 hours)  Using JTAG for in-system
 Introduction to Timing Constraints (2 hours) debugging.
 Hands-on: Setting up and using JTAG in
 Timing analysis: Setup, hold times, and clock FPGA designs.
constraints.
 Hands-on: Defining and simulating timing  Logic Analyzers for FPGA Debugging (2 hours)
constraints in FPGA designs.  Using external logic analyzers and internal
logic probes.
 Handling Clock Domain Crossings (2 hours)  Hands-on: Debugging FPGA
 Techniques for managing multiple clock designs using logic analyzers.
domains in FPGAs.
 Hands-on: Designing and verifying clock Day 18: In-System Testing and Debugging (4 hours)
domain crossing circuits.  In-System Verification (2 hours)
 Verifying FPGA designs directly on
Day 14: Timing Closure Techniques (4 hours) hardware.
 Hands-on: Performing in-system testing using
 Techniques for Achieving Timing Closure FPGA tools.
(2 hours)
 Pipelining, retiming, and optimizing synthesis  Debugging Real Hardware Issues (2 hours)
strategies.  Identifying and solving real-world FPGA
 Hands-on: Applying timing closure techniques hardware issues.
to a real design.  Hands-on: Debugging a real
hardware design.
 Hands-on Timing Analysis (2 hours)
 Using FPGA tools (Vivado, Quartus) for Day 19: Final FPGA Timing and Performance (4
timing analysis. hours)
 Hands-on: Analyzing and improving timing  Real-Time Timing and Performance Issues (2
in an FPGA project. hours)
 Identifying timing bottlenecks in real FPGA
Day 15: Performance Verification (4 hours) systems.
 Hands-on: Using timing analysis tools to
 Performance Metrics in FPGA Design (2
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 debug timing issues.  Early Prototyping or Conceptual Design:
 Begin creating early prototypes, models, or
 Real-Time Performance Optimization (2 hours) conceptual designs to validate project
 Advanced techniques for optimizing assumptions.
FPGA performance.  Run initial tests or small-scale simulations to
assess viability.
 Hands-on: Performance profiling and
optimization on real FPGA hardware.
Month – 3 (20 Days)
Day 20: Simulation and Synthesis Verification
Wrap-up (4 hours) Project Phase-2: Development, Testing, and Refinement
1. Development & Iteration:
 Start full-scale development or experimentation
 Full Synthesis and Implementation Flow (4
hours) based on initial designs or prototypes.
 End-to-end FPGA synthesis, implementation,  Implement core features or processes, following
and verification. the project plan.
 Hands-on: Running full synthesis,
implementation, and verification flow on an 2. Testing and Validation:
FPGA design.
 Conduct tests, gather data, and analyse results
MAIN PROJECT to ensure the project is meeting objectives.
 Identify issues, bugs, or areas for
 Design and Simulation of Digital Controller/CPU improvement and iterate as necessary.
Core/Protocols such as UART, SPI, I2C, AXI4
 Design, Simulation, Implementation and 3. Refinement & Optimization:
Verification of Digital Controllers, ALU Cores  Refine and optimize the work based on test
and protocols such as UART, SPI, I2C, AXI4 on results and feedback.
FPGA Board.  Fine-tune performance, usability, or
effectiveness to meet the desired goals.
 SV Verification of Digital Controller/CPU
Core/Protocols such as UART, SPI, I2C, AXI4
 UVM Verification of Digital Controller/CPU 4. Prepare for Final Deliverables:
 Prepare the project documentation, results, or
Core/Protocols such as UART, SPI, I2C, AXI4
reports as needed.
 Finalize the product or outcome in preparation
for review.
Month – 2 (20 Days)

Project Phase-1: Research, Planning, and Initial Final Project Demo and Presentation
Development

 Project Scope Definition: 1. Project Demonstration: Present the final

product, solution, or findings.
 Define the project objectives, deliverables, and  Demonstrate key functionalities or outcomes
success criteria. that align with the project’s goals.
 Identify key stakeholders and gather initial
requirements. 1. Final Presentation:
 Research & Feasibility Study: Summarize the project’s objectives,
 Conduct a literature review or market research challenges, and results.
related to the project. Highlight key learnings, benefits, and future potential.
 Evaluate tools, frameworks, and resources
required for the project.

 Initial Planning & Setup:

 Develop the project timeline and allocate
tasks/resources.
 Set up the necessary tools, environments, and
platforms for development or
experimentation.

CRANES VARSITY (A Division of CSIL) St.Marks Road, Bangalore Ph: 080-6764 4800/4848 ( www.cranesvarsity.com )