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Model Question Paper - ECT203

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62 views3 pages

Model Question Paper - ECT203

Uploaded by

mohdhasikv
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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ELECTRONICS AND COMMUNICATION ENGINEERING

Model Question Paper

A P J Abdul Kalam Technological University

Third Semester B Tech Degree Examination

Branch: Electronics and Communication


Course: ECT 203 Logic Circuit Design
Time: 3 Hrs Max. Marks: 100

PART A
Answer All Questions

1 Convert 203.5210 to binary and hexadecimal. (3) K1


2 Compare bitwise and logical verilog operators (3) K1
3 Prove that NAND and NOR are not associative. (3) K2
4 Convert the expression ABCD+ABC+ACD to minterms. (3) K2
5 Define expressions in Verilog with example. (3) K2
6 Explain the working of a decoder. (3) K1
7 What is race around condition? (3) K1
8 Convert a T flip-flop to D flip-flop. (3) K2
9 Define fan-in and fan-out of logic circuits. (3) K2
10 Define noise margin and how can you calculate it? (3) K2

PART B
Answer one question from each module. Each question carries 14 mark.

Module I

11(A) Subtract 4610 from 10010 using 2’s complement arithmetic. (8) K2
11(B) Give a brief description on keywords and identifiers in Ver- (6) K2
ilog with example.

OR

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ELECTRONICS AND COMMUNICATION ENGINEERING

12(A) Explain the floating and fixed point representation of num- (8) K2
bers
12(A) Explain the differences between programming lanuguages (6) K2
and HDLs

Module II

13(A) Simplify using K-map (7) K3


X
f (A, B, C, D) = m(4, 5, 7, 8, 9, 11, 12, 13, 15)

using K-maps
13(B) Write a Verilog code for implementing above function (7) K3

OR

14(A) Write a Verilog code to implement the basic gates. (7) K3


14(B) Reduce the following Boolean function using K-Map and (7) K3
implement the simplified function using the logic gates
X
f (A, B, C, D) = (0, 1, 4, 5, 6, 8, 9, 10, 12, 13, 14)

Module III

15(A) Design a 3-bit magnitude comparator circuit. (8) K3


15(B) Write a Verilog description for a one bit full adder circuit. (6) K3

OR

16(A) Write a verilog code to implement 4:1 multiplexer (6) K3


16(B) Implement the logic function (8) K3
X
f (A, B, C) = m(0, 1, 4, 7)

using 8 : 1 and 4 : 1 multiplexers.

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ELECTRONICS AND COMMUNICATION ENGINEERING

Module IV

17 Design MOD 12 asynchronous counter using T flip-flop. (14) K3

OR

18(A) Explain the operation of Master Slave JK flipflop. (7) K3


18(B) Derive the ouput Qn+1 in Terms of Jn , Kn and Qn (7) K3

Module V

19(A) Explain in detail about TTL with open collector output con- (8) K2
figuration.
19(B) Draw an ECL basic gate and explain. (6) K2

OR

20(A) Demonstrate the CMOS logic circuit configuration and char- (8) K2
acteristics in detail.
20(B) Compare the characteristics features of TTL and ECL dig- (6) K2
ital logic families

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