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    Assignment Ar

    Uploaded by

    keroadham715

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    Assignment Ar

    Uploaded by

    keroadham715
    2 views5 pages

    Original Title

    Assignment Ar[1]

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    © © All Rights Reserved

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    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    2 views5 pages

    Assignment Ar

    Uploaded by

    keroadham715

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 5

    Name kerolos adham

    Id 221001851

    Q1)
    Cycles per instruction (CPI):
    CPI= Total cycles / Total instructions
    CPI= 12000 cycles/300 instructions = 40 cycles/instructions
    Instructions Per Cycle (IPC):
    IPC = 1/CPI
    IPC= 1/40 cycles/instruction = 0.025 instruction/cycle

    CPI= 40 cycles/instruction IPC= 0.025 instruction/cycle

    Q2) Calculating CPI for each sequence:


    Sequence 1:
    Total cycles = (3*2) + (4*5) + (2*3) = 6 + 20 + 6 =32 million cycles
    CPI= Total cycles / Total instructions = 32/ (3+ 4 + 2) = 32 / 9 = 3.56 cycles/instruction

    Sequence 2:
    Total cycles = (1*2) + (2*5) +(5 * 3) =2+10+15 =27 million cycles
    CPI = Total cycles / Total instructions =27/(1+5+2)=27/8=3.375 cycles/instruction

    Comparing the 2 sequences:


    Sequence 2 has a lower CPIC (3.375) compared to sequence 1 (3.56)
    Therefore, Sequence 2 is faster according to the CPI metric.

    Q3)

    a.11011001 -> 01101101


    xor
    11011001
    + 10110100
    = 01101101

    b.11011001 → 11111101
    xnor
    11011001
    - 11011011
    = 11111101
    c.11011001 -> 00001010
    xor
    11011001
    + 11010011
    = 00001010

    D. 11011001->11111110
    Nand
    11011001
    ! 00100111
    11111110

    Q4
    // Code your testbench here // Code your design here
    // or browse Examples // Code your design here
    // Code your testbench here module OR(
    // or browse Examples input wire x,
    module testbench(); input wire y,
    reg A,B ,C; output reg out
    wire out; );
    always@(x,y)
    Final_module f4(A, B ,C , out); begin
    initial out =(x | y);
    begin end
    $monitor("The output = ",out); endmodule
    A= 1'b1;
    B= 1'b1; module NOT(
    C= 1'b1; input wire x,
    end output reg out
    endmodule );
    always@(x)
    begin
    out =( ~x );
    end
    endmodule

    module AND(
    input wire x,
    input wire y,
    output reg out
    );
    always@(x,y)
    begin
    out =(x & y);
    end
    endmodule

    module Final_module(
    input A, B, C,
    output reg out
    );
    inout wire S;
    inout wire N;
    inout wire V;
    inout wire D;
    inout wire O;

    AND f1(A,B,S);
    OR f2(A,B,N);
    NOT f3(C,V);
    AND f4(C,S,D);
    AND f5(V,N,O);
    OR f6(O,D,out);
    endmodule

    Q5
    module test(); module mux2x1(
    reg [15:0] in; input wire [1:0] in,
    reg [3:0]sel; input wire sel,
    wire out; output reg out
    final11 f(in,sel, out); );
    always @(*)
    initial begin
    begin case(sel)
    in = 16'b1111111111111111; 1'b0: out = in[0];
    sel=4'b1110; 1'b1: out = in[1];
    $monitor(out); endcase
    end end
    endmodule endmodule
    module final11(
    input wire [15:0] in,
    input wire [3:0] sel,
    output reg out
    );
    inout wire [13:0] out_internal;

    mux2x1 m1(in[1:0], sel[0],


    out_internal[0]);
    mux2x1 m2(in[3:2], sel[0],
    out_internal[1]);
    mux2x1 m3(in[5:4], sel[0],
    out_internal[2]);
    mux2x1 m4(in[7:6], sel[0],
    out_internal[3]);
    mux2x1 m5(in[9:8], sel[0],
    out_internal[4]);
    mux2x1 m6(in[11:10], sel[0],
    out_internal[5]);
    mux2x1 m7(in[13:12], sel[0],
    out_internal[6]);
    mux2x1 m8(in[15:14], sel[0],
    out_internal[7]);
    mux2x1 md1(out_internal[1:0], sel[1],
    out_internal[8]);
    mux2x1 md2(out_internal[3:2], sel[1],
    out_internal[9]);
    mux2x1 md3(out_internal[5:4], sel[1],
    out_internal[10]);
    mux2x1 md4(out_internal[7:6], sel[1],
    out_internal[11]);
    mux2x1 mdf1(out_internal[9:8], sel[2],
    out_internal[12]);
    mux2x1 mdf2(out_internal[11:10], sel[2],
    out_internal[13]);
    mux2x1 f1(out_internal[13:12], sel[3],
    out);
    endmodule

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