Special Topics

Assignment 3
Dr. Dheya Mustafa Finite State Machines

Implement a finite state machine (FSM) that recognizes two specific sequences of applied input sym-bols, namely
four consecutive 1s or four consecutive 0s. There is an input w and an output z. Whenever w = 1 orw = 0 for four
consecutive clock pulses the value of z has to be 1; otherwise, z = 0. Overlapping sequences are allowed, so that if
w = 1 for five consecutive clock pulses the output z will be equal to 1 after the fourth and fifthpulses. Figure 1
illustrates the required relationship between w and z.

Clock

Figure 1: Required timing for the output z.

A state diagram for this FSM is shown in Figure 2. For this part you are to manually derive an FSM circuit that
implements this state diagram, including the logic expressions that feed each of the state flip-flops. To implement
the FSM use nine state flip-flops called y8, . . . , y0 and the one-hot state assignment given in Table 1.

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 Reset

A/0
w=0 w=1
1
B/0 0 F/0

w=0 1
1 0
C/0 G/0

w=0 1 0 1

D/0 1 0 H/0

w=0 1

0 E/1 I/1 1

Figure 2: A state diagram for the FSM.

write Verilog code for the FSM in Figure 2. Describe the state table for the FSM by using a Verilog case statement
in an always block, and use another always block to instantiate the state flip-flops. You can use a third always
block or simple assignment statements to specify the output z. Toimplement the FSM, use four state flip-flops y3,
. . . , y0 and binary codes, as shown in Table 3.

State Code
Name y3y2y1y0
A 0000
B 0001
C 0010
D 0011
E 0100
F 0101
G 0110
H 0111
I 1000

Table 3: Binary codes for the FSM.

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A suggested skeleton of the Verilog code is given in Figure 3.

module part2 ( . . . );
. . . define input and output ports

. . . define signals
reg [3:0] y_Q, Y_D; // y_Q represents current state, Y_D represents next state
parameter A = 4’b0000, B = 4’b0001, C = 4’b0010, D = 4’b0011, E = 4’b0100,
F = 4’b0101, G = 4’b0110, H = 4’b0111, I = 4’b1000;

always @(w, y_Q)

begin: state_table
case (y_Q)
A: if (!w) Y_D = B;
else Y_D = F;
. . . remainder of state table
default: Y_D = 4’bxxxx;
endcase
end // state_table

always @(posedge Clock)

begin: state_FFs
...
end // state_FFS

. . . assignments for output z and the LEDs

endmodule

Figure 3: Skeleton Verilog code for the FSM.

Implement your circuit as follows.

1. Create a new project for the FSM.

2. Include in the project your Verilog file that uses the style of code in Figure 3.
3. Before compiling your code it is necessary to explicitly tell the Synthesis tool in Quartus that you wish to
have the finite state machine implemented using the state assignment specified in your Verilog code. If you
do not explicitly give this setting to Quartus, the Synthesis tool will automatically use a state assignment
of its own choosing, and it will ignore the state codes specified in your Verilog code. To make this setting,
choose Assignments > Settings in Quartus, and click on the Compiler Settings item on the left side of
the window, then click on the Advanced Settings (Synthesis) button. As indicated in Figure 4, change
the parameter State Machine Processing to the setting User-Encoded.

4. Compile your project. To examine the circuit produced by Quartus open the RTL Viewer tool. Double-click
on the box shown in the circuit that represents the finite state machine, and determine whether the state
diagram that it shows properly corresponds to the one in Figure 2. To see the state codes used for your FSM, open
the Compilation Report, select the Analysis and Synthesis section of the report, and click on State
Machines.
5. test the circuit’s functionality.

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6. In step 3, you instructed the Quartus Synthesis tool to use the state assignment given in your Verilog code.
To see the result of removing this setting, open again the Quartus settings window by choosing Assign-
ments > Settings, and click on the Compiler Settings item on the left side of the window, then click
on the Advanced Settings (Synthesis) button. Change the setting for State Machine Processing from
User-Encoded to One-Hot. Recompile the circuit and then open the report file, select the Analysis and
Synthesis section of the report, and click on State Machines. Compare the state codes shown to those
given in Table 2, and discuss any differences that you observe.

Figure 4: Specifying the state assignment method in Quartus.