Unit II Introduction to Assembly Language Programming

Assembly Language Programming Basics

An assembly language is the most basic programming language available for any processor. With
assembly language, a programmer works only with operations that are implemented directly on
the physical CPU.

Assembly languages generally lack high-level conveniences such as variables and functions, and
they are not portable between various families of processors. They have the same structures and
set of commands as machine language, but allow a programmer to use names instead of
numbers. This language is still useful for programmers when speed is necessary or when they
need to carry out an operation that is not possible in high-level languages.
Assembly language is specific to a given processor. For e.g. assembly language of 8085 is different
than that of Motorola 6800 microprocessor.

Microprocessor cannot understand a program written in Assembly language. A program known

as Assembler is used to convert Assembly language program to machine language.

Assembly language program to add two numbers

Advantages of Assembly Language

a) The symbolic programming of Assembly Language is easier to understand and saves a lot
of time and effort of the programmer.
b) It is easier to correct errors and modify program instructions.
c) Assembly Language has the same efficiency of execution as the machine level language.

Disadvantages of Assembly Language

a) One of the major disadvantages is that assembly language is machine dependent. A
program written for one computer might not run in other computers with different
hardware configuration.
b) If you are programming in assembly language, you must have detailed knowledge of the
particular microcomputer you are using.
c) Assembly language programs are not portable.

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Classification of Instructions
An instruction is a binary pattern designed inside a microprocessor to perform a specific function.
The entire group of instructions that a microprocessor supports is called Instruction Set. 8085
has 246 instructions. Each instruction is represented by an 8-bit binary value. These 8-bits of
binary value is called Op-Code or Instruction Byte.

a) Data Transfer Instruction

b) Arithmetic Instructions
c) Logical Instructions
d) Branching Instructions
e) Control Instructions
Data Transfer Instruction
These instructions move data between registers, or between memory and registers. These
instructions copy data from source to destination. While copying, the contents of source are not
modified.
Example: MOV, MVI

Arithmetic Instructions
These instructions perform the operations like:
- Addition
- Subtract
- Increment
- Decrement
Any 8-bit number, or the contents of register, or the contents of memory location can be added
to the contents of accumulator. The result (sum) is stored in the accumulator. No two other 8-bit
registers can be added directly.

Any 8-bit number, or the contents of register, or the contents of memory location can be
subtracted from the contents of accumulator. The result is stored in the accumulator. No two
other 8-bit registers can be subtracted directly.
The 8-bit contents of a register or a memory location can be incremented or decremented by 1.
The 16-bit contents of a register pair can be incremented or decremented by 1. Increment or
decrement can be performed on any register or a memory location.

Logical Instructions
These instructions perform logical operations on data stored in registers and memory.
The logical operations are:
- AND
- OR
- XOR
- Rotate
- Compare
- Complement

2
AND, OR, XOR
Any 8-bit data, or the contents of register, or memory location can logically have AND operation,
OR operation, XOR operation with the contents of accumulator. The result is stored in
accumulator.

Rotate
Each bit in the accumulator can be shifted either left or right to the next position.

Compare
Any 8-bit data, or the contents of register, or memory location can be compares for:
- Equality
- Greater Than
- Less Than
with the contents of accumulator.

Complement
The contents of accumulator can be complemented. Each 0 is replaced by 1 and each 1 is replaced
by 0.

Branching Instructions
Branching instructions refer to the act of switching execution to a different instruction sequence
as a result of executing a branch instruction.
The three types of branching instructions are:
- Jump
- Call
- Return
Jump Instructions
The jump instruction transfers the program sequence to the memory address given in the
operand.
JMP 2050 (Jumps to the address 2050)
Call Instructions
The call instruction transfers the program sequence to the memory address given in the operand.
Before transferring, the address of the next instruction after CALL is pushed onto the stack.
CALL 2050 (Transfers program sequence to address 2050)
Return Instructions
The return instruction transfers the program sequence from the subroutine to the calling
program.
RET (Return from the subroutine)

Control Instructions
The control instructions control the operation of microprocessor.

3
Examples:
NOP (No operation is performed)
HLT (The CPU finishes executing the current instruction and halts any further execution)
DI (Disable Interrupts)
EI (Enable Interrupts)

Instruction Set of 8085

Data Transfer Group

Instruction Addressing Modes Operation Description

Loads the accumulator direct

(transfers contents stored in memory
LDA address Direct A M address  location to accumulator)

Stores the accumulator direct

(transfers contents stored in
M  A 
STA address Direct address accumulator to memory address)

tranfers the contents from one register

MOV A, A Register A A to another

MOV A, B Register A B 

MOV A, C Register A C 
MOV A, D Register A D 
MOV A, E Register A E 
MOV A, H Register A H  
MOV A, L Register A L 
MOV B, A Register B A 
MOV B, B Register B B 
MOV B, C Register B C 
MOV B, D Register B D 

4
MOV B, E Register B E 
MOV B, H Register B H  
MOV B, L Register B L 
MOV C, A Register C A 
MOV C, B Register C B 
MOV C, C Register C C  
MOV C, D Register C D 
MOV C, E Register C E 
MOV C, H Register C H  
MOV C, L Register C L 
MOV D, A Register D  A 
MOV D, B Register D  B 

MOV D, C Register D  C 

MOV D, D Register D  D 
MOV D, E Register D  E 
MOV D, H Register D H  
MOV D, L Register D L 
MOV E, A Register E A 
MOV E, B Register E B 
MOV E, C Register E C  
MOV E, D Register E D 
MOV E, E Register E E 
MOV E, H Register E H  

5
MOV E, L Register E L 
MOV H, A Register H  A 
MOV H, B Register H  B 
MOV H, C Register H  C 
MOV H, D Register H  D 
MOV H, E Register H  E 
MOV H, H Register H  H  
MOV H, L Register H  L 
MOV L, A Register L A 
MOV L, B Register L B 
MOV L, C Register L C 
MOV L, D Register L D 
MOV L, E Register L E 
MOV L, H Register L H  
MOV L, L Register L L 
It moves / copies the data stored in
memory location whose address is
given in H-L register pair, to the given
MOV A, M Register indirect A M H L  register.

MOV B, M Register indirect B M H L  

MOV C, M Register indirect C M H L  
MOV D, M Register indirect D M H L  
MOV E, M Register E M H L  
indirect

MOV H, M Register indirect H M H L  

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MOV L, M Register indirect L M H  L  
This instruction moves / copies
the data in the given register to
the memory location addressed
MOV M, A Register M H L  A by H-L register pair.
indirect

MOV M, B Register Indirect M H L  B 

MOV M, C Register M H L  C  
indirect

MOV M, D Register M H L  D 

indirect

MOV M, E Register M H L  E 

indirect

MOV M, H Register M H L  H  
indirect

MOV M, L Register M H L  L 

indirect

This instruction transfers the given

MVI A, data Immediate A data data to the register.

MVI B, data Immediate B data 

MVI C, data Immediate C data 
MVI D, data Immediate D data 
MVI E, data Immediate E data 
MVI H, data Immediate H  data 
MVI L, data Immediate L data 
MVI M, data Immediate M H L  data 

7
Arithmetic Group of Instructions

Instruction Addressing Modes Operation Description

It adds the content stored in

given register with the
accumulator. The result of this
addition is stored in
ADD A Register A  A A accumulator.

ADD B Register A A B 

ADD C Register A A C 
ADD D Register A A D 
ADD E Register A A E 

ADD H Register A A H  

ADD L Register A A L 
adds the content of memory
location whose address is given
in H-L register pair with the
accumulator and the answer is
ADD M Register A A M H L  stored in accumulator.
indirect

It immediately adds the given

data with the accumulator and
the answer will be stored in
ADI data Immediate A A data Accumulator.

It adds the content stored in

given register and content of CY
flag with the content of
accumulator. The result of this
addition is stored in
ADC A Register A A A CY accumulator.

ADC B Register A A B CY 

ADC C Register A A C CY 

8
ADC D Register A A D CY 
ADC E Register A A E CY 
ADC H Register A A H  CY 
ADC L Register A  A L CY 
adds the content of memory
location whose address is given
in H-L register pair to the
accumulator with carry and the
ADC M Register A A M H L  CY answer is stored in accumulator.
indirect

It immediately adds the given

data to the accumulator with
carry and the answer will be
ACI data Immediate A A data  CY stored in Accumulator.

Adds the contents of pair register and

DAD B Register BC  BC  BC store in pair

DAD D Register DE  DE  DE

DAD H Register HL  HL  HL

It subtracts the content stored in given

register with the accumulator. The
result of this subtraction is stored in
SUB A Register A A  A accumulator.

SUB B Register A A B 

SUB C Register A A C  
SUB D Register A A D 
SUB E Register A A E 
SUB H Register A A H  
SUB L Register A A L 

9
 subracts the content of memory
location whose address is given in H-L
register pair with the accumulator and
SUB M Register A A M H L  the answer is stored in accumulator.
indirect

It immediately subtracts the given data

with the accumulator and the answer
SUI data Immediate A A data will be stored in Accumulator.

SBB A Register A A A CY Subtract with borrow

SBB B Register A A B CY 

SBB C Register A A C CY 
SBB D Register A A D CY 
SBB E Register A A E CY 
SBB H Register A A H  CY 
SBB L Register A A L CY 
Subtracts the contents of memory address
given by H-L pair with accumulator with
SBB M Register A A M H L  CY borrow

indirect

SBI data Immediate A A data  CY Subtract immediate with borrow

INR A Register A A1 Increment contents of register by 1

INR B Register B B 1 

INR C Register C C 1 

10
INR D Register D D 1 

INR E Register E E1 

INR H Register H  H  1 

INR L Register L L1 

Increments contents of memory address given

INR M Register M H L  M H L  1 by H-L pair by 1

indirect

INX B Register BC  BC  1 Increment register pair by 1

INX D Register DE  DE  1

INX H Register HL  HL  1

DCR A Register A A1 Decrement contents of register by 1

DCR B Register B B1 

DCR C Register C C1 

DCR D Register D D1 

DCR E Register E E1 

DCR H Register H  H 1 

DCR L Register L L1 

11
 Decrements contents of memory address given
DCR M Register M H L  M H L 1 by H-L pair by 1

indirect

DCX B Register BC  BC 1 Decrement register pair by 1

DCX D Register DE  DE 1

DCX H Register HL  HL 1

RLC Implicit/implied Rotate left through

carry

RAL Implicit/implied Rotate all left

RRC Implicit/implied Rotate right through

carry

RAR Implicit/implied Rotate all right

Logic Transfer Group

Instructions Addressing Modes Operation Description

In this instruction each bit of the

given register contents are ANDed
with each bit of the accumulator
contents (bit by bit). The result is
saved in the accumulator. It does
not affect the contents of the given
ANA A Register A A.AND.A register.

ANA B Register A A.AND.B 

ANA C Register A A.AND.C 

12
ANA D Register A A.AND.D 

ANA E Register A A.AND.E 

ANA H Register A A.AND.H  

ANA L Register A A.AND.L 

In this instruction each bit of the data

stored in the memory location addressed
by H-L register pair are ANDed with
each bit of the accumulator contents (bit
by bit). The result is stored in the
ANA M Register A A.AND.M H L  accumulator like ANA.

Indirect

In this instruction each bit of the given

data is immediately ANDed with each bit
of the accumulator contents (bit by bit).
ANI data Immediate A A.AND.data The result is stored in the accumulator.

In this instruction each bit of the given

register contents are ORed with each bit
of the accumulator contents (bit by bit).
ORA A Register A¬ A.OR.A The result is saved in the accumulator.

ORA B Register A¬ A.OR.B 

ORA C Register A¬ A.OR.C 

ORA D Register A¬ A.OR.D 

13
ORA E Register A A.OR.E 

ORA H Register A¬ A.OR.H  

ORA L Register A¬ A.OR.L 

In this instruction each bit of the
data stored in the memory location
addressed by H-L register pair are
ORed with each bit of the
accumulator contents (bit by bit).
The result is stored in the
ORA M Register A¬ A.OR.M H L  accumulator.
Indirect

In this instruction each bit of the

given data is immediately ORed
with each bit of the accumulator
contents (bit by bit). The result is
ORI data Immediate A¬ A.OR.data stored in the accumulator.

In this instruction each bit of the given

register contents are XORed with each bit
of the accumulator contents (bit by bit).
XRA A Register A¬ AXOR A The result is saved in the accumulator.

XRA B Register A¬ AXOR B 

XRA C Register A¬ A XOR C 

XRA D Register A¬ A XOR D 

XRA E Register A¬ A XOR E 

XRA H Register A¬ A XOR.H  

14
XRA L Register A¬ A XOR L 

In this instruction each bit of the data

stored in the memory location addressed
by H-L register pair are XORed with
each bit of the accumulator contents (bit
by bit). The result is stored in the
XRA M Register A¬ A XOR M H L  accumulator.
Indirect

In this instruction each bit of the given

data is immediately XORed with each bit
of the accumulator contents (bit by bit).
XRI data Immediate A¬ A XOR data The result is stored in the accumulator.

The contents of the given register are

compared with the accumulator contents.
In fact the contents of the register are
subtracted from the contents of
accumulator and the accumulator
CMP A Register contents remain unchanged.

CMP B Register

CMP C Register

CMP D Register

CMP E Register

CMP H Register

CMP L Register

the contents of the addressed memory

location will be compared by the
CMP M Register accumulator contents.

Indirect

In this instruction the given data is

compared with the accumulator
CPI data Immediate contents.

15
 The execution of this instruction inverts

A A COM
each bit of the accumulator contents and
CMA --- the result is saved in the accumulator.

CMC --- CY  CY Complements the carry flag.

It sets the carry flag. Only carry flag gets

STC --- CY  1 affected on this instruction.

Branching Group

Instructions Addressing Modes Operation Description

JMP addr Immediate PC  addr Unconditional Jump

JNZ addr Immediate PC  addrif Z=0. Conditional Jump

JZ addr Immediate PC  addrif Z=1.

JNC addr Immediate PC addrif CY=0.
JC addr Immediate PC  addrif CY=1.
JM addr Immediate PC  addrif S=1.
JP addr Immediate PC  addrif S=0.
JPO addr Immediate PC  addrif P=0.
JPE addr Immediate PC  addrif P=1.
CALL addr Immediate Calls subroutine program. Unconditional Call

Calls subroutine program Conditional Call

CNZ addr Immediate if

Z=1.

Calls subroutine program

CZ addr Immediate if
Z=0.

16
 Calls subroutine program
CNC addr Immediate if
CY=1.

Calls subroutine program

CC addr Immediate if
CY=0.

Calls subroutine program

CM addr Immediate if
S=1.

Calls subroutine program

CP addr Immediate if
S=0.

Calls subroutine program

CPO addr Immediate if
P=0.

Calls subroutine program

CPE addr Immediate if
P=1.

Returns to main program

RNZ Register if
indirect Z=1.

Returns to main program

RZ Register if
indirect Z=0.

Returns to main program

RNC Register if
indirect CY=0.

Returns to main program

RC Register if
indirect CY=1.

Returns to main program

RM Register indirect if S=1.

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 Returns to main program
RP Register if
indirect S=0.

Returns to main program

RPO Register if
indirect P=0.

Returns to main program

RPE Register if
indirect P=1.

Control Instructions Group

Instruction Meaning Explanation

No operation No operation is performed, i.e., the

NOP
instruction is fetched and decoded.

Halt and The CPU finishes executing the current

enter wait instruction and stops further execution. An
HLT
state interrupt or reset is necessary to exit from
the halt state.

Disable The interrupt enable flip-flop is reset and all

DI
interrupts the interrupts are disabled except TRAP.

Enable The interrupt enable flip-flop is set and all

EI
interrupts the interrupts are enabled.

Read This instruction is used to read the status of

RIM interrupt interrupts 7.5, 6.5, 5.5 and read serial data
mask input bit.

Set interrupt This instruction is used to implement the

SIM mask interrupts 7.5, 6.5, 5.5, and serial data
output.

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