ANALOG AND DIGITAL COMMUNICATIONS LAB

Course Code: 22ECC19

Instruction : 2 P Hours per Week

Duration of SEE : 3 Hours
SEE : 50 Marks
CIE : 50 Marks
Credits : 1

LIST OF EXPERIMENTS:

1. AM signals generation and detection.

2. Generation of DSB-SC using Balanced modulator.
3. FM generation and detection.
4. Sampling of continuous time signal and its Reconstruction (PAM).
5. PWM Modulation and Demodulation.
6. PPM Modulation and Demodulation.
7. Data formats / Line coding techniques.
8. PCM generation and detection.
9. Linear Delta Modulation and demodulation.
10. Adaptive Delta Modulation and demodulation.
11. ASK generation and detection.
12. FSK generation and detection.
13. BPSK generation and detection.
14. QPSK generation and detection
15. Structured Enquiry
16. Open-ended Enquiry

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 EXPERIMENT – 1

AM SIGNALS GENERATION AND DETECTION

AIM: To Study the circuit of Amplitude Modulation and Demodulation circuits for various cases
and determine the modulation index for each case.

APPARATUS
 C.R.O. -1No
 Trainer Kit
 Connecting Wires

THEORY: Amplitude Modulation is defined as a process in which the amplitude of the carrier
wave c(t) is varied linearly with the instantaneous amplitude of the message signal m(t).The
standard form of an amplitude modulated (AM) wave is defined by
S(t) = Ac (1 + Ka m(t)) Cos (2π fct)
Where Ka is a constant called the amplitude sensitivity of the modulator.

The demodulation circuit is used to recover the message signal from the incoming AM wave at the
receiver. An envelope detector is a simple and yet highly effective device that is well suited for
the demodulation of AM wave, for which the percentage modulation is less than 100%.Ideally, an
envelope detector produces an output signal that follows the envelop of the input signal wave form
exactly; hence, the name. Some version of this circuit is used in almost all commercial AM radio
receivers.

Frequency Spectrum of the AM Waves

We shall show mathematically that the frequencies present in the AM wave are the carrier
frequency and the first pair of the sideband frequencies, where a sideband is defined as
fSB = fc  nfm and in first pair n=1
When a carrier signal is amplitude modulated, the proportionality constant is made equal to unity
and the instantaneous modulating voltage variations are superimposed onto the carrier amplitude.
Thus, when there is temporarily no modulation, the amplitude of the carrier is equal to its
unmodulated value. When modulation is present, the amplitude of the carrier is varied by the
instantaneous value of the modulating signal. This situation is illustrated in the following figure,
which shows how to max amplitude of amplitude-modulated voltage is made to vary in accordance
with modulating voltage changes. It also shows that something unusual (distortion, as it happens)
will occur if Am is greater than Ac. The fact that the ratio Am /Ac often occurs, leads to the following
definition of the modulation index.

Modulation index: m= Am/Ac

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The modulation index is a number lying between 0 and 1, and it is very often expressed as a
percentage and is called the percentage modulation.

𝐴𝑚 (𝑉𝑚𝑎𝑥 − 𝑉𝑚𝑖𝑛) ⁄2 𝑉𝑚𝑎𝑥 − 𝑉𝑚𝑖𝑛

𝑚= = =
𝐴𝑐 (𝑉𝑚𝑎𝑥 + 𝑉𝑚𝑖𝑛)⁄2 𝑉𝑚𝑎𝑥 + 𝑉𝑚𝑖𝑛

EXPERIMENTAL PROCEDURE

1. Connect AC Adaptor to the mains and the other side to the experimental trainer.
2. Observe the carrier and modulating waveforms and note their frequencies. Carrier
Frequency is around 100 KHz and amplitude is variable from 0-8Vp-p. Modulating Signal
is 1 KHz (approx.).
3. Connect the carrier and modulating signals to the modulator circuit as shown in panel
diagram.
4. Observe the amplitude modulated output in synchronization with the modulating signal on
a dual trace CRO following fig shows the connections.
5. Connect carrier i/p to ground and apply a 2V peak to peak AF signal input to (Modulating
i/p) and adjust P1 for extreme anti clock wise position to get min AC output.
6. Connect the modulating i/p to ground and apply 3 V peak to peak carrier signal to carrier
input and adjusts p2 for extreme clock wise position to get min AC o/p.
7. Connect modulating input and carrier input to ground and adjust p3 for zero DC o/p.
8. Make modulating i/p 2Vpp and carrier i/p 3Vpp peak to peak and adjust p4 for max o/p.
9. Calculate maximum and minimum points on the modulating envelope on a CRO and
calculate depth of modulation from the diagram.
10. Observe that varying the modulating voltage, the depth of modulation varies.
11. During demodulation connect this AM output to the input of the demodulator.
12. By adjusting the R.C time constant (i.e. cutoff frequency) of the filter circuit we can get
minimum distorted output. Calculate the modulation index in all the cases.
13. Observe that this demodulated o/p is amplified has some phase delay because of RC
components.

OBSERVATIONS

Table : 1 CARRIER SIGNAL AMPLITUDE CONSTANT

Ac=________V: fc=________KHz: t=__________msec

Modulation Amplitude of
Amplitude of AF Signal (V) Vmax (V) Vmin (V)
index (m) demodulated signal

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Table: 2 MODULATING SIGNAL AMPLITUDE CONSTANT

Am=________V: fc=________KHz: t=__________msec

Amplitude of carrier Modulation Amplitude of

Vmax (V) Vmin (V)
Signal (V) index (m) demodulated signal

EXPECTED GRAPHS

Under Modulated AM Wave

(m<1)

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 Critical Modulated AM Wave (m=1)

Over Modulated AM Wave (m>1)

Demodulated Signal

RESULT

The working of Amplitude Modulation and Demodulation for various cases is studied and the
modulation index for each case is determined.

DISCUSSION QUESTIONS

1. What are the different detectors used in

a) Critical modulation b) Under modulation c) Over modulation
2. What will happen, if modulation index is greater than 100%?

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3. An amplitude modulated amplifier has a radio frequency output of 50w at 100%
modulation. The internal loss in the modulator is low. What output power is required from
the modulator?
4. In what stage modulation is done in high – power A.M transmissions?
5. What is the significance of modulation index?

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 EXPERIMENT - 2

DSB-SC BALANCED MODULATOR

AIM: To observe DSB-SC amplitude modulated signal using balanced modulator and to calculate
the carrier suppression ratio using MC1496 IC.

APPARATUS

 DSB-SC Balanced modulator Kit

 Signal generator.
 CRO - Dual trace
 Patch cords

THEORY: Two important parameters of a communication system are transmitting power and
bandwidth. Hence in any communication system, saving of power and bandwidth is highly
desirable. In conventional AM, there is wastage in carrier power. In order to save the power in
amplitude modulation the carrier is suppressed, because it doesn’t contain any useful information.
This scheme is called as double side band suppressed carrier amplitude modulation (DSB-SC-
AM).The DSBSC signal is given by

V(t)DSBSC = Vm(t) * Vc(t)

Where Vm(t) = message signal and Vc(t) = carrier signal

Product modulator is used to generate DSB-SC-AM signals. In this modulator, a DSBSC waves
generated by using two AM modulators arranged in a balanced configuration to suppress the
carrier wave.

CIRCUIT DIAGRAM

Fig: DSB-SC BALANCED MODULATOR

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EXPRIMENTAL PROCEDURE

1. Study the circuit provided as front panel of board.

2. Apply a sine wave carrier input 74 KHz and sine wave modulating signal of around 1K-
3K at the respective input pins of circuit shown.
3. Connect the CRO at output pin 6 to observe the balanced AM output.
4. Precisely adjust the amplitude and frequency of modulating and carrier signal to obtain the
stable output as shown in output wave.
5. Vary amplitude of modulating signal and note change in output waveform.
6. Vary the carrier frequency and amplitude. Note the change in output waveform.

OBSERVATIONS TABLE
fm = ______; fc = ______; Ac = _______

Modulating ESBpp (Voltage of side bands) Carrier Suppression ratio in db.

signal amplitude (p-p) 20 log [ESBpp/ ECpp ]

EXPECTED GRAPHS

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RESULT

Thus, the balanced modulator is studied and observed the double sideband output with a
suppressed carrier signal.

DISCUSSION QUESTIONS

1. What is the balanced modulator

2. Give some application of balanced modulator
3. What is the working of Balanced Modulator?
4. Why SSB is not used for video broad casting.

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 EXPERIMENT – 3

FM GENERATION AND DETECTION

AIM
1. To generate frequency modulated signal and determine the modulation index and
Bandwidth for various values of amplitude and frequency of modulating signal.
2. To demodulate a Frequency Modulated signal using FM detector.

APPARATUS
 CRO-1 No.
 Trainer Kit
 Connecting wires

THEORY
The process, in which the frequency of the carrier is varied in accordance with the
instantaneous amplitude of the modulating signal, is called “Frequency Modulation”. The FM
signal is expressed as
S(t) = Ac Cos (2πfct + β Sin (2πfmt)

Where Ac is amplitude of the carrier signal, fc is the carrier frequency, β is the modulation index
of the FM wave.
The frequency-modulated waveform has the following characteristics:
 It is constant in amplitude but varies in frequency.
 The rate of carrier deviation is the same as the frequency of the modulating signal.
 The amount of carrier deviation is directly proportional to the amplitude of the modulating
signal.

MODULATION INDEX

In AM, the degree of modulation is measured as a percentage form 0% to 100% or as a

modulation factor from 0 to 1. In angle modulation, the degree of modulation is measured by the
modulation index. The equation for modulation index is:
β = ∆f / fm
fd or Δf = Frequency deviation; fm = Frequency of the message signal

While the modulation factor in AM is limited to a decimal between 0 and 1, the modulation
index in angle modulation can reach quite high numerical values. Another measure of angle
modulation is the deviation ratio. This is the ratio of the maximum deviation to the maximum audio
frequency; thus, it is a total system measurement rather than the instantaneous measurement
of modulation index.

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KIT DIAGRAM

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CIRCUIT DESCRIPTION

In this Trainer, frequency modulation is generated by using IC8038. The frequency of the
waveform generator is a direct function of DC Voltage given at pin 8 (measured from v+) altering
this voltage, frequency modulation is performed. For small deviations (e.g. + / - 10%). The
modulating signal can be applied directly to the pin 8, merely providing DC decoupling with a
capacitors. An external resistor between pin 7 & 8 is not necessary, but it can be used to increase
the input impedance from about 8K  (pin 7 & 8 connect together) to about (R + 8K). For larger
FM deviations or for frequency sweeping, the modulating signal is applied between the positive
supply voltage and pin 8. During the demodulation, FM output is given to a phase locked loop
(565 IC). We have seen that, during lock, the average dc level of the phase comparator output is
directly proportional to the frequency of the input signal. As the frequency shifts, it is this output
which causes the vw to shift and keep tracking in other, words, the phase comparator output is an
exact replica of the original modulating audio signal . The component values shown are for a
carrier frequency of 70 KHz approx. The demodulated output is followed by a three stage filter to
remove RF component. A small capacitor of 0.01F is connected between pins 7 & 8 to eliminate
possible oscillations in the current source.

EXPERIMENTAL PROCEDURE

1. Connect the AC adaptor to the mains and the other side to and the other side to experimental
trainer.
2. Observe carrier signal and the modulating signal on the dual trace CRO.
 Carrier signal: Modulator output without any modulating input. Carrier frequency
is 160KHz and amplitude is 4VP-P (Variable).
 Modulating signal: Frequency is 12.5 KHz. Amplitude is 5VP-P(Variable).
3. Connect modulating signal to the modulator, input and observe modulating signal and
FM output on the dual trace CRO. The following fig shows the procedure. The bandwidth
required for FM signal, as per carseni’s rule is Bandwidth B= 2(Δf + fm )
where Δf =frequency deviation fm = modulating frequency.
4. Trigger CRO w.r.t CH1. Adjust amplitude of the modulating signal until we get undistorted
FM output. It is difficult to trigger FM as analog CRO. That is why you adjust modulating
signal amplitude until small distortion notified in FM output.
5. Calculate maximum frequency & minimum frequency from the FM output and calculate
modulating index.
i) Now slowly increase the amplitude of modulating signal and measure fmin and
maximum frequency deviation Δf at each step.
ii) Evaluate the modulating index (mf = β) using Δf / fm where Δf = |fc - fmin|.
Calculate Bandwidth. BW = 2 (β + 1)fm = 2(Δf + fm)
6. Repeat step 5 by varying frequency of the modulating signal.

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Demodulation:
1. During demodulation, connect the circuit as shown below.
2. In this condition, decrease the amplitude of the modulating signal generator until we get
undistorted demodulated output.
3. Adjust the potentiometer in demodulation section until we get demodulated output.

OBSERVATION TABLE
fm = ______KHz ; fc =________KHz ; Ac =________V

Amplitude of fc + ∆f ∆f Modulation Bandwidth Amplitude of

Message Signal (V) index β =2(f+fm) Demodulated Signal (V)

Frequency of demodulated Signal: ______________.

EXPECTED GRAPHS

V Message Signal

Carrier Signal

FM Modulated Signal

Demodulated Signal

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RESULT

Thus, the FM modulated, demodulated waveforms were observed, and the frequency deviation
for different amplitudes of the input signal was calculated.

DISCUSSION QUESTIONS

1. Differentiate FM and AM.

2. How FM wave can be converted into PM wave?
3. How does ratio detector differ from Foster-Seeley discriminator?
4. What is meant by linear detector?
5. What are the drawbacks of slope detector?

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 EXPERIMENT – 4

SIGNAL SAMPLING AND ITS RECONSTRUCTION

(PULSE AMPLITUDE MODULATION)
AIM: To study the analog signal sampling i.e. generation of PAM signal and its re-construction.

APPARATUS

 DCL-001 Kit.
 20MHz CRO and Probes.
 Patch cards.

THEORY

SAMPLING PRINCIPLE: When an analog message is conveyed over an Analog

Communication System, the full message is typically used at all times. To send the same analog
signal over a Digital Communication System, only its samples requires to be transmitted at
periodic intervals. The receiver will receive only samples of the message. It must attempt to re -
construct the original message at all times from only its samples.

SAMPLING THEOREM FOR BAND LIMITED RANDOM SIGNALS: “A band limited

signal of finite energy, which has no frequency component higher than W Hz is completely
described by specifying the values of the signal at instants of time separated by 1/2W seconds”. It
can be recovered from knowledge of samples taken at the rate of 2W per second.

Let x(t) be a signal which is band-limited such that its highest frequency special component is f m.
Let the values of x(t) be determined at regular intervals separated by times T s<1/2fm, i.e. the signal
is periodically sampled every Ts second. Then these samples x(nTs) where n is an integer, uniquely
determine the signal and the signal may be re-constructed from these samples with no distortion.
Ts is the sampling time.

Fig.1: Basic Sampling Process

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Introduction to “DCL-001”: Kaushik’s “DCL-001” is an introductory trainer to enable the
students to understand the principles of SAMPLING AND RECONSTRUCTION. The single-
board “DCL-001” comes in a plastic enclosure with cover and easy to carry around in the Lab and
make measurements. The unit provides a 2 KHz sine wave, and a pulse waveform giving a choice
of 5 discrete sampling frequencies and 9 discrete pulse widths from 10% to 90% of the duty cycle
in steps of 10%.

Specifications of “DCL-001” Kit:

Signal:
Internal frequency : 2 KHz
Amplitude : 5V peak to peak.
External frequency : Band limited to 2 KHz
Amplitude : 5V peak to peak.

Sampling:
Internal frequency : 1 KHz, 8 KHz, 16 KHz, 32 KHz
Duty ratio : 10% - 90% in 10% steps (Switchable)
External ratio : Up to 40 KHz
Duty ratio : 10% - 90%
Amplitude : 5 volts

Supply : +5V, +12V DC Voltage

CIRCUIT DESCRIPTION:

The “DCL-001” is used to study the Signal Sampling and its Re-construction. It basically consists
of three Basic modules, namely, Sampling Control Logic, Sampling Circuitry, and Filter section.

SAMPLING CONTROL LOGIC:

This unit generates two main signals used in the study of Sampling Theorem. A 5V(p-p) 2 KHz
analog signal, i.e., the signal to be sampled and the sampling frequency signals, namely 1KHz, 4
KHz, 8 KHz, 16 KHz, 32KHz and each is 5V (p-p). The duty cycle of each sampling frequency
signal can be varied in discrete steps of 10% steps from 10 % to 90%, as indicated in the Table.1.
The selection of various sampling frequencies is made by means of the FR SEL switch. In the
power-ON condition, the highest frequency, i.e., 32 KHz is selected which is indicated by means
of a LED and thereafter by using the FR SEL switch, the sampling frequency can be selected in
the descending order, i.e., from 32 KHz to 1KHz.

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SAMPLING CIRCUITARY:

The unit has two parts, namely, signal sampling circuit and sample and hold circuit. And both these
operations are performed by means of an electronic switch and the associated circuitry.

Filter Section:
Two types of Filters are provided on board, viz., 2nd Order LPF and 4th order LPF. By connecting
the Sample & Hold output to 2nd Order and 4th Order LPF, the input signal is reconstructed at filter
output.

Block Schematics and Description:

Frequency Generation Logic:

The 6.4 MHz crystal oscillator generates the 6.4 MHz clock signal. The decade counter divides
the frequencies by 10 and the count generates the basic sampling frequencies 32 KHz to 1 KHz.

Sampling Frequency and Duty Cycle Selection Logic:

Sampling Frequency:
For each press on the FR SEL switch the output of the state counter increases by one and it counts
from 000 to 100. As the output of the 3 to 8 decoder resets the state and the whole cycle repeats
again. As the state counter counts from 000 to 100 the corresponding input of the MUX is switched
to the output also the corresponding decoder output is chosen, switching the LED ON. Refer the
truth table. 1 given below for better understanding.

State Counter O/P Selected I/P Selected Sampling Frequency

Q2 Q1 Q0
0 0 0 I0 32KHz
0 0 1 I1 16KHz
0 1 0 I2 8KHz
0 1 1 I3 4KHz
1 0 0 I4 1KHz
1 0 1 Resets 393 to I0 state

Table 1. Truth Table for Selection of Sampling Frequency.

Duty Cycle:

The BCD counter counts from 0000 to 1000. This is connected to the A inputs of the comparator.
The way DIP switch can be configured such that the input of the comparator varies from 0000 to
1000 and the frequency of the A<B output of the comparator is 10 times less than the frequency
of square wave, that is fed to the input if the BCD counter. Now the duty cycle of the A<B output
varies from 10% to 90% as the setting of the 4 way DIP switch varies from 0000 to 1000.

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2 KHz Sine Wave Generation Logic:

Refer figure 1.2. The serial to parallel shift register with the resistive ladder network and the output
generates the sine wave by the serial shift operations. The R-C filter suppresses the ripple at the
D/A output and smoothens the sine wave. The unity gain amplifier takes care of the impedance
matching.
Note: For 16 shifts of the shift register one sine wave is produced. So if a 32 KHz clock is fed to
the register 2 KHz sine wave is generated.

Sampling and Sample/Hold Logic:

The logic takes sine waves as analog inputs and samples the analog input at the rate equal to the
rate of sampling signal. The sample/hold capacitor, which holds the samples momentarily before
transmission.

Baseband Reconstruction Logics:

The reconstruction units are Butterworth low pass filter.

NATURAL SAMPLING:

Figure 2: Block Diagram of Natural sampling

The switch is closed for the duration of each pulse allowing the message signal at that sampling
time to become part of the output. The switch is open for the remainder of each sampling period
making the output zero. This type of sampling is called natural sampling.

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FLAT-TOP SAMPLING:

Figure 3: Block Diagram of Flat-top sampling

For flat-top sampling, a sample-and-hold circuit is used in conjunction with the chopper to hold
the amplitude of each pulse at a constant level during the sampling time, as shown in Figure .3.

COMPARISON OF TYPES OF SAMPLING

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EXPECTED GRAPHS

EXPERIMENTAL PROCEDURE

1. Connect the 2 KHz, 5V (p-p) signal generated onboard to the Analog Input, by means of
the patch cords provided.
2. Select the frequency of the sampling signal by means of FR SEL switch and connect it in
the internal mode by means of the shorting pin provided (refer fig. 1.9). Ensure that the
Duty Cycle of the sampling waveform is 50%.
3. Observe the corresponding Natural sampled signal at the output of ‘Sampling Amplifier’
using CRO and note the observed waveforms.
4. Using CRO, observe & note the 2nd/4th order LPF outputs by connecting the sampled output
to the input of the 2nd/4th order LPF and also determine the amplitude, frequency, and phase
distortions between the original analog I/P signal (generated on-board) and the
corresponding filtered O/P, if any.
5. Observe the corresponding sampled/hold signal at the output of ‘Sample/Hold amplifier’
using CRO and note.
6. Connect the S/H output to the input of the 2nd /4th order LPF. Using CRO, observe & note
the corresponding outputs and also determine the amplitude, frequency, and phase
distortions between the Analog I/P signal (generated on-board) and the corresponding
filtered O/P, if any.
7. Repeat the steps 3 – 6 by changing the frequency of the Sampling Signal.

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OBSERVATIONS

Analog Input Signal: Amplitude = __________; Frequency = __________;

Sampling Signal: Amplitude = ________; Frequency = _______; Duty Cycle = _______;

Sampled Outputs:
Natural Sampling: No. of Samples =
Flat-top Sampling: No. of Samples =

Filter Outputs (Reconstruction Outputs):

Natural Sampling:
2nd Order LPF Output: Amplitude = Frequency =
4th Order LPF Output: Amplitude = Frequency =
Flat-top Sampling:
2nd Order LPF Output: Amplitude = Frequency =
4th Order LPF Output: Amplitude = Frequency =

RESULT

From the above observation, we infer that for Signal Re-construction with no distortion, Nyquist
criterion has to be just satisfied and hence we prove the Sampling Theorem. If Nyquist Criteria is
not satisfied or if the signal is not band-limited, then spectral overlap, called “ALIASING” occurs,
causing higher frequency signal to show up at lower frequencies in the recovered signal.

PART-II
EFFECT OF VARYING THE SAMPLING FREQUENCY DUTY CYCLE

AIM

To study the effects of varying duty cycle of the sampling frequency on the amplitude of the re-
constructed signal.

APPARATUS

 DCL-001 Kit
 20MHz CRO and probes
 Patch cords

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EXERIMENTAL PROCEDURE

1. Connect the 2 KHz signal and the sampling frequency signal in internal mode, as in the
previous set-up.
2. By means of the Dip switch setting, as indicated in the DUTY CYCLE TABLE ( refer Table
1.1), vary the duty cycle of the sampling frequency signal from 50% to 80%, in steps of 10%
and repeat the steps 3 – 5 as in the previous set-up.
3. Change the frequency of the sampling signal and repeat the above steps.

OBSERVATIONS

It can be observed that as the duty cycle increases, practically the re-constructed signal remains
identical with any duty cycle.

RESULT

From the above observations, we infer that as long as NYQUIST CRITERIA is just satisfied duty
cycle has no importance.

DISCUSSION QUESTIONS

1. Why flat top sampling is better than natural sampling?

2. What is the significance of sampling?
3. What do you understand by sample and hold circuit?
4. What is the importance of doing sample and hold of signals?
5. Why sample and hold output is more reliable than natural sampled output signal?

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 EXPERIMENT - 5

PULSE WIDTH MODULATION AND DEMODULATION

AIM

To study the principle and operation of Pulse Width Modulation and Demodulation System.

APPARATUS

 ‘FUTURE TECH Pulse Width modulation & Demodulation Trainer Kit.

 Built in DC power supply: +/-5V/350mA.
 Set of Patch chords Stackable 4mm – 8 Nos.
 20 MHz CRO & probes.

THEORY

Pulse Width Modulation (PWM): Pulse width Modulation is an analog pulse modulation. In
Pulse Width Modulation, we have fixed Amplitude and starting time of each pulse, but the width
of each pulse is made proportional to the Amplitude of the Modulating Signal at that instant. Pulse
Time Modulation is also known as Pulse Width Modulation or Pulse Length Modulation. In PWM,
the samples of the message signal are used to vary the duration of the individual pulses. Width
may be varied by varying the time of occurrence of leading edge, the trailing edge or both edges
of the pulse in accordance with modulating wave. It is also called Pulse Duration Modulation.

In the FUTURE TECH Trainer Board, Pulse Width Modulation is generated by a Monostable
Multivibrator, using 555-IC connected in the Monostable mode as shown in the Panel layout
diagram. Initially, the Synchronous clock from the Synchronous clock generator is given to the
pin-2 of the 555-IC and the AF signal is given to the pin-5 of the same. If we observe the output
at pin-3, we see the Pulse Width Modulated signal. The width of each pulse is varied, in accordance
with instantaneous Amplitude of the AF signal.

Pulse Width Demodulation:

The Demodulation of the Pulse Width Modulation is a simple process. Pulse Width Modulated
signal is fed to an integrating (RC) circuit (Low pass Filter) from which the modulating signal is
recovered, whose Amplitude at any time is proportional to the Width of the Pulse. An Amplifier
circuit is used to amplify the recovered AF signal.

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KIT DIAGRAM

EXPERIMENTAL PROCEDURE

1. Connect the AC Adaptor to the mains and the other side to the Experimental Trainer.
2. Observe & note the Synchronous clock generator output and AF signal outputs using CRO.
3. Connect Synchronous clock generator output to the Synchronous clock input point of
PWM modulator and observe the same clock on one channel of a dual trace CRO.
4. Trigger the CRO with respect to CH 1
5. Observe & note the PWM output on CH 2. If we observe the PWM output, its width varies
according to the modulating voltage.
6. Vary the amplitude of AF signal & observe how the PWM signals are varying for AC
modulating voltages. In this case we have to trigger the CRO w.r.t modulating voltage.
7. During the demodulation, apply PWM signal to the input of demodulator and observe &
note its output.

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 8. Determine the amplitude, frequency, and phase distortions between the modulating signal
and the corresponding output of the Demodulator, if any (almost coincides with the but
having some phase difference due to RC networks and amplifiers, which are in the
demodulator).

OBSERVATIONS

Message Signal Frequency fm = _______

Carrier Signal Amplitude A c = _______
Carrier Signal Time period: TON = _______; TOFF = ________; T = TON + TOFF = ______

Amplitude of the PWM Output

Modulating Signal TON TOFF

Demodulated Signal:
Amplitude = _______
Frequency = _______

EXPECTED GRAPHS

a) Carrier Signal b) Modulating Signal c) PWM signal d) Demodulated signal

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RESULT

Observed and noted the waveforms of Pulse Width Modulation & Demodulation.

DISCUSSION QUESTIONS

1. What is the BW of PWM?

2. What are the methods to generate PWM?
3. What do you understand by pulse width modulation?
4. What is the effect of varying sampling frequency on pulse width modulation?

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 EXPERIMENT - 6

PULSE POSITION MODULATION AND DEMODULATION

AIM

a) To study the generation of PPM signal and its Demodulation.

b) To study the effect of Amplitude & Frequency of the modulating signal on its output.
c) To study the effect of the frequency of sampling signal on the output of Modulated- signal.

APPARATUS

1. ‘FUTURE TECH’ Pulse Position Modulation and Demodulation Trainer Kit

2. 20MHz Dual Trace Oscilloscope & probes.
3. Patch chords.

THEORY

Pulse Position Modulation is an analog communication. In Pulse Position Modulation, both the
pulse amplitude and pulse duration are held constant but the position of the pulse is varied in
proportional to the sampled values of the message signal. Pulse time modulation is a class of
signaling techniques that encodes the sample values of an analog signal on to the time axis of a
digital signal and it is analogous to angle modulation techniques. The two main types of PTM are
PWM and PPM. In PPM the analog sample value determines the position of a narrow pulse relative
to the clocking time. In PPM rise time of pulse decides the channel bandwidth. It has low noise
interference.

Hardware Description:
1. Saw tooth Generator : 2 KHz to 32 KHz.
2. Sampling Pulse Generator : 2KHz to 32 KHz
3. AF Signal Generator :20 Hz to 20 KHz in 3 ranges
4. Modulator with Sampling gate, Comparator & Monostable
5. Demodulator consisting of PPM to PWM Comparator and Low Pass Filter (3.4 KHz
cut off).
6. Built-in power supplies : +/_12V/350mA, +/- 5V/350 mA.

For generating a PPM signal (Figure 1) the modulating signal is first converted into the pulse width
modulation (PWM) signal by sending it through a PWM converter. The PWM signal is then fed
to a differentiator. At the output, positive and negative spikes are obtained. These spikes are passed
through a positive clipper which removes the positive spikes and gives negative spikes at the
output. The negative spikes are now made to trigger a Monostable multivibrator and finally the
PPM signal is obtained.

28 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

 Figure 1: Block diagram to generate PPM signal

Note that the pulse width duration modulation is a trailing edge modulation. This makes the leading
edge fixed, which is turn makes the positive part of the differentiated wave unchanged by the
modulating signal, and the positive part is therefore clipped. The negative part of the differentiated
wave contains original information in terms of relative position. The Monostable multivibrator
causes the pulse of equal duration to appear as the output. The position of the output pulse carries
the original information.

Figure Block diagram to generate PPM from PWM signal

KIT DRAGRAM

29 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

EXPECTED GRAPHS

t
Demodulated Signal

EXPERIMENTAL PROCEDURE

1. Connect the AC Adapter to the mains and the other side to the Experimental Trainer.
2. Observe & note the AF signal generator output. It is a sine wave of frequency varying from
20 Hz to 20 KHz with 0-5Vp-p Amplitude variation.

30 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

 3. Observe & note the output of the sampling Pulse generator. Its frequency is varying from
2 KHz to 30 KHz and the pulse width also variable.
4. Connect the output of the AF signal generator to the AF signal input of the PPM Modulator.
5. Sampling pulse is internally connected to the multiplexer; make sure that the frequencies
adjust pot in its maximum and the pulse width pot in its minimum positions.
6. The sample and hold output of the multiplexer at pin 6 of CA 3130 is given to one input of
the comparator.
7. The second input of the comparator is coming from 8038, which gives a saw tooth
waveform. So the output of the comparator is PWM output.
8. Observe & note the AF signal generator output on Channel 1 of a dual trace CRO.
9. Observe & note the PPM output on the second channel of the CRO by changing.
a) AF signal frequency
b) AF signal Amplitude
c) Frequency of the saw tooth wave
10. During demodulation, PPM output is given to PPM - PWM connected and also give
sampling pulse input from the modulator as a synchronizing clock from the transmitter.
11. Output of the low pass filter is the replica of the AF signal given to the PPM modulator.
12. Repeat the step-9, when observing the demodulated output also.

OBSERVATIONS

Frequency of the Message signal:

Amplitude of the Carrier signal:
Frequency of the Carrier signal:

S.No Amplitude of the Width of the Modulated Shift in Position of the Modulated
message signal (V) signal :TON (msec) signal :TON (msec)

Amplitude of the Demodulated signal:

Frequency of the Demodulated signal:

RESULT
a) Observed & noted the waveforms of PPM signal and its Demodulation.
b) Observed & noted the effect of Amplitude & Frequency of the modulating signal on its
output.
c) Observed & noted the effect of the frequency of sampling signal on the output of
Modulated- signal.
Thus, the PPM modulated & demodulated waveforms were observed and plotted the graph.

31 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

DISCUSSION QUESTIONS

1. What is the BW of PPM?

2. How to generate PPM?
3. What is the difference in applying DC input and Sine wave input?
4. Why low pass filters are required in demodulation process?
5. Why PPM is not generally used in digital communication system?

32 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

 EXPERIMENT - 7

DATA FORMATS / LINE CODING AND DECODING

AIM

To study the various data formats or line coding techniques.

APPARATUS

 DCL-005: Data conditioning & carrier modulation trainer kit

 Patch chords
 DC power supply
 CRO (20MHz)
 Probes

THEORY

In Digital Communications 1’s and 0’s can be represented in various formats in different levels
and waveforms. The selection of coding technique depends on system band width, system’s
ability to pass dc level information, error checking facility. We need to represent PCM binary
digits by electrical pulses in order to transmit them through a Base-band channel. The most
commonly used PCM popular Data formats are being realized here.

The digital data in PCM systems can be encoded in several formats:

NON-RETURN TO ZERO SIGNALS (NRZ)

They are called so because the signals do not return to zero with the clock. The following data
formats come under this category
a. Non- return to zero level(NRZ-L)
b. Non- return to zero mark(NRZ-M)

33 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

 a. Non- return to zero space(NRZ-M)

NON RETURN TO ZERO LEVEL CODING (NRZ - L)

The data format is very simple where all “ones” are represented by HIGHS &all zeros by LOWS.

NON- RETURN TO ZERO MARK CODING (NRZ - M)

In this format all ONES are marked by change in levels & all ZEROS by no transitions & the
transitions take place at the raising edge of the clock.

NON- RETURN TO ZERO SPACE CODING (NRZ - S)

This type of wave form is marked by change in levels for ZEROS and no transition for ONES &
the transitions take place at the raising edge of the clock.

RETURN TO ZERO CODING (RZ)

These signals are called return to zero signals since the return to ZERO with clock.
Unipolar return to zero coding:
One is represented by a half bit wide pulse and a zero is represented by the absence of the pulse.

BIPHASE SIGNALS
These phase encoded group consists of:
a. Bi-phase-level (popularly known as Manchester coding)
b. Bi-phase-mark
c. Bi-phase-space signals

These schemes are used in magnetic recording, optical communications & in satellite telemetry
links.

MANCHESTER CODING (BI-PHASE-L)

With the bi-phase-L, a ONE is represented by a half bit wide pulse positioned during the first half
of the bit interval & a ZERO is represented by a half bit wide pulse positioned during the second
half of the bit interval.

BI-PHASE - MARK CODING (BI-PHASE-M)

With the bi-phase-M, a transition occurs at the beginning of every bit interval. A ONE is
represented by a second transition, one half bit later.

BI-PHASE – SPACE CODING (BI-PHASE-S)

With a bi-phase-S, a transition occurs at the beginning of every bit interval.

MULTI LEVEL SIGNALS

They use 3 or more levels of voltages to represent the binary data.
Return to zero - alternate mark inversion coding (RZ-AMI):
ONES are represented by equal amplitude of alternating pulses, which alternate between +5v & -
5v.

34 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

KIT DIAGRAM

EXPERIMENTAL PROCEDURE

1. Set up the DCLT-005 in standalone mode and prepare a list of waveforms that are to be
observed in DCLT-005.
2. Connect the unit with the given power supply.
3. Connect s-clock to the Coding clock and observe the two signals.
4. Connect S-DATA to INPUT DATA and observe the two signals.
5. Connect one Channel-1 of the CRO to the S-DATA and Channel-2 to the CODED
DATA.
6. Observe CODED DATA with respect to Clock signal for various S-DATA inputs.

35 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

EXPECTED GRAPHS

OBSERVATIONS

1. Observe & note the various waveforms anticipated at the various test points provided.
2. Observe & note the NRZ-L data & the corresponding NRZ-M, NRZ-S, NRZ, Bi-phase-L,
Bi-phase-S, & AMI wave forms wing the two channels of the CRO.

RESULT

Various Data formats are studied and observed and the waveforms are plotted.

36 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

 EXPERIMENT - 8

PULSE CODE MODULATION AND DEMODULATION

AIM

To study 2-channel time division multiplexing and sampling of analog signal, and its Pulse code
modulation in None-parity mode in the transmitter section and to study the demultiplexing and
reconstruction of the analog signal in the receiver section.

APPARATUS

 DCL-03 &DCL-04 trainer kits

 Connecting chords
 Power supply
 20 MHz dual trace oscilloscope and probes

THEORY

In pulse code modulation (PCM) only certain discrete values are allowed for
the modulating signals. The modulating signal sampled, as in other forms of pulse
modulation. But any sample falling within a specified range of values is assigned a
discrete value. Each value is assigned a pattern of pulses and the signal transmitted by
means of this code. The electronic circuit that produces the coded pulse train from the
modulating waveform is termed a coder or encoder. A suitable decoder must be used
at the receiver in order to extract the original information from the transmitted pulse
train.
The sine wave of frequency 500 Hz & 1 KHz & DC signal DC1 & DC2 whose amplitude can
be varied accordingly are generated onboard on DCL-03 .These signals are fed to the input of
the sampling logic CH0 & CH1 &their samples are multiplexed by interleaving them properly
in their assigned time slots.
The crystal oscillator generates a clock of 6.4Mhz from which all the transmitter data & timing
signal s are derived .For fast mode operation the transmitter clock is240khz,& sampling clock
is 16khz .For slow mode operation, depending on jumper position the transmitter clock is 1.23
Hz or 0.6Hz& sampling clock is 0.088hz or 0.044hz i,e the sampling rate per channel is 11 or
22sec & serial data transmission rate is 813 ms or 1.6sec.

37 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

BLOCK DIAGRAM

EXPEIMENTAL PROCEDURE

Note: keep the switch faults in OFF position

1. Refer to the block diagram & carry out following connections.
 Connect power supply in proper polarity to the kit ‘DCL-03’ &’DCL-04’ & switch it on.
 Connect sine wave of frequency 500Hz & 1 KHz to the i/p CH0&CH1 of the sample &
hold logic.
 Connect OUT0 to CH0-IN & OUT1 to CH1-IN
2. Set the speed selection switch SW1 to FAST mode.
3. Select parity selection switch to NONE mode on both the kits ‘DCL-03’ &’DCL-04’ as shown
in switch setting diagram .
4. Connect TXDATA, TXCLK & TXSYNC of the transmitter section DCL-03 to the
corresponding RXDATA, RXCLK & RXSYNC of the receiver section DCL-04.
5. Connect post DACOUT to IN post of the de-multiplexer section on DCL-04
6. Ensure that fault switch SF1 as shown in switch setting diagram introduces no faults
7. Take the observations as mentioned below.
8. Repeat the above procedure with DC signal at the inputs of the channel CHO & CH1.
9. Connect ground points of both the kits with the help.

OBSERVATIONS

Observe the following signal on oscilloscope & plot it on the graph paper.
ON KIT ‘DCL-03’
1. Input signal CH0 & CH1

38 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

2. Sample & Hold O/P OUT0 & OUT1.
3. Multiplexed clock CLK1 &CLK2
4. Multiplexed data MUXOUT
5. PCM data TXDATA, TXCLK, TXSYNC

SWITCH FAULTS
Keep the connection as per the procedure. Now switch corresponding fault switch button in ON
condition & observe the different effects on the o/p. The faults are normally use done at a time.
1. Put switch 0 of SF2 (DCL-03) in switch fault section to ON position
2. Put switch 3 of SF2 (DCL-03) in switch fault section to ON position
3. Put switch 4 of SF2 (DCL-03) in switch fault section to ON position

EXPECTED GRAPHS

39 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

RESULT
Thus pulse code modulation and demodulation is studied.

EXPERIMENT - 8 (b)

PRINCIPLE OF A/D CONVERTER AND D/A CONVERTER

AIM
To study principle of analog to digital and digital to analog conversion

APPARATUS
 DCL-03 &DCL-04 trainer kits
 Connecting chords
 Power supply
 20 MHz dual trace oscilloscope and probes

THEORY

The analog to digital converter converts the analog samples to digital bits. The analog to digital
converter (A/D) IC AD673 forms the heart of this logic this device performs both the quantizing
& encoding operations. The level of the i/p signal can be varied from 0V to 5V. Then the level is
divided into 128 uniform steps corresponds to 4.96 V /128 = 40mv.
The quantizing level is considered to be midway of the steps. If the signal level falls below the
quantizing level, then the signal is rounded off to the lower level. If the signal level falls above the
quantizing level, then the signal is rounded off to the upper level. This type of quantizing is called
“uniform quantizing’.

40 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

 BLOCK DIAGRAM

DC1

ᶲ Out 0 Ch0IN
P1 Sample
& M Fault
U A/D Error code
Ch
hold generator switching
Converter
P2
ᶲ 0 X
Logic
Out 1 Ch1IN
Function DC2
Generator
Parallel to
serial converter

TXCLK

Function TXDATA
Transmitter PRBS Transmitter
Generator
timing logic generator output logic
TXSYNC
FAST SLOW
RXCLK

Receiver
timing logic
RXSYNC

Error
D/A detection & Data Serial to
DAC OUT converter parallel
correction latch
converter RXDATA
logic

EXPERIMENTAL PROCEDURE

Note: keep the switch faults in OFF position

1. Refer to the block diagram & carry out following connections.
 Connect power supply in proper polarity to the kit ‘DCL-03’ &’DCL-04’ & switch on.
 Connect DC input signal DC1 to the i/p CH0 & CH1 of the sample & hold logic
 Connect OUT0 to CH0-IN & OUT1 to CH1-IN
2. Set the speed selection switch SW1 to FAST mode.
3. Select parity selection switch to NONE mode on both the kits ‘DCL-03’ &’DCL-04’ as shown
in switch setting diagram .
4. Connect TXDATA, TXCLK & TXSYNC of the transmitter section DCL-03 to the
corresponding RXDATA, RXCLK & RXSYNC of the receiver section DCL-04.
5. Ensure that fault switch SF1 as shown in switch setting diagram introduces no faults.
6. Vary the amplitude of i/p DC signal from 0V to 4.96V.
7. Take the observations as mentioned below.
8. Repeat the experiment in the slow mode.

41 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

 PCM Operation (with DC input):
Theoretical value can be obtained by:
A/D input voltage
________________ = X(10) = Y(2)
1 LSB value
Where 1 LSB value = Vref / 2 n

Since Vref = 5V and n= 8

1 LSB Value = 0.01953
Example:
A/D input voltage = 1 V = 51.2(10) = 00110011(2)
So digital output is 00110011

OBSERVATIONS

Observe the following signal for each setting of i/p DC signal & tabulate at least ten reading in
your record book.
ON KIT ‘DCL-03’
1. I/P signal to ADC (on CRO or digital multimeter) MUXOUT
2. ADC O/P (on LED’S) B1 to B7
Note: Always a single bit error (LSB) is common in the analog to digital conversion applications.

EXPECTED WAVEFORM

1111111
1111110

Output code

0000100
0000011
0000010
0000001
0000000

FIG:1 (b) Waveform for A/D converted o/p code v/s input voltage for DCL-003

RESULT
Analog to digital and digital to analog converters are studied.

42 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

 EXPERIMENT - 9

LINEAR DELTA MODULATION AND DEMODULATION

AIM
To study delta modulation and demodulation and to observe the step size and errors in it

APPARATUS
 DCL-07 EXPERIMENTAL kit(Falcon make)
 Connecting cords
 Power supply
 20MHz dual trace oscilloscope

THEORY
Delta modulation
Delta modulation is the differential pulse code modulation scheme in which the difference signal
is encoded into a single bit. With Delta Modulation (DM) a train of fixed width pulses is
transmitted, whose polarity indicates whether the demodulator output should rise or fall at each
pulse. The output is caused to rise or fall by a fixed step height at each pulse. A block diagram of
DM system is given in Figure. At the receiver the digital signal is decoded and filtered to get the
reconstructed analog signal. Sufficient number of samples are required to allow the analog signal
to be reconstructed accurately. Delta modulation is a process of converting analog signal one bit
indicates whether the signal is larger or smaller than the previous samples.

The modulating message signal (𝑡) is applied to the comparator. The input analog signal
m(𝑡) is compared with the loop estimated signal 𝒎̃(𝒕) to generate the error signal e(𝑡). Then,
this error signal is fed into a two level quantizer. The quantized error signal is
multiplied by the sampling function pulse generator to generate the output 𝒙𝑫𝑴(𝒕). The
signal 𝒙𝑫𝑴(𝒕) is integrated to generate the loop estimate 𝒎̃(𝒕). In this implementation,
the sampling function is a train of narrow pulses with unit amplitude (most practical
implementations also). The multiplier becomes a switch and the sampling function
becomes the switch enable input. The output (𝑡) is a sequence of pulses with amplitude
+∆ or −∆. It is very important to note that the DM process samples the quantized error
function and not the input signal itself and for narrow sampling pulses the estimated
43 | CBIT, DEPT. OF ECE, ADC LAB MANUAL
Delta demodulation
The delta demodulator consist of a D filp flop, followed by an integrator and second & fourth order
low pass Butterworth filter. The delta modulator receives the data stream form D-flip flop of delta
modulator. It indicates this data at every rising edge of the receiver clock.

BLOCK DIAGRAM

Data input
FF Data input
Voltage
comparator clk
Digital sampler

Integrator-1

Figure a & b: Delta Modulator and Demodulator

KIT DIAGRAM

44 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

EXPERIMENTAL PROCEDURE

Note: Keep all the switches to faults (switch SF1 & SF2) in OFF position
1. Refer to the block diagram and connect power supply to bit & switch it ON.
2. Select sine wave input 20Hz of 0v to connect to post IN of buffer whose OUT is connected
to digital sampler input.
3. Select clock rate of 8KHz by pressing Si which is indicated by LED LOW & keep
SWITCH S2 in delta position
4. Connect o/p of digital sampler to IN of integrator whose OUT is connected to IN2 of
digital sampler .then observe delta modulated o/p & compare clock rate selected
5. It can be observed that as the clock rate is increased amplitude of triangular waveform
decreases. This is called minimum step size
6. Increase the amplitude of 250Hz sine wave through pot P1 further high & observe that the
integrator o/p cannot follow the i/p signal.
7. Connect delta modulator OUT of digital sampler to i/p of delta demodulator.
8. Connect o/p of integrator 3 post OUT to the i/p of o/p buffer post IN
9. CONNECT o/p of second order filter post OUT to the i/p of fourth order filter post IN.
10. Keep the switch S4 in HIGH position
11. Then observe signal reconstructed through second order filter and fourth order filter
12. Refer to Block Diagram (Figure 3.1) & Carry out the following connections.
Connect the power supply with the proper polarity to the Kit DCL-07 and switch it ON.
13. Keep the switch faults in OFF position.
14. Select sine wave input 250Hz of 0V through pot P1 and connects post 250Hz to post IN of
input buffer.
15. Connect output of buffer post OUT to Digital Sampler input post IN1.
16. Then select clock rate of 8 KHz by pressing switch S1 selected clock is indicated by LED
glow.
17. Keep Switch S2 in Delta position.
18. Connect output of Digital Sampler post OUT to input post IN of Integrator 1.
19. Connect output of Integrator 1 post OUT to input post IN2 of Digital Sampler.
20. Observe the Delta modulated output at output of Digital Sampler post OUT and compare
it with the clock rate selected. It is half the frequency of clock rate selected.
21. Observe the integrator output test point. It can be observe that as the clock rate is increased
amplitude of triangular waveform decreases. This is called minimum step size.
22. Increase the amplitude of 250Hz sine wave up to 0.5V. Signal approximating 250Hz is
available at the integrator output. This signal is obtained by integrating the digital output
resulting from Delta modulation.
23. Go on increasing the amplitude of selected signal through the respective pot from 0 to 2V.
It can be observed that the digital high makes the integrator output to go upward and digital
low makes the integrator output to go downwards. Observe that the integrator output follow
the input signal.

45 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

 24. Increase the amplitude of 250Hz sine wave through pot P1 further high and observe that
the integrator output cannot follow the input signal. State the reason.
25. Select the clock rate of 32 KHz using switch S1. Repeat the above mention procedures
with different signal sources and selecting the different clock rates and observe the
response of Delta Modulator.
26. Connect Delta modulated output post OUT of Digital Sampler to the input of Delta
Demodulator section post IN of Demodulator.
27. Connect output of Demodulator post OUT to the input of Integrator 3 post IN
Keep Switch S4 in high position.
28. Connect output of Integrator 3 post OUT to the input of output buffer post IN.
29. Connect output of output buffer post OUT to the input of 2nd order filter post IN.
30. Connect output of 2nd order filter post OUT to the input of 4th order filter post IN.

EXPECTED GRAPHS

46 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

 Modulating signal i/p

t in ms

clock i/p
Am
plit
ude(
V)
t in ms

Digital sampler o/p

t in ms
Integrator o/p

t in ms

4th order filtered o/p

t in ms
2nd order filtered o/p

t in ms

OBSEVATIONS
Observe the following signal on oscilloscope & ploy it on the paper
1. Input signal
2. Sampling clock
3. Digital sampler output

47 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

 4. Integrator 1 output at feedback loop for delta modulator
Demodulator output
5. Integrator 3 output
6. Filter outputs

RESULTS
Thus the delta modulation & demodulation process have been performed and calculated the step
size from the obtained output.

DISCUSSION QUESTIONS

1. What are the advantages of Delta modulator?

2. What are the disadvantages of delta modulator?
3. How to overcome slope overload distortion?
4. How to overcome Granular or ideal noise?
5. What are the differences between PCM & DM?
6. Define about slope over load distortion?

48 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

 EXPERIMENT - 10

ADAPTIVE DELTA MODULATION AND DEMODULATION

AIM
To study adaptive delta modulation & demodulation & to observe the adaptive changes in the
step size.

APPARATUS
 DCL-07 experiment kit
 Connecting cords
 Power supply
 Dual trace oscilloscope(20MHz)

THEORY
As Delta modulation system is unable to chase the rapidly changing information of the analog
signal, which gives rise to distortion & poor quality reception. The problem can be overcome by
increasing the integrator gain. Adaptive delta modulation is a variation of delta modulation, which
offers relief from disadvantage of DM by adopting the step size to accommodate changing signal
condition. If the i/p signal is large, step is caused to increase, thereby reducing the slope overload
effects. The block diagram of ADM is shown in figure. It is same as that of DM except the variable
gain circuit & the step size controller. The controller keeps sensing the slope condition of the
message conveyed. If the slope is small, the controller o/p causes a small gain.

BLOCKDIAGRAM

Data input
FF Data input
Voltage
comparator clk
Digital sampler
ᶴ

Integrator-2

49 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

KIT DIAGRAM

EXPERIMENTAL PROCEDURE

Note: keep all the switches to faults (switch SF1 & SF2) in OFF position
1. Refer to the block diagram and connect power supply to bit & switch it ON.
2. Connect the power supply with the proper polarity to the kit DCL-07 & switch it on.
3. Select sine wave input 500Hz of 0v above through pot P1 & connect post 1KHz to post
IN of digital buffer
4. Connect o/p of buffer post OUT to digital sampler i/p post IN1.
5. Then select clock rate of 32KHz by pressing switch S1, selected clock in indicated by LED
glow
6. Keep switch S2 in D (delta) position.
7. Connect o/p of digital sampler post OUT to i/p post IN of integrator 2.
8. Connect o/p of integrator 2 post OUT to i/p IN2 of digital sampler.
9. Keep switch S3 in low position.
10. Connect delta modulated o/p post OUT of digital sampler to the i/p of delta demodulator
section post IN of demodulator.
11. Connect o/p of demodulator post OUT to the i/p of integrator 3 post IN
12. Connect o/p of integrator 3 post OUT to the i/p of o/p buffer post IN.
13. Connect o/p of o/p buffer post OUT to the i/p second order filter post IN
14. Connect o/p of second order filter post OUT to the i/p of fourth order filter post IN
15. Keep switch S4 in low position.
16. Observer the o/p of filter at post OUT of 4th order filter

50 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

 17. Repeat the above mention procedures with different signal sources & selecting the
different clock rates & observe the response of adaptive delta modulation, which follows
i/p signal even if amplitude & frequency of i/p signal increases adaptive delta modulator
matches the slope of the i/p signal sue to low time constant
18. We will get better recovery of signal as we go on increasing the clock rate.

Refer to the block diagram(Figure 3.2) and carry out the following connections.
 Connect the power supply with the proper polarity to the Kit DCL-07 and switch it ON.
 Keep the switch faults in OFF position.
 Select sine wave input 500Hz of 2V or above through pot P2 and connect post 500Hz to post
IN of input buffer.
 Connect output of buffer post OUT to Digital Sampler input post IN1.
 Then select clock rate of 32 KHz by pressing switch S1 selected clock is indicated by LED
glow.
 Keep Switch S2 in Delta position.
 Connect output of Digital Sampler post OUT to input post IN of Integrator 2.
 Connect output of Integrator 2 post OUT to input post IN2 of Digital Sampler.
Keep Switch S3 in LOW position.
 Connect Delta modulated output post OUT of Digital Sampler to the input of Delta
Demodulator section post IN of Demodulator.
 Connect output of Demodulator post OUT to the input of Integrator 3 post IN.
 Keep Switch S4 in LOW position.
 Connect output of Integrator 3 post OUT to the input of output buffer post IN.
 Connect output of output buffer post OUT to the input of 2nd order filter post IN.
 Connect output of 2nd order filter post OUT to the input of 4th order filter post IN.
 Select 1 KHz of 2V pp. signal as input.
 Observe output at digital sampler output post
 Observe output at integrator 3 output post
 Observe the output at filter output post

51 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

EXPECTED GRAPHS

Message signal
t(ms)

Clock signal

t(ms)
Digital sampler o/p

t(ms)
Amplitude(V)

Integrator o/p

t(ms)

2nd order filter output

t(ms)

4th order filter output

t(ms)

OBSERVATIONS
Observe the following signal on oscilloscope & plot it on the paper
1. Input signal
2. Sampling clock
3. Digital sampler output
4. Integrator 1 output at feedback loop for delta modulator

52 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

 Demodulator output
5. Integrator 3 output
6. Filter outputs

RESULT

Thus, the output of the ADM is obtained & observed the change in the step size in accordance with
the change in the input amplitude. The analog data is reconstructed using adaptive delta
demodulator.

53 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

 EXPERIMENT – 11

AMPLITUDE SHIFT KEYING GENERATION & DETECTION

AIM
 To generate amplitude shift keyed (ASK) output using modulator using both analog and
discrete carriers.
 To reconstruct the data signal from the ASK output using demodulator.

APPARATUS
 ASK modulation kit
 Built-in DC power supply (+/-18V /350mA & +5v/350mA)
 CRO
 Patch cords

THEORY

The binary ASK system was one of the earliest form of digital modulation used in wireless
telegraphy. In an binary ASK system binary symbol 1 is represented by transmitting a
sinusoidal carrier wave of fixed amplitude Ac and fixed frequency fc for the bit duration
Tb whereas binary symbol 0 is represented by switching of the carrier for T b seconds.
This signal can be generated simply by turning the carrier of a sinusoidal oscillator ON
and OFF for the prescribed periods indicated by the modulating pulse train. For this
reason the scheme is also known as on-off shift testing.
In this modulation technique binary ‘1’ is represented by presence of the carrier and
binary ‘0’ by the absence of the carrier signals. The block diagram of ASK transmitter can
be represented as shown in the diagram.

Amplitude Shift Keying (ASK) is a digital modulation scheme where the binary data is transmitted
using a carrier signal with two different amplitude levels. For binary 0 and 1, the carrier switches
between these two levels. In its simplest form, a carrier is sent during one input and no carrier is
sent during the other. This kind of modulation scheme is called on-off keying. A simple ASK
modulator circuit is shown in figure. Here a sinusoidal high frequency carrier signal is sent for
logic ‘0’ (-5V) and no carrier is sent for logic ‘1’ (+5V). The transistor works as a switch closes

54 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

when the input (base) voltage is +5V (logic ‘1’) and shorts the output. When the input voltage is -
5V (logic ‘0’), the switch opens and the carrier signal is directly connected to the output.

KIT DIAGRAM

EXPERIMENTAL PROCEDURE

a) ASK modulation
1. Connect the AC adapter to the mains & the other side to the experimental trainer.
2. Observe the bit clock frequency on the oscilloscope. Adjust the frequency to 10KHz &
connect it to pin of IC74165.
3. Set the SPDT switches patter to the desired code.
4. Parallel load by changing the switch to opposite side for a short duration & get back to shift
position.
5. Observe the 8bit word pattern at the o/p of the 8-bit word generator. This is the modulating
signal.
6. Adjust the carrier frequency of 100 KHz& 5 Vpp. Give this i/p to ASK modulator i/p using
patch cords.
7. Connect 8-bit word generator o/p to the data i/p of the ASK modulator.
8. Change 8-bit word sequence with help of SPDT switches & load & check the o/p of ASK,
modulator wrt data signal.
9. During demodulation, connect the o/p of ASK modulator to demodulator & adjust
potentiometer P1 to get data same as modulating signal which is original signal.

55 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

 b) ASK demodulation
1. Sync o/p signal is provided to synchronize data at ASK o/p.
2. For this operation connect sync o/p to i/p of binary counter, o/p’s Q 0,Q1,Q2,Q3 are the data
i/p’s to the ASK modulator
3. By changing the carrier, the carrier frequency &bit clock frequency observe the ASK o/p
& demodulated o/p.

EXPECTED GRAPHS

CASE 1: ASK WITH ANALOG CARRIER

Data Input

Analog Carrier Input

ASK Output (OOSK)

ASK Output
(Min amp for bit ‘0’)

Demodulated
Output

56 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

 CASE 2: ASK WITH DISCRETE CARRIER

Amp Data input

Demodulated Output

RESULT

Thus the generation & detection of ASK has been performed for a given data bit pattern

57 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

 EXPERIMENT – 12

FREQUENCY SHIFT KEYING GENERATION AND DETECTION

AIM
 To generate frequency shift keyed (FSK) output using modulator.
 To reconstruct the data signal from the FSK output using demodulator.

APPARATUS
 Panel layout diagram with components mounted on PCB/panel
 Built-in DC power supply +/-12V /350mA & +5v/350mA
 Set of patch chords & user manual
 20MHz CRO & probes

THEORY

FSK signaling schemes find a wide range of applications in low -speed digital data
transmission system. FSK schemes are not as efficient as PSK in terms of power and
bandwidth utilization. In binary FSK signaling the waveforms are used to convey binary
digits 0 and 1 respectively. The binary FSK waveform is a continuous, phase constant
envelope FM waveform. FSK is a system of frequency modulation in it the un-modulated carrier
frequency corresponds to the mask condition, & a space is represented by a downward frequency
shift.

KIT DIAGRAM:

58 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

HARDWARE DESCRIPTION

HF CLOCK SOURCE: The Bit Clock source is designed around the popular timer IC 555
operated in Astable mode. The 1MΩ Potentiometer in conjunction with 0.0047 µF condenser used
as the timing circuit facilitates the frequency to be set & at any chosen value from 100 Hz to 100
kHz.

DATA CLOCK GENERATOR. A 74163 IC which is a Divide by 16 counter is provided to

generate different data frequencies of f/2, f/4, f/8 & f/16 of the input clock frequency to this
counter. The output frequencies are used as clock inputs to the 8 Bit word generator.

EXPERIMENTAL PROCEDURE

1. Connect the AC adapter to the mains & the other side to the experimental trainer.
2. Apply one binary sequence as input message to the FSK
modulator. This sequence is taken from decade counter outputs. (7490IC)
3. Observe the frequency changes according to the data i/p & note down the frequencies from
the modulated o/p on the second channel of the CRO.
To perform demodulation,
4. Give the modulated FSK signal to the demodulator input. Observe the output
of the demodulator on the CRO along with the original data sequence. Adjust
the tuning controls (of filter and comparator) so that input and demodulated
outputs are the same. Do not touch the tuning controls after the adjustment is
done.
5. Adjust the potentiometers P1 & P2 until we get the demodulated o/p equivalent to the
modulating data signal. Observe & note the same.
6. Compare the modulating data signal & the demodulated o/p & observe amplitude,
frequency & phase distortions if any.

OBSERVATIONS

Digital data input: Amplitude = ________; Bit duration Tb = ________

Carrier input:
Low frequency signal: Amplitude = ________; frequency = ______
High frequency signal: Amplitude = ________; frequency = ______
FSK Output:
Amplitude = ________
Frequency observed for bit ‘0’ = ________
Frequency observed for bit ‘0’ = ________
Demodulated Output: Amplitude = ________; Bit duration Tb = ________

59 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

EXPECTED GRAPHS

Demodulated Output

RESULT

Generation and detection of frequency shift keying has been performed. Observed the two different
frequencies for mark and space of the given data sequence.

60 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

 EXPERIMENT - 13

BINARY PHASE SHIFT KEYING GENERATION AND DETECTION

AIM
1. To generate the binary phase shift keying output.
2. To detect the message signal from the PSK output using the demodulator.

APPARATUS
 PSK modulator &demodulator kits
 Built-In DC power supply
 Patch chords
 CRO probes

THEORY

Phase Shift Keying is a digital modulation Technique. Phase Shifting Keying (PSK) is a
modulating / Data transmitting technique in which phase of the carrier signal is shifted between
two distinct levels. A cosinusoidal carrier of a fixed amplitude and frequency is taken. The
digital data of 1’s and 0’s is converted to S1(t)=AcCos(2πfct) (i.e. for bit ‘1’),
S0(t)=AcCos(2πfct+π) (i.e. for bit ‘0’) respectively. Binary Phase Shift Key modulation, binary ‘1’
is represented by actual carrier and binary ‘0’ is represented by 1800 phase shifted carrier signal.
The block diagram of BPSK transmitter can be represented as shown in the figure.

In binary phase shift keying the phase of the modulator is shifted by +180 degrees for mask and
by -180 degrees for space. Here the carrier wave of 28 KHz & 5Vp-p sine wave is generated by a
Wein Bridge oscillator using the IC741. This sine wave is converted to square wave signal by
TL084 in comparator mode. The BC107 converts the square wave to the TTL level. This is then
used as clock i/p to the decade counter (7490IC) which generated the modulating data outputs
modulating data input is applied to the control input. The 180 degrees phase shift to the carrier
wave created by an op-amp (IC741).
During the demodulation the PSK signal is converted to the +5Vp-p square wave using a transistor
& is applied to tone i/p of an EX-OR gate. To the second i/p of the gate carrier signal is applied
after conversion into a +5Vp-p signal. So the EX-OR gate o/p is equivalent modulating data signal.

61 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

KIT DIAGRAM

EXPERIMENTAL PROCEDURE

1. Apply the carrier signal to the i/p of the modulator. Observe & note this signal using CRO.
2. Apply the modulating data signal to modulator i/p. Observe & note this signal using CRO.
3. Observe & note the o/p of PSK modulator using the CRO.
4. Apply the PSK o/p to demodulator i/p & also apply the carrier signal to the demodulator
i/p.
5. Observe the demodulator o/p & compare it with the modulating data i/p signal applied to
the modulator i/p.
6. Using the CRO observe & note the amplitude, phase & frequency distortions between the
demodulated o/p & modulating data.

62 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

OBSERVATIONS

Digital data input: Amplitude = ________; Bit duration Tb = ________

Carrier input: Amplitude = ________; frequency = ______
BPSK Output:
Amplitude = ________
Phase observed for bit ‘0’ = ________
Phase observed for bit ‘0’ = ________
Demodulated Output: Amplitude = ________; Bit duration Tb = ________

EXPECTED GRAPHS
Data i/p signal

t(ms)
Bit Clock

t(ms)
Carrier signal
Amplitude (V)

t(ms)

BPSK Output

t(ms)

Demodulated siganl

t(ms)

RESULT

Thus, the generation & detection BPSK signal is performed by using binary data signal.

63 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

 EXPERIMENT - 14

QPSK GENERATION AND DETECTION

AIM
3. To generate the binary phase shift keying output.
4. To detect the message signal from the PSK output using the demodulator.

APPARATUS
 QPSK trainer kit
 Built-In DC power supply
 Patch chords
 CRO probes

THEORY

QPSK Modulation:

Quadrature Phase Shift Keying (QPSK) is a form of Phase Shift Keying in which two bits
are modulated at once, selecting one of four possible carrier phase shifts (0, 90, 180, or
270 degrees). QPSK perform by changing the phase of the In-phase (I) carrier from 0° to 180° and
the Quadrature-phase (Q) carrier between 90° and 270°. This is used to indicate the four states of
a 2-bit binary code. Each state of these carriers is referred to as a Symbol.
QPSK allows the signal to carry twice as much information as ordinary PSK
using the same bandwidth. The Quadrature Phase Shift Keying (QPSK) is a
variation of BPSK, which sends two bits of digital information at a time, called as digits.
Instead of the conversion of digital bits into a series of digital stream, it converts them
into bit pairs. This decreases the data bit rate to half, which allows space for the other
users. In QPSK, the phase of the carrier depends upon the pair of successive bits in the data stream.
This there are four possible combinations of bit pair viz 00, 01, 10 & 11. During each
combination of bit pair, the carrier frequency fc is transmitted with Quadrature phase difference.

Bit Pair Phase of Carrier

00 fc ∠00

01 fc ∠180 0

10 fc ∠90 0

11 fc ∠270 0

64 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

BLOCK DIAGRAM

Figure: QPSK Transmitter Block Diagram

KIT DIAGRAM

QPSK MODULATOR

65 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

QPSK DEMODULATOR

EXPERIMENTAL PROCEDURE

QPSK Modulation:
1. Connect the QPSK modulator to AC source and switch on the trainer.
2. Check the phase difference of the Quadrature phase carrier generated at the outputs of FF1
and FF2.
3. Connect the output at TP1 to Ch1 of oscilloscope and synchronize the scope with Ch1 and
positive slope trigger.
4. Observe on Ch2 the phase shifted carriers at TP2, TP3 and TP4 w.r.t the carrier and TP1
and fill up the table.

Signal Phase angle with respect

at pin to carrier at TP1
TP1 ∠00
TP2 ∠1800
TP3 ∠900

TP4 ∠2700

5. Test the odd even bit separator for static bit levels. The logic levels at sockets S 2 and
S3 will determine the odd bit and even bit stream.

66 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

 S3 S2 OUTPUTS
00 01 10 11
Gnd Gnd H L L L
Open Gnd L L H L
Gnd Open L H L L
Open Open L L L H

6. Test the selection of carrier w.r.t the bit pattern generation. Observe on Channel-1 carrier fc
<1800 at TP1. Connect on Channel-2, the output of QPSK modulator. Observe the switched
carrier as:
Socket S2 Socket S3 Phase angle of QPSK output wrt 1800 carrier
Gnd (0) Gnd (0) 00
Open (1) Gnd (0) 900
Gnd (0) Open (1) 1800
Open (1) Open (1) 2700

EXPECTED GRAPHS

67 | CBIT, DEPT. OF ECE, ADC LAB MANUAL

RESULT

Thus QPSK modulation and demodulation is performed practically and observed the 4 phase
angles with respect to the data sequence and the graphs are plotted.

68 | CBIT, DEPT. OF ECE, ADC LAB MANUAL