Inverter Tranasmission gate

module inverter(b, a); module trans(b, a, cntrl1, cntrl2);

input a; input a;
output b; input cntrl1,cntrl2;
assign b = ~a; output b;
endmodule reg b;
tb always @ (a or cntrl1 or cntrl2)
module inv_tb; begin
wire b; if (cntrl1 = = cntrl2)
reg a; b = 1’bx;
inverter i1(b,a); else if (cntrl1 = = 0 & cntrl2 = = 1)
initial b = a;
begin else
a=1’b0; b = 1'bz;
#10 a=1’b1; end
#10 a=1’b x; endmodule
#10 a= 1’bz; tb
end module trans_tb;
endmodule wire b ;
reg a ;
buffer reg cntrl1,cntrl2;
module buffer(b,a,en); trans t1(b, a, cntrl1, cntrl2);
input a,en; initial
output b; begin
reg b; a= 1'b0 ; cntrl1 = 1'b0 ; cntrl2 = 1'b0 ;
always@(a or en) #10 a= 1'b0 ; cntrl1 = 1'b0 ; cntrl2 = 1'b1;
begin #10 a= 1'b0 ; cntrl1 = 1'b1 ; cntrl2 = 1'b0;
if (en==1) #10 a= 1'b0 ; cntrl1 = 1'b1 ; cntrl2 = 1'b1;
b=a; #10 a= 1'b1 ; cntrl1 = 1'b0 ; cntrl2 = 1'b0;
else #10 a= 1'b1 ; cntrl1 = 1'b0 ; cntrl2 = 1'b1;
b=1’bz; #10 a= 1'b1 ; cntrl1 = 1'b1 ; cntrl2 = 1'b0;
end #10 a= 1'b1; cntrl1 = 1'b1 ; cntrl2 = 1'b1;
endmodule end
tb endmodule
module buffertest;
reg a,en;
wire b;
buffer b1(b,a,en);
initial
begin
en=1’b1;
a=1'b0;
#10 a=1'b1;
#10 a=1'b0;
#10 a=1'bx;
#10 a=1'bz;
#10 a=1'b0;
end
endmodule
Logic gate SR Flipflop
module logic(f1,f2,f3,f4,f5,f6,a,b); module srff(q,qb,s,r,clk,rst);
input a,b; input s,r,clk,rst;
output f1,f2,f3,f4,f5,f6; output q,qb;
assign f1=a&b; reg [1:0] sr;
assign f2=a|b; reg q,qb;
assign f3=~a; always @(posedge clk)
assign f4=~(a|b); begin
assign f5=~(a&b); if (rst ==1)
assign f6=a^b; q=1’b0;
endmodule else
//Test bench sr={s,r};
module logictest; case(sr)
reg a,b; 2'b00:q=q;
wire f1,f2,f3,f4,f5,f6; 2'b01:q=1'b0;
logic g1(f1,f2,f3,f4,f5,f6,a,b); 2'b10:q=1'b1;
initial 2'b11:q=1'bx;
begin endcase
a=1'b0; qb=~q;
b=1'b0; end
#10 b=1'b1; endmodule
#10 a=1'b1; //Test bench
b=1'b0; module srfftest;
#10 b=1'b1; reg s,r,clk,rst;
#10; wire q,qb;
end srff s1(q,qb, s,r,clk,rst);
endmodule initial
clk=1'b0;
always
#5 clk=~clk;
initial
begin
rst = 1’b1;
#10 rst = 1’b0; s=1'b0;r=1'b1;
#10 s=1'b1;r=1'b0;
#15 s=1'b0;r=1'b0;
#20 s=1'b1;r=1'b1;
#20;
end
endmodule
D flipflop JK Flipflop
module dff(d,clk,rst,q,qb); module jkff(q,qbar,j.k,clk,rst);
input d,clk,rst; input j,k,clk,rst;
output q,qb; output q,qbar;
reg q,qb; reg q,qbar;
always@(posedge clk) reg [1:0] jk;
begin always@(posedge clk)
if (rst ==1) begin
q=1’b0; if(rst)
else q = 1’b0;
q=d; else
qb=~d; jk = {j,k}
end case (jk)
endmodule 2’b00: q=q;
//Test bench 2’b01: q=1’b0;
module dfftest; 2’b10: q=1’b1;
reg clk,d,rst; 2’b11: q=~q;
wire q,qb; endcase
dff d1(d,clk,rst,q,qb); qbar =~q;
initial end
clk = 1'b0; endmodule
always //Test bench
#5clk=~clk; module jkfftest;
initial reg j,k,clk,rst;
begin wire q,qbar;
rst=1’b1; jkff jk1(q,qbar,j,k,clk,rst);
#10 rst = 1’b0;d=1'b0; initial
#10d=1'b1; clk=1'b0;
end always
endmodule #5 clk=~clk;
initial
begin
rst = 1’b1;
#10 rst = 1’b0; j=1’b0;k=1’b0;
#10 k=1’b1;
#10 j=1’b1; k=1’b0;
#10 k=1b1;
end
endmodule
Master slave T flipflop
module ms_jkff (qs,qsb,qm,qmb,j,k,clk,rst); module tff(q,qb, rst,clk,t);
output qs, qsb; input rst,clk,t;
inout qm,qmb; output q,qb;
input j,k,clk,rst; reg q,qb;
wire clkbar; always @(posedge clk)
assign clkbar = ~ clk; begin
jkff jk1 (qm,qmb ,j,k,clk,rst); if (rst ==1)
jkff jk2 (qs,qsb,qm,qmb,clkbar,rst); q=1’b0;
endmodule else
//Test bench if (t==0)
module ms_jkff_test; q=q;
reg j,k,clk,rst; else
wire qs,qsb,qm,qmb; q=~q;
ms_jkff ms1(qs,qsb,qm,qmb,j,k,clk,rst); qb=~q;
initial end
clk = 1’b0; endmodule
always //Test bench
#10 clk = ~clk; module tfftest;
initial reg rst,clk,t;
begin wire q,qb;
rst = 1’b1; j = 1’b0; k= 1’b0; tff t1(q,qb,rst, clk,t);
#15 rst = 1’b0; initial
#25 k = 1’b1; clk=1'b0;
#25 j = 1’b1; k= 1’b0; always
#25 k= 1’b1; #5 clk=~clk;
end initial
endmodule begin
rst = 1’b1;
#10 rst = 1’b0;t=1'b0;
#10 t=1'b1;
end
endmodule