Asynchronous Clock Generator for a 14-bit

Two-stage Pipelined SAR ADC in 0.18 μm CMOS

Kairang Chen, Martin Nielsen-Lönn, Atila Alvandpour
Division of Integrated Circuits and Systems
Department of Electrical Engineering, Linköping University
SE-581 83 Linköping, Sweden, Email: [email protected]

Abstract—This paper describes the design and implementation by using a self-synchronization loop utilizing edge detector.
of an asynchronous clock generator which has been used in Such variable duration allows longer time for the comparator
a 14-bit two-stage pipelined SAR ADCs for low-power sensor to act on smaller input signals. Finally, a 14-bit two-stage
applications. A self-synchronization loop based on an edge
detector was utilized to generate an internal clock with variable pipelined SAR ADC with proposed asynchronous clock gen-
phase and frequency. A tunable delay element enables to allocate erator has been designed and simulated in 0.18 μm CMOS.
the available time for the switch capacitor DACs and the gain- The simulation results show that the ADC achieves an effective
stage. Thereafter, three separate asynchronous clock generators number of bits (ENOB) of 13.58-bit at 10 kS/s sampling rate
were implemented to create the control signals for two sub-ADCs while consuming 2.13 μW. The asynchronous clock generator
and the gain-stage between. Finally, a 14-bit asynchronous two-
stage pipelined SAR ADC was designed and simulated in 0.18 consumes 0.33 μW.
μm CMOS. Detailed pre-layout circuit simulations show that the This paper is organized as follows. Section II describes
ADC achieves a SNDR of 83.5 dB while consuming 2.13 μW with the overview of asynchronous two-stage pipelined SAR ADC.
a sampling rate of 10 kS/s. The corresponding FoM is 177.2 dB. Section III provides the detailed circuit implementation of the
proposed asynchronous clock generator. Section IV presents
Index Terms—Asynchronous clock generator, pipelined SAR the simulation results. Finally, conclusions are drawn in Sec-
ADC, self-synchronization, low-power sensors, delay element. tion V.

I. I NTRODUCTION II. P ROPOSED A SYNCHRONOUS T WO - STAGE P IPELINED

SAR ADC A RCHITECTURE
Wireless sensor networks are employed in many applica-
tions, such as for monitoring bio-potential signals, environ-
            
mental information and interactive multimedia. These appli-          
cations require high-resolution (>12 bits) analog-to-digital
  
converters (ADCs) at low-sampling rates [1]. The successive
approximation register (SAR) assisted pipeline architecture    
has shown to be an attractive architecture to achieve both
Ia
high resolution and low power [2] [3]. Low-power sensors   !
might be active only for very short time triggered for example       $
  % " # 
by an external pulse to acquire the data. Hence, this work   
describes design and implementation of an asynchronous clock
generator for a pipelined SAR ADC with 14-bit resolution 
for low-power sensors. The overall goal has been to arrive 
  
at a flexible clocking scheme which can dynamically and Ia
efficiently allocate the available time for the DAC charge  
redistribution, the comparator and the gain-stage. Such clock 
generators are often based on delay elements. In [2], the Fig. 1. Architecture and timing of the proposed asynchronous two-stage
delay buffer provides a propagation delay of several hundred Pipelined SAR ADC.
picoseconds which is not suitable for low-speed ADCs. In [4],
a delay buffer chain has been implemented to apply a fixed Fig. 1 shows the architecture and timing of the proposed
delay of 10 ns. However, several missing codes are observed 14-bit asynchronous two-stage pipelined SAR ADC. The 7-bit
due to the fixed delay which is not long enough for the DAC SAR ADC with segmented binary-weighted capacitive DAC
to settle all the digital codes. [5] serves as the first-stage in order to reduce the unit capacitor
In this work, in order to provide variable redistribution time value and the chip area. The 3-stage capacitive charge pump
for the switched capacitor DACs, a tunable delay element has (CCP), described in [6], is used as the gain-stage to amplify
been utilized to create a controllable delay. Furthermore, a the residue signal with a inter-stage gain of 8. As the inter-
comparator with variable regeneration time has been achieved stage gain is reduced from 64 to 8, an extra capacitor with

978-1-5090-1095-0/16/$31.00 ©2016 European Union

value of 7Ctot2 is required for the second stage DAC [7] of clkin1 and generates two outputs (outp , outn ), either ’high’
to compensate for the reduced signal swing, where the Ctot2 or ’low’. An NAND gate is used to detect the two outputs and
represents the total capacitance of the capacitor array in the further creates the clk1 . After the comparator completes the
second DAC. An 8-bit SAR ADC with split binary-weighted comparison, the rising edge of clk1 appears for the first time.
capacitive DAC is chosen in order to alleviate the increased A J-K latch combining the clk1 and clk1 td is utilized to create
capacitance requirement in the second-stage DAC. the following phases of clkin1 , where the clk1 td represents
Three asynchronous clock generators were utilized in the the delayed version of the clk1 . When the clk1 td goes low,
ADC to generate the internal control signals for two sub- the clkin1 starts to go high and resets the comparator. Thus
ADCs and the gain-stage respectively. The 1st asynchronous the clk1 is kept low. After a delay of td1 , the clkin1 goes low
clock generator is triggered by an external pulse (fs1 ) which due to the rising edge of clk1 td and the comparator starts
subsequently creates an internal clock signal (clkin1 ) of the a new comparison again. This completes one cycle for the
first sub-ADC. Once the data conversion of the first-stage is internal clock generator. Because the rising edge of clkin1
completed, the start signal (fres ) for the 2nd asynchronous is generated after the comparator completes the comparison,
clock generator is generated by the SAR1 logic and further hence this method gives the comparator sufficient comparison
triggers the 2nd asynchronous clock generator to create the time for the small inputs.
control signal (φa ) for the gain-stage. It should be mentioned
that the φa represents a group of signals including three phases 
for sampling and three phases for amplifying as shown in
Fig. 6b. The clkin2 can be generated by the 3rd generator ." .2
with the trigger pulse fs2 . The tc , td1 and td2 represent the  
comparator’s regeneration time, charge redistribution time of .1 .
DAC and the amplifying time for the gain-stage respectively. 
. '
Since the comparator’s inputs vary with the proceeding of 
conversion, the tc is variable. A tunable RC network was used 
to create a controllable delay.    ./ .0

III. A SYNCHRONOUS C LOCK G ENERATOR .! 

. .
I MPLEMENTATION
A. Internal Clock Generator
Fig. 3. RC delay circuit based on cross-coupled inverter.
The internal clock generator, which is based on self-
synchronization, serves as the key part of the asynchronous From Fig. 2(b), to create the clkin1 , the clk1 td plays an
clock generator. Fig. 2 shows the block diagram of the important role in the entire cycle. Hence the delay circuit is
internal clock generator and its timing diagram. Initially, the the key block in this internal clock generator. To achieve a
microsecond delay, a tunable RC delay circuit as shown in
 Fig. 3 was utilized in this work. It is composed of a RC

network (M1, C) and a dynamic cross-coupled inverter. When
clk1 is high, the output is connected to ground. At the falling
( * edge of clk1 , the capacitor is charged and the output acts as a
# '#   ramp signal. The pulse will not be generated until the rising
   )
   & edge of clk1 happens again. This pulse as one input drives an
 '
AND gate to create the clk1 td . The delay time is controlled by
+, turning the Vbias1 manually from an external voltage source. In
 order to reduce the charge and discharge power consumed by
 the capacitor, the value of C should be kept as low as possible
'-'#
(50 fF in this work). This RC delay element has been used in
 the three asynchronous clock generators for the two sub-ADCs
 (1st and 3rd ) and the gain-stage (2nd ) shown in Fig. 1. Vbias1
& 
was set for the 1st and 3rd clock generators to create td1 and
Vbias2 was used to generate td2 for the 2nd clock generator.
+ , With M1 (0.22 μ/5 μ) and C= 50 fF, Fig. 4 shows the sim-
Fig. 2. (a) Diagram of internal clock generator. (b) Timing diagram of internal ulated results of internal clock generator. A fully differential
clock generator. sinusoidal signal with common mode voltage of 0.9 V and
the amplitude of 10 mV was set as the input and the dynamic
comparator is reset when the rising edge of the trigger pulse latch comparator [8] was chosen to compare the inputs. The
(fs1 ) propagates through an OR gate. Subsequently, the clkin1 comparator is reset at the rising edge of fs1 and started to work
goes low for the first time after the falling edge of fs1 . The at falling edge. With Vbias1 = 0.47 V, the td1 is 7.6 μs and the
comparator compares the two input signals at the falling edge tc is 1.244 ns with 20 mV peak-to-peak inputs whereas this
 2
C. Control Logic of Gain-stage
Voltage (V)

1
The 3-stage CCP architecture as shown in [6] has been used
fs1
to provide a voltage gain of 8. To achieve such voltage gain,
0
0 5 10 15 20 25 30 35 40 45 three phases for sampling (φ1 s ,φ2 s ,φ3 s ) and three phases for
t
0.92 amplifying (φ1 a , φ2 a , fs2 ) are inevitable. Fig. 6a illustrates
Voltage (V)

0.9
inp the control logic. It is composed of four delay elements and
inn
each one supplies a delay of td2 . When fres is high, the output
0.88
0 5 10 15 20 25 30 35 40 45 of first delay element is ’low’ until the delay time up to td2 .
2 During the same time period, the fres propagates through the
1 NAND gate and the signal ’a’ with a delay of td2 is generated.
Voltage (V)

0
By choosing the fres and ’a’ as the inputs of an AND gate, the
2
1 1.244 ns
2
1 1.322 ns first sampling phase φ1 s with pulse width of td2 is created.
−1 0 0
clk , V
in1 bias1
=0.47 V The rest of sampling phase can be achieved by using the same
0 5 10 15 20 25 30 35 40 45 method except the input pulse should be the previous sampling
Time (us)
(a)
phase. Two OR gates are utilized to create the reset signal and
2 φ1 a by connecting the inputs to the relevant outputs of NAND
gates (b, c, d) as shown in Fig. 6a. Finally, the timing diagram
Voltage (V)

1
of the 3-stage CCP gain-sage is shown in Fig. 6b.
0
clk , V =0.55 V
in1 bias1
0 5 10 15 20 25 30 35 40 45 I& s
Time (us)
   +, 
(b)
I & s
Fig. 4. Output waves of internal clock generator. (a) Simulation undergoes
with Vbias1 =0.47 V; (b) Simulation undergoes with Vbias1 =0.55 V. I& s   +,
 
I & s
I & s   +, 
time is 1.322 ns at 30 μs as shown in Fig. 4a due to the smaller I& a
inputs (5 mVpp ). Hence the clkin1 ’s duration of ’low’ varies 
I & s   +,
with the input’s amplitude. Fig. 4b shows the simulated output  I & a
waveform under the Vbias1 =0.55 V. With the same inputs, the +,
td1 is reduced to 3.3 μs.

B. SAR Logic of First-stage ADC 
The block diagram of the SAR logic for the first-stage I& s
controlled by the clkin1 is shown in Fig. 5. It consists of I & s
two separate shift registers. The upper DFFs chain generates
the bit approximation pulses while the DFFs in lower row I & s
store the outputs of the comparator (Cout ). Finally, the switch  
control signals (D13...D7) for the DAC are generated which I& a
will be involved in the ADC conversion. The final DFF on the
far right side generates the trigger pulse (fres ) for the gain- I & a
stage. The same SAR logic architecture was implemented in  
the second-stage except the clock is clkin2 . + ,

Fig. 6. (a) Diagram of control logic of 3-stage CCP gain-stage. (b) Timing
 diagram of 3-stage CCP gain-stage.
 
Q Q Q Q Q
    
BB BB BB BB BB
Q Q Q Q Q IV. S IMULATION RESULTS
         

A 14-bit pipelined SAR ADC with asynchronous clock
generator was designed and simulated in 0.18 μm CMOS.
'
Q  Q Q Q
The segmented binary-weighted capacitive DAC [5] with k=3
  Q
BB BB

BB

BB

BB
serves as the 7-bit first-stage to reduce the unit capacitor value
Q Q Q Q Q
           and chip area. The Cu1 is chosen as 120 fF which satisfies the
mismatch and thermal noise requirements of 14-bit resolution.
The three-stage CCP [6] with source follower as unity-gain
   
buffer was implemented into the gain-stage. Simulation results
Fig. 5. Diagram of SAR control logic for first-stage ADC. show that such gain-stage provides a voltage gain of 7.7. The
gain error caused by the source follower is compensated by
 TABLE I. ADC PERFORMANCE WITH DIFFERENT DELAY
tuning the reference voltage of second DAC. The 8-bit split
DAC with a 31 fF unit capacitor forms the second-stage to CMOS 0.18 μm
Resolution 14-bit
alleviate the increased total capacitance. Furthermore, this 8- Sampling rate 10 kS/s
bit split DAC consists of a 4-bit main DAC and 4-bit sub-DAC Vbias1 ∗ (V) 0.47 0.47 0.49
to further reduce the power consumption. The conventional Vbias2 ∗∗ (V) 0.47 0.49 0.47
bootstrapped switch with a 17-bit linearity is used to achieve td1 /td2 (μs) 7.6/7.6 7.6/6.2 6.2/7.6
SNDR (dB) 83.5 83.4 83.18
the input sampling switch (S1 in Fig. 1) for the first sub-ADC. ENOB (bit) 13.58 13.56 13.53
Simple inverters and transmission gate were used to implement Power Breakdown
the DAC switches and the second sub-ADC’s input sampling Asyn-clock
0.33 0.33 0.39
generators (μW)
switch (S2) respectively. SAR ADCs (μW) 0.63 0.63 0.65
Gain-stage (μW) 1.17 0.94 1.17
0
Total Power (μW) 2.13 1.9 2.21
SNDR = 83.5 dB
−20
SFDR = 94.4 dB FoM (dB) 177.2 177.6 176.7
−40
ENOB = 13.58 bits (*) Bias voltage for 1st and 3rd asyn-clock generators.
PSD [ dB ]

(**) Bias voltage for 2nd asyn-clock generator.

−60

−80

−100
flexible clocking scheme enables to efficiently allocate the
−120
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 available time for the sub-DACs, the comparator and the gain
Frequency [ f / fs ]
stage. Using the proposed asynchronous clock generator, a 14-
bit two-stage pipelined SAR ADC has been designed in 0.18
0 μm CMOS technology. The simulation results demonstrate
SNDR = 83.0 dB
−20 SFDR = 95.7 dB the correct operation and effectiveness of the proposed asyn-
−40
ENOB = 13.49 bits chronous clock generator to achieve an ADC with an ENOB
PSD [ dB ]

−60 of 13.58-bit at a sampling frequency of 10 kHz, with a total

−80 power consumption of 2.13 μW.
−100

−120 VI. ACKNOWLEDGMENTS

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Frequency [ f / fs ] The authors would like to thank Dr. Ingemar Söderquist
Fig. 7. Simulated 2048-point FFT spectrums with 1 kHz and 4.3 kHz inputs for useful technical discussions. This work was financially
at 10 kS/s, Vbias1 =Vbias2 =0.47 V supported in part by the strategic innovation program ‘Smarter
Electronics Systems’ a joint venture of Sweden’s innovation
A 10 kHz external trigger pulse with a 7.7% duty cycle agency, Swedish Research Council Formas, and the Swedish
was required for the simulation. The amplitude of the inputs Energy Agency under the grant agreement No 2015-01305 and
were set to -0.5 dBFS. To compensate the gain error caused in part by the European Union’s Horizon 2020 project ‘smart-
by the source follower in the gain-stage, the reference voltage MEMPHIS’ under the grant agreement No 644378.
of the second DAC was set to 1.75 V. Table I summarizes
the ADC performance with different delay settings (td1 , td2 ).
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