BITS Pilani, Hyderabad Campus First Semester, 2018–2019

CS/ECE/EEE/INSTR F215: Digital Design, Comprehensive Exam (Closed Book)

Time for PART A: 9 : 00 − 11 : 00 AM (120 Minutes) Date : 11th December 2018
Max. Marks for PART A: 80 No. of Pages: 4

PART A
Instructions for Part A:
(1) Questions 1 to 20 are MCQs.
(i) Each correct answer carries +2 marks and wrong answer/Overwritten answer carries -1 mark.
(ii) Write the answers in CAPITAL letters only in the space provided after the instructions
(2) Questions 21 to 28 are short answer type questions.
(i)The final answer/design should be written in the space provided after each question.
(ii) Each correct answer carries +5 marks and wrong/partial answer carries 0 mark.(No Negative marking)
(iii)There will be NO PARTIAL marking for questions 21-28.
(3) Please write your NAME and ID No. on all sheets. Papers without ID No. and Name will not be evaluated.
Name: ID No.:

1. 2. 3. 4. 5. 6. 7. 8. 9. 10.

11. 12. 13. 14. 15. 16. 17. 18. 19. 20.
(For Evaluator’s use)

Total Correct Total Wrong Total Marks

output
D Q J Q
Clock
MSB
Q’ K Q’

Figure 2
Figure 1
Output

DA QA DB QB DC QC

Clock QA’ QB’ QC’

Figure 3

1. Consider Logic circuit shown in Figure 1 consisting of 3-8 decoder with active low enable and active low outputs. Which the
following expression represents Z(A, B, C, D)?
(A) D(B ⊕ C + ĀC̄) (B) D(A C + ĀC̄) (C) D(B C + ĀB̄) (D) D(B ⊕ C + ĀB̄)

2. Which of the following sequence is generated at Q output of JK flip-flop in Figure 2? (Assume both the flip-flop outputs are
initially 0):
(A) 011011011.... (B) 01110111.... (C) 010010010.... (D) 001001001....

3. For the circuit shown in Figure 3 (with D flip-flops), QA, QB and QC are initialized to 1, 0 and 0 respectively. If the frequency
of input clock for this circuit is F, then frequency generated at QA (output) is equal to
(A) F ÷ 5 (B) F ÷ 4 (C) F ÷ 8 (D) F ÷ 6

4. The 9’s complement of a decimal number 5432 is equal to

(A) 3456 (B) 5678 (C) 5679 (D) 4567

5. In K-map based simplification of a boolean function of n variables, a group of 2m adjacent 1’s leads to a term with
(A) n − m + 1 literals (B) n − m − 1 literals (C) n + m literals (D) n − m literals

6. What logic is produced by adding inverter to each input and output of an AND gate?
(A) OR (B) NOR (C) XOR (D) NAND

7. The BCD equivalent of hexadecimal number 1D is

(A) 00100100 (B) 00011101 (C) 00101001 (D) 00011101

Version n. 1 – Page 1
 8. A N :1 MUX with its select lines generated by a N -bit counter operates as a
(A) Modified Multiplexer (B) Parallel-to-Serial Converter
(C) Serial-to-Parallel Converter (D) Modified Counter

9. The adder preferred for applications where circuit minimization is more important than speed is
(A) Parallel Adder (B) Serial Adder (C) Ripple-Carry Adder (D) Carry-lookahead Adder

10. If (25)x + (17)x = (40)x , then the value of x (base of the numbers) is equal to
(A) 10 (B) 12 (C) 13 (D) 11

11. How many 3-to-8 decoders with an enable input are needed to construct a 6-to-64 line decoder without using any other logic
gates?
(A) 9 (B) 8 (C) 7 (D) 10

12. The number of directed arcs terminating to any state of a state diagram is
(A) independent of the number of inputs (B) dependent on the number of outputs
n
(C) 2 where n is number of flip-flops (D) 2n where n is number of inputs

13. The simplified form of the boolean expression (X + Y + Z)(X + Y + Z)(X + Y + Z)

(A) XY + Z (B) X + Y Z (C) XY + Z (D) XY + Z

14. If X = 01110 and Y = 11001 are two 5-bit signed binary numbers, which use 2’s complement format for representing negative
numbers, then X + Y is equal to __.
(A) 001000 (B) 000111 (C) 100111 (D) 101001

15. The possible number of unique boolean functions of 4 variables W, X, Y, and Z such that f(W,X,Y,Z)=f(Z,Y,X,W) (i.e. f(0,0,0,0)
= f(0,0,0,0), f(0,0,0,1)=f(1,0,0,0). . . ) is
(A) 212 (B) 216 (C) 210 (D) 28

16. The following operations are to be done on signed numbers (which 2’s complement representation) using a 4-bit adder-subtractor
circuit with overflow detection. Operation 1: 6 is added to 4, Operation 2: 5 is subtracted from −3. The operation 1 and 2
result in __(i) __and __(ii) __.
(A) (i) Overflow, (ii) No Overflow (B) (i) No Overflow, (ii) No Overflow
(C) (i) No overflow, (ii) Overflow (D) (i) Overflow, (ii) Overflow

17. In ASM chart, Mealy type of outputs

(A) can be represented inside the decision boxes (B) can be represented inside conditional output boxes
(C) cannot be represented (D) can be represented inside state box

18. The complex programmable logic device contains several PLD blocks and __
(A) Global interconnection matrix (B) Field-programmable Gates
(C) A language compiler (D) AND/OR arrays

19. Consider a mod-12 synchronous counter with QD QC QB QA as outputs (assume QD as MSB). If the frequency of QC of the
mod-12 counter is 6KHz, then the frequency of input clock signal is __
(A) 48KHz (B) 72KHz (C) 12KHz (D) 24KHz

20. A circuit consists of two clocked JK flip-flops with J0 = K0 = Q1 , J1 = Q0 , K1 = Q0 . Each flip-flop receives clock input
simultaneously. Also Q1 represents MSB and both Q1 & Q0 are 0 initially. This circuit acts as
(A) 2-bit Shift register (B) mod-4 Counter (C) mod-3 Counter (D) mod-2 Counter

P P
21. Implement the functions F1 (A, B, C) = (1, 3, 6, 7) and F2 (A, B, C) = (0, 1, 6, 7) using PLA structure below after minimizing
the number of product terms. (Mark x appropriately in the PLA Structure given below and also label AND array outputs)
A

B
C

C C’ B B’ A A’

F1 F2
Version n. 1 – Page 2
 Name: ID No.:

22. The figure shows a combinational circuit consisting of a NOR-gate and an OR-gate (left figure). If the same functionality has to
be realized using a NAND-NAND circuit (Right figure), then find the inputs to NAND-NAND circuit. (Assume variables and
their complements are available as inputs. Write your answers in the boxes provided)

23. Design a circuit to multiply any 4-bit number (x3 x2 x1 x0 ) by a constant value (0110)2 i.e. (6)10 , to give 8-bit output
(p7 p6 p5 p4 p3 p2 p1 p0 ), using only a 5-bit adder. No other gates/components should be used. The adder block, available inputs
and expected outputs are shown below. Complete the circuit (assume logic 1 and logic 0 are also available as inputs).

P
24. Given a function f (A, B, C, D) = m(0, 1, 2, 3, 4, 6, 8, 9)+dc(10, 11), minimize the function using K-map and find the minimized
expression in SOP form. (Show the K-Map grouping and write the expression in space provided)

25. A circuit, with positive edge triggered D Flip-flops with asynchronous active low preset (PRE) and clear (CLR) pins, is shown
in the figure below. The Waveforms of X and Clock are also shown. Draw the Output waveform in the space provided. (Assume
both the flip-flops are in logic ‘0’ state initially)

X Logic ‘1’ 1
X
Logic ‘0’
D PRE Q D PRE Q
Output 0
Clock CLK Clock
CLK
0
CLR Q’ CLR Q’

Logic ‘1’ Logic ‘1’

Output 0

Version n. 1 – Page 3
26. For the sequential circuit shown below. Draw the complete state digram (Assume Q1 as MSB. Show the transitions for all
possible states)

27. Two synchronous 2-bit counters are available as shown below. Counter 1 is a normal 2-bit binary counter with QA1 , QA0 as
outputs, Whereas Counter 2 is a 2-bit binary counter with Enable (En) input and QB1 QB0 as outputs. If En=0, Counter 2 will
remain in the same state (i.e. counter stops) and if En=1, the Counter 2 will behave like normal binary counter. Design a 4-bit
synchronous counter (with Q3 Q2 Q1 Q0 as outputs) by using Counter 1, Counter 2 and only one additional gate. (Complete the
circuit below by adding one gate and making appropriate connections)

Common Clock

En
Clk Clk
Counter 2 Counter 1
MSB MSB

MSB

28. Convert the State Diagram in to ASM chart.

Complete the ASM

S0
W=1/Z=0
W=1/Z=1
W=0/Z=0
S0 S1

W=0/Z=0

S1

Version n. 1 – Page 4
 BITS Pilani, Hyderabad Campus First Semester, 2018–2019
CS/ECE/EEE/INSTR F215: Digital Design, Comprehensive Exam (Closed Book)
Time for PART A: 9 : 00 − 11 : 00 AM (120 Minutes) Date : 11th December 2018
Max. Marks for PART A: 80 No. of Pages: 4

PART A
Instructions for Part A:
(1) Questions 1 to 20 are MCQs.
(i) Each correct answer carries +2 marks and wrong answer/Overwritten answer carries -1 mark.
(ii) Write the answers in CAPITAL letters only in the space provided after the instructions
(2) Questions 21 to 28 are short answer type questions.
(i)The final answer/design should be written in the space provided after each question.
(ii) Each correct answer carries +5 marks and wrong/partial answer carries 0 mark.(No Negative marking)
(iii)There will be NO PARTIAL marking for questions 21-28.
(3) Please write your NAME and ID No. on all sheets. Papers without ID No. and Name will not be evaluated.
Name: ID No.:

1. 2. 3. 4. 5. 6. 7. 8. 9. 10.

11. 12. 13. 14. 15. 16. 17. 18. 19. 20.
(For Evaluator’s use)

Total Correct Total Wrong Total Marks

output
D Q J Q
Clock
MSB
Q’ K Q’

Figure 2
Figure 1
Output

DA QA DB QB DC QC

Clock QA’ QB’ QC’

Figure 3
1. Consider Logic circuit shown in Figure 1 consisting of 3-8 decoder with active low enable and active low outputs. Which the
following expression represents Z(A, B, C, D)?
(A) D(B ⊕ C + ĀC̄) (B) D(B ⊕ C + ĀB̄) (C) D(B C + ĀB̄) (D) D(A C + ĀC̄)

2. Which of the following sequence is generated at Q output of JK flip-flop in Figure 2? (Assume both the flip-flop outputs are
initially 0):
(A) 001001001.... (B) 010010010.... (C) 01110111.... (D) 011011011....

3. For the circuit shown in Figure 3 (with D flip-flops), QA, QB and QC are initialized to 1, 0 and 0 respectively. If the frequency
of input clock for this circuit is F, then frequency generated at QA (output) is equal to
(A) F ÷ 5 (B) F ÷ 4 (C) F ÷ 6 (D) F ÷ 8

4. Consider a mod-12 synchronous counter with QD QC QB QA as outputs (assume QD as MSB). If the frequency of QC of the
mod-12 counter is 6KHz, then the frequency of input clock signal is __
(A) 48KHz (B) 12KHz (C) 24KHz (D) 72KHz

5. The possible number of unique boolean functions of 4 variables W, X, Y, and Z such that f(W,X,Y,Z)=f(Z,Y,X,W) (i.e. f(0,0,0,0)
= f(0,0,0,0), f(0,0,0,1)=f(1,0,0,0). . . ) is
(A) 28 (B) 216 (C) 210 (D) 212

6. What logic is produced by adding inverter to each input and output of an AND gate?
(A) XOR (B) NAND (C) OR (D) NOR

7. The 9’s complement of a decimal number 5432 is equal to

(A) 5679 (B) 4567 (C) 5678 (D) 3456
Version n. 2 – Page 1
 8. The following operations are to be done on signed numbers (which 2’s complement representation) using a 4-bit adder-subtractor
circuit with overflow detection. Operation 1: 6 is added to 4, Operation 2: 5 is subtracted from −3. The operation 1 and 2
result in __(i) __and __(ii) __.
(A) (i) No Overflow, (ii) No Overflow (B) (i) Overflow, (ii) Overflow
(C) (i) Overflow, (ii) No Overflow (D) (i) No overflow, (ii) Overflow

9. How many 3-to-8 decoders with an enable input are needed to construct a 6-to-64 line decoder without using any other logic
gates?
(A) 10 (B) 7 (C) 9 (D) 8

10. The complex programmable logic device contains several PLD blocks and __
(A) Global interconnection matrix (B) AND/OR arrays
(C) Field-programmable Gates (D) A language compiler

11. In K-map based simplification of a boolean function of n variables, a group of 2m adjacent 1’s leads to a term with
(A) n − m − 1 literals (B) n − m + 1 literals (C) n − m literals (D) n + m literals

12. The number of directed arcs terminating to any state of a state diagram is
(A) independent of the number of inputs (B) 2n where n is number of flip-flops
n
(C) 2 where n is number of inputs (D) dependent on the number of outputs

13. The BCD equivalent of hexadecimal number 1D is

(A) 00011101 (B) 00101001 (C) 00100100 (D) 00011101

14. A circuit consists of two clocked JK flip-flops with J0 = K0 = Q1 , J1 = Q0 , K1 = Q0 . Each flip-flop receives clock input
simultaneously. Also Q1 represents MSB and both Q1 & Q0 are 0 initially. This circuit acts as
(A) mod-2 Counter (B) mod-3 Counter (C) 2-bit Shift register (D) mod-4 Counter

15. In ASM chart, Mealy type of outputs

(A) can be represented inside the decision boxes (B) cannot be represented
(C) can be represented inside state box (D) can be represented inside conditional output boxes

16. If (25)x + (17)x = (40)x , then the value of x (base of the numbers) is equal to
(A) 12 (B) 11 (C) 13 (D) 10

17. If X = 01110 and Y = 11001 are two 5-bit signed binary numbers, which use 2’s complement format for representing negative
numbers, then X + Y is equal to __.
(A) 101001 (B) 000111 (C) 100111 (D) 001000

18. A N :1 MUX with its select lines generated by a N -bit counter operates as a
(A) Modified Multiplexer (B) Parallel-to-Serial Converter
(C) Serial-to-Parallel Converter (D) Modified Counter

19. The adder preferred for applications where circuit minimization is more important than speed is
(A) Serial Adder (B) Ripple-Carry Adder (C) Parallel Adder (D) Carry-lookahead Adder

20. The simplified form of the boolean expression (X + Y + Z)(X + Y + Z)(X + Y + Z)

(A) X + Y Z (B) XY + Z (C) XY + Z (D) XY + Z

P P
21. Implement the functions F1 (A, B, C) = (1, 3, 6, 7) and F2 (A, B, C) = (0, 1, 6, 7) using PLA structure below after minimizing
the number of product terms. (Mark x appropriately in the PLA Structure given below and also label AND array outputs)
A

B
C

C C’ B B’ A A’

F1 F2

Version n. 2 – Page 2
 Name: ID No.:

22. The figure shows a combinational circuit consisting of a NOR-gate and an OR-gate (left figure). If the same functionality has to
be realized using a NAND-NAND circuit (Right figure), then find the inputs to NAND-NAND circuit. (Assume variables and
their complements are available as inputs. Write your answers in the boxes provided)

23. Design a circuit to multiply any 4-bit number (x3 x2 x1 x0 ) by a constant value (0110)2 i.e. (6)10 , to give 8-bit output
(p7 p6 p5 p4 p3 p2 p1 p0 ), using only a 5-bit adder. No other gates/components should be used. The adder block, available inputs
and expected outputs are shown below. Complete the circuit (assume logic 1 and logic 0 are also available as inputs).

P
24. Given a function f (A, B, C, D) = m(0, 1, 2, 3, 4, 6, 8, 9)+dc(10, 11), minimize the function using K-map and find the minimized
expression in SOP form. (Show the K-Map grouping and write the expression in space provided)

25. A circuit, with positive edge triggered D Flip-flops with asynchronous active low preset (PRE) and clear (CLR) pins, is shown
in the figure below. The Waveforms of X and Clock are also shown. Draw the Output waveform in the space provided. (Assume
both the flip-flops are in logic ‘0’ state initially)

X Logic ‘1’ 1
X
Logic ‘0’
D PRE Q D PRE Q
Output 0
Clock CLK Clock
CLK
0
CLR Q’ CLR Q’

Logic ‘1’ Logic ‘1’

Output 0

Version n. 2 – Page 3
26. For the sequential circuit shown below. Draw the complete state digram (Assume Q1 as MSB. Show the transitions for all
possible states)

27. Two synchronous 2-bit counters are available as shown below. Counter 1 is a normal 2-bit binary counter with QA1 , QA0 as
outputs, Whereas Counter 2 is a 2-bit binary counter with Enable (En) input and QB1 QB0 as outputs. If En=0, Counter 2 will
remain in the same state (i.e. counter stops) and if En=1, the Counter 2 will behave like normal binary counter. Design a 4-bit
synchronous counter (with Q3 Q2 Q1 Q0 as outputs) by using Counter 1, Counter 2 and only one additional gate. (Complete the
circuit below by adding one gate and making appropriate connections)

Common Clock

En
Clk Clk
Counter 2 Counter 1
MSB MSB

MSB

28. Convert the State Diagram in to ASM chart.

Complete the ASM

S0
W=1/Z=0
W=1/Z=1
W=0/Z=0
S0 S1

W=0/Z=0

S1

Version n. 2 – Page 4
 BITS Pilani, Hyderabad Campus First Semester, 2018–2019
CS/ECE/EEE/INSTR F215: Digital Design, Comprehensive Exam (Closed Book)
Time for PART A: 9 : 00 − 11 : 00 AM (120 Minutes) Date : 11th December 2018
Max. Marks for PART A: 80 No. of Pages: 4
PART A
Instructions for Part A:
(1) Questions 1 to 20 are MCQs.
(i) Each correct answer carries +2 marks and wrong answer/Overwritten answer carries -1 mark.
(ii) Write the answers in CAPITAL letters only in the space provided after the instructions
(2) Questions 21 to 28 are short answer type questions.
(i)The final answer/design should be written in the space provided after each question.
(ii) Each correct answer carries +5 marks and wrong/partial answer carries 0 mark.(No Negative marking)
(iii)There will be NO PARTIAL marking for questions 21-28.
(3) Please write your NAME and ID No. on all sheets. Papers without ID No. and Name will not be evaluated.
Name: ID No.:

1. 2. 3. 4. 5. 6. 7. 8. 9. 10.

11. 12. 13. 14. 15. 16. 17. 18. 19. 20.
(For Evaluator’s use)

Total Correct Total Wrong Total Marks

output
D Q J Q
Clock
MSB
Q’ K Q’

Figure 2
Figure 1
Output

DA QA DB QB DC QC

Clock QA’ QB’ QC’

Figure 3
1. Consider Logic circuit shown in Figure 1 consisting of 3-8 decoder with active low enable and active low outputs. Which the
following expression represents Z(A, B, C, D)?
(A) D(B ⊕ C + ĀC̄) (B) D(B C + ĀB̄) (C) D(B ⊕ C + ĀB̄) (D) D(A C + ĀC̄)

2. Which of the following sequence is generated at Q output of JK flip-flop in Figure 2? (Assume both the flip-flop outputs are
initially 0):
(A) 010010010.... (B) 001001001.... (C) 01110111.... (D) 011011011....

3. For the circuit shown in Figure 3 (with D flip-flops), QA, QB and QC are initialized to 1, 0 and 0 respectively. If the frequency
of input clock for this circuit is F, then frequency generated at QA (output) is equal to
(A) F ÷ 5 (B) F ÷ 6 (C) F ÷ 4 (D) F ÷ 8

4. The 9’s complement of a decimal number 5432 is equal to

(A) 5678 (B) 5679 (C) 4567 (D) 3456

5. If X = 01110 and Y = 11001 are two 5-bit signed binary numbers, which use 2’s complement format for representing negative
numbers, then X + Y is equal to __.
(A) 100111 (B) 101001 (C) 000111 (D) 001000

6. How many 3-to-8 decoders with an enable input are needed to construct a 6-to-64 line decoder without using any other logic
gates?
(A) 7 (B) 9 (C) 10 (D) 8

7. The possible number of unique boolean functions of 4 variables W, X, Y, and Z such that f(W,X,Y,Z)=f(Z,Y,X,W) (i.e. f(0,0,0,0)
= f(0,0,0,0), f(0,0,0,1)=f(1,0,0,0). . . ) is
(A) 210 (B) 212 (C) 28 (D) 216
Version n. 3 – Page 1
 8. The adder preferred for applications where circuit minimization is more important than speed is
(A) Parallel Adder (B) Ripple-Carry Adder (C) Carry-lookahead Adder (D) Serial Adder

9. What logic is produced by adding inverter to each input and output of an AND gate?
(A) XOR (B) OR (C) NOR (D) NAND

10. In ASM chart, Mealy type of outputs

(A) can be represented inside the decision boxes (B) cannot be represented
(C) can be represented inside state box (D) can be represented inside conditional output boxes

11. The number of directed arcs terminating to any state of a state diagram is
(A) dependent on the number of outputs (B) independent of the number of inputs
n
(C) 2 where n is number of flip-flops (D) 2n where n is number of inputs

12. The following operations are to be done on signed numbers (which 2’s complement representation) using a 4-bit adder-subtractor
circuit with overflow detection. Operation 1: 6 is added to 4, Operation 2: 5 is subtracted from −3. The operation 1 and 2
result in __(i) __and __(ii) __.
(A) (i) No overflow, (ii) Overflow (B) (i) Overflow, (ii) Overflow
(C) (i) No Overflow, (ii) No Overflow (D) (i) Overflow, (ii) No Overflow

13. In K-map based simplification of a boolean function of n variables, a group of 2m adjacent 1’s leads to a term with
(A) n − m − 1 literals (B) n − m + 1 literals (C) n + m literals (D) n − m literals

14. A N :1 MUX with its select lines generated by a N -bit counter operates as a
(A) Serial-to-Parallel Converter (B) Modified Multiplexer
(C) Modified Counter (D) Parallel-to-Serial Converter

15. The simplified form of the boolean expression (X + Y + Z)(X + Y + Z)(X + Y + Z)

(A) XY + Z (B) XY + Z (C) X + Y Z (D) XY + Z

16. Consider a mod-12 synchronous counter with QD QC QB QA as outputs (assume QD as MSB). If the frequency of QC of the
mod-12 counter is 6KHz, then the frequency of input clock signal is __
(A) 12KHz (B) 48KHz (C) 72KHz (D) 24KHz

17. The BCD equivalent of hexadecimal number 1D is

(A) 00101001 (B) 00100100 (C) 00011101 (D) 00011101

18. A circuit consists of two clocked JK flip-flops with J0 = K0 = Q1 , J1 = Q0 , K1 = Q0 . Each flip-flop receives clock input
simultaneously. Also Q1 represents MSB and both Q1 & Q0 are 0 initially. This circuit acts as
(A) mod-2 Counter (B) mod-3 Counter (C) 2-bit Shift register (D) mod-4 Counter

19. If (25)x + (17)x = (40)x , then the value of x (base of the numbers) is equal to
(A) 12 (B) 13 (C) 10 (D) 11

20. The complex programmable logic device contains several PLD blocks and __
(A) AND/OR arrays (B) Global interconnection matrix
(C) Field-programmable Gates (D) A language compiler

P P
21. Implement the functions F1 (A, B, C) = (1, 3, 6, 7) and F2 (A, B, C) = (0, 1, 6, 7) using PLA structure below after minimizing
the number of product terms. (Mark x appropriately in the PLA Structure given below and also label AND array outputs)
A

B
C

C C’ B B’ A A’

F1 F2

Version n. 3 – Page 2
 Name: ID No.:

22. The figure shows a combinational circuit consisting of a NOR-gate and an OR-gate (left figure). If the same functionality has to
be realized using a NAND-NAND circuit (Right figure), then find the inputs to NAND-NAND circuit. (Assume variables and
their complements are available as inputs. Write your answers in the boxes provided)

23. Design a circuit to multiply any 4-bit number (x3 x2 x1 x0 ) by a constant value (0110)2 i.e. (6)10 , to give 8-bit output
(p7 p6 p5 p4 p3 p2 p1 p0 ), using only a 5-bit adder. No other gates/components should be used. The adder block, available inputs
and expected outputs are shown below. Complete the circuit (assume logic 1 and logic 0 are also available as inputs).

P
24. Given a function f (A, B, C, D) = m(0, 1, 2, 3, 4, 6, 8, 9)+dc(10, 11), minimize the function using K-map and find the minimized
expression in SOP form. (Show the K-Map grouping and write the expression in space provided)

25. A circuit, with positive edge triggered D Flip-flops with asynchronous active low preset (PRE) and clear (CLR) pins, is shown
in the figure below. The Waveforms of X and Clock are also shown. Draw the Output waveform in the space provided. (Assume
both the flip-flops are in logic ‘0’ state initially)

X Logic ‘1’ 1
X
Logic ‘0’
D PRE Q D PRE Q
Output 0
Clock CLK Clock
CLK
0
CLR Q’ CLR Q’

Logic ‘1’ Logic ‘1’

Output 0

Version n. 3 – Page 3
26. For the sequential circuit shown below. Draw the complete state digram (Assume Q1 as MSB. Show the transitions for all
possible states)

27. Two synchronous 2-bit counters are available as shown below. Counter 1 is a normal 2-bit binary counter with QA1 , QA0 as
outputs, Whereas Counter 2 is a 2-bit binary counter with Enable (En) input and QB1 QB0 as outputs. If En=0, Counter 2 will
remain in the same state (i.e. counter stops) and if En=1, the Counter 2 will behave like normal binary counter. Design a 4-bit
synchronous counter (with Q3 Q2 Q1 Q0 as outputs) by using Counter 1, Counter 2 and only one additional gate. (Complete the
circuit below by adding one gate and making appropriate connections)

Common Clock

En
Clk Clk
Counter 2 Counter 1
MSB MSB

MSB

28. Convert the State Diagram in to ASM chart.

Complete the ASM

S0
W=1/Z=0
W=1/Z=1
W=0/Z=0
S0 S1

W=0/Z=0

S1

Version n. 3 – Page 4
 BITS Pilani, Hyderabad Campus First Semester, 2018–2019
CS/ECE/EEE/INSTR F215: Digital Design, Comprehensive Exam (Closed Book)
Time for PART A: 9 : 00 − 11 : 00 AM (120 Minutes) Date : 11th December 2018
Max. Marks for PART A: 80 No. of Pages: 4

PART A
Instructions for Part A:
(1) Questions 1 to 20 are MCQs.
(i) Each correct answer carries +2 marks and wrong answer/Overwritten answer carries -1 mark.
(ii) Write the answers in CAPITAL letters only in the space provided after the instructions
(2) Questions 21 to 28 are short answer type questions.
(i)The final answer/design should be written in the space provided after each question.
(ii) Each correct answer carries +5 marks and wrong/partial answer carries 0 mark.(No Negative marking)
(iii)There will be NO PARTIAL marking for questions 21-28.
(3) Please write your NAME and ID No. on all sheets. Papers without ID No. and Name will not be evaluated.
Name: ID No.:

1. 2. 3. 4. 5. 6. 7. 8. 9. 10.

11. 12. 13. 14. 15. 16. 17. 18. 19. 20.
(For Evaluator’s use)

Total Correct Total Wrong Total Marks

output
D Q J Q
Clock
MSB
Q’ K Q’

Figure 2
Figure 1
Output

DA QA DB QB DC QC

Clock QA’ QB’ QC’

Figure 3

1. Consider Logic circuit shown in Figure 1 consisting of 3-8 decoder with active low enable and active low outputs. Which the
following expression represents Z(A, B, C, D)?
(A) D(B ⊕ C + ĀC̄) (B) D(A C + ĀC̄) (C) D(B ⊕ C + ĀB̄) (D) D(B C + ĀB̄)

2. Which of the following sequence is generated at Q output of JK flip-flop in Figure 2? (Assume both the flip-flop outputs are
initially 0):
(A) 001001001.... (B) 01110111.... (C) 011011011.... (D) 010010010....

3. For the circuit shown in Figure 3 (with D flip-flops), QA, QB and QC are initialized to 1, 0 and 0 respectively. If the frequency
of input clock for this circuit is F, then frequency generated at QA (output) is equal to
(A) F ÷ 5 (B) F ÷ 8 (C) F ÷ 6 (D) F ÷ 4

4. The complex programmable logic device contains several PLD blocks and __
(A) AND/OR arrays (B) Field-programmable Gates
(C) A language compiler (D) Global interconnection matrix

5. If X = 01110 and Y = 11001 are two 5-bit signed binary numbers, which use 2’s complement format for representing negative
numbers, then X + Y is equal to __.
(A) 000111 (B) 001000 (C) 101001 (D) 100111

6. A N :1 MUX with its select lines generated by a N -bit counter operates as a

(A) Parallel-to-Serial Converter (B) Serial-to-Parallel Converter
(C) Modified Counter (D) Modified Multiplexer

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 7. The adder preferred for applications where circuit minimization is more important than speed is
(A) Serial Adder (B) Parallel Adder (C) Carry-lookahead Adder (D) Ripple-Carry Adder

8. The number of directed arcs terminating to any state of a state diagram is

(A) independent of the number of inputs (B) 2n where n is number of inputs
n
(C) 2 where n is number of flip-flops (D) dependent on the number of outputs

9. The BCD equivalent of hexadecimal number 1D is

(A) 00101001 (B) 00011101 (C) 00100100 (D) 00011101

10. The following operations are to be done on signed numbers (which 2’s complement representation) using a 4-bit adder-subtractor
circuit with overflow detection. Operation 1: 6 is added to 4, Operation 2: 5 is subtracted from −3. The operation 1 and 2
result in __(i) __and __(ii) __.
(A) (i) No overflow, (ii) Overflow (B) (i) Overflow, (ii) No Overflow
(C) (i) No Overflow, (ii) No Overflow (D) (i) Overflow, (ii) Overflow

11. Consider a mod-12 synchronous counter with QD QC QB QA as outputs (assume QD as MSB). If the frequency of QC of the
mod-12 counter is 6KHz, then the frequency of input clock signal is __
(A) 48KHz (B) 12KHz (C) 72KHz (D) 24KHz

12. The possible number of unique boolean functions of 4 variables W, X, Y, and Z such that f(W,X,Y,Z)=f(Z,Y,X,W) (i.e. f(0,0,0,0)
= f(0,0,0,0), f(0,0,0,1)=f(1,0,0,0). . . ) is
(A) 28 (B) 210 (C) 216 (D) 212

13. If (25)x + (17)x = (40)x , then the value of x (base of the numbers) is equal to
(A) 11 (B) 13 (C) 10 (D) 12

14. The simplified form of the boolean expression (X + Y + Z)(X + Y + Z)(X + Y + Z)

(A) X + Y Z (B) XY + Z (C) XY + Z (D) XY + Z

15. What logic is produced by adding inverter to each input and output of an AND gate?
(A) NOR (B) XOR (C) NAND (D) OR

16. How many 3-to-8 decoders with an enable input are needed to construct a 6-to-64 line decoder without using any other logic
gates?
(A) 7 (B) 8 (C) 9 (D) 10

17. In ASM chart, Mealy type of outputs

(A) can be represented inside the decision boxes (B) cannot be represented
(C) can be represented inside state box (D) can be represented inside conditional output boxes

18. In K-map based simplification of a boolean function of n variables, a group of 2m adjacent 1’s leads to a term with
(A) n − m + 1 literals (B) n + m literals (C) n − m − 1 literals (D) n − m literals

19. The 9’s complement of a decimal number 5432 is equal to

(A) 5678 (B) 3456 (C) 4567 (D) 5679

20. A circuit consists of two clocked JK flip-flops with J0 = K0 = Q1 , J1 = Q0 , K1 = Q0 . Each flip-flop receives clock input
simultaneously. Also Q1 represents MSB and both Q1 & Q0 are 0 initially. This circuit acts as
(A) 2-bit Shift register (B) mod-4 Counter (C) mod-2 Counter (D) mod-3 Counter

P P
21. Implement the functions F1 (A, B, C) = (1, 3, 6, 7) and F2 (A, B, C) = (0, 1, 6, 7) using PLA structure below after minimizing
the number of product terms. (Mark x appropriately in the PLA Structure given below and also label AND array outputs)
A

B
C

C C’ B B’ A A’

F1 F2

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 Name: ID No.:

22. The figure shows a combinational circuit consisting of a NOR-gate and an OR-gate (left figure). If the same functionality has to
be realized using a NAND-NAND circuit (Right figure), then find the inputs to NAND-NAND circuit. (Assume variables and
their complements are available as inputs. Write your answers in the boxes provided)

23. Design a circuit to multiply any 4-bit number (x3 x2 x1 x0 ) by a constant value (0110)2 i.e. (6)10 , to give 8-bit output
(p7 p6 p5 p4 p3 p2 p1 p0 ), using only a 5-bit adder. No other gates/components should be used. The adder block, available inputs
and expected outputs are shown below. Complete the circuit (assume logic 1 and logic 0 are also available as inputs).

P
24. Given a function f (A, B, C, D) = m(0, 1, 2, 3, 4, 6, 8, 9)+dc(10, 11), minimize the function using K-map and find the minimized
expression in SOP form. (Show the K-Map grouping and write the expression in space provided)

25. A circuit, with positive edge triggered D Flip-flops with asynchronous active low preset (PRE) and clear (CLR) pins, is shown
in the figure below. The Waveforms of X and Clock are also shown. Draw the Output waveform in the space provided. (Assume
both the flip-flops are in logic ‘0’ state initially)

X Logic ‘1’ 1
X
Logic ‘0’
D PRE Q D PRE Q
Output 0
Clock CLK Clock
CLK
0
CLR Q’ CLR Q’

Logic ‘1’ Logic ‘1’

Output 0

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26. For the sequential circuit shown below. Draw the complete state digram (Assume Q1 as MSB. Show the transitions for all
possible states)

27. Two synchronous 2-bit counters are available as shown below. Counter 1 is a normal 2-bit binary counter with QA1 , QA0 as
outputs, Whereas Counter 2 is a 2-bit binary counter with Enable (En) input and QB1 QB0 as outputs. If En=0, Counter 2 will
remain in the same state (i.e. counter stops) and if En=1, the Counter 2 will behave like normal binary counter. Design a 4-bit
synchronous counter (with Q3 Q2 Q1 Q0 as outputs) by using Counter 1, Counter 2 and only one additional gate. (Complete the
circuit below by adding one gate and making appropriate connections)

Common Clock

En
Clk Clk
Counter 2 Counter 1
MSB MSB

MSB

28. Convert the State Diagram in to ASM chart.

Complete the ASM

S0
W=1/Z=0
W=1/Z=1
W=0/Z=0
S0 S1

W=0/Z=0

S1

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