International Journal of Scientific and Research Publications, Volume 3, Issue 3, March 2013 1

ISSN 2250-3153

Design and Implementation of 8X8 Truncated Multiplier

on FPGA
Suresh R.Rijal (Asst. Prof. KITS, Ramtek), Ms.Sharda G. Mungale (Asst. Prof. PCEA, Nagpur)

Abstract- Multiplication is frequently required in digital signal significantly reduced, and in many cases the delay also
processing. Parallel multipliers provide a high-speed method for decreases.
multiplication, but require large area for VLSI implementations. The trade-off is that truncating the multiplier matrix introduces
In most signal processing applications, a rounded product is additional error into the computation. Recent advancements in
desired to avoid growth in word size. Thus an important design VLSI technology and in particular, the increasing complexity and
goal is to reduce the area requirement of the rounded output capacity of state-of-the-art programmable logic devices have
multiplier. This paper presents a method for parallel been making hardware emulations possible. The underlying key
multiplication which computes the products of two n-bit numbers of the emulation system is to use SRAM-based field
by summing only the most significant columns with a variable programmable gate arrays (FPGAs) which are very flexible and
correction method. This paper also presents a comparative study dynamically reconfigurable. In many cases implementation of
of Field Programmable Gate Array (FPGA) implementation of DSP algorithm demands using Application Specific Integrated
8X8 standard and truncated multipliers using Very High Speed Circuits(ASICs).The development cost for Application Specific
Integrated Circuit Hardware Description Language (VHDL). Integrated Circuits(ASICs) are high, algorithms should be
Truncated multipliers can be used in finite impulse response verified and optimized before implementation. The Digital Signal
(FIR) and discrete cosine transforms (DCT). The truncated Processing (DSP), image processing and multimedia requires
multiplier shows much more reduction in device utilization as extensive use of multiplication. The truncated multipliers can
compared to standard multiplier. Significant reduction in FPGA easily be implemented using Field Programmable Gate Array
resources, delay, and power can be achieved using truncated (FPGA) devices.
multipliers instead of standard parallel multipliers when the full In FPGAs, the choice of the optimum multiplier involves three
precision of the standard multiplier is not required. key factors: area, propagation delay and reconfiguration time. An
FPGA is a digital integrated circuit that comes in a wide variety
Index Terms- Digital Signal Processing (DSP), Field of size and with many different combinations of internal and
Programmable Gate Array (FPGA), Truncated Multiplier, external features. The state-of-the-art FPGAs consist of relatively
Variable correction method, VHDL small blocks of programmable logic. These blocks, each of
which typically contains a few registers and a few dozen low
level, configurable logic elements, are arranged in a grid pattern
I. INTRODUCTION and tied together using programmable interconnects. The
truncated multipliers can be designed using either constant
P arallel multipliers provide high speed method for
multiplications, but require large area for VLSI
implementation. In most signal processing applications, rounded
correction method or variable correction method.

product is required to avoid growth in word size. Thus an CONSTANT CORRECTION METHOD
important aim is to design a multiplier which required less area
and that is possible with the truncated multiplier. In the wireless In constant correction method design the lower N columns of a
multimedia word, DSP systems are ubiquitous. DSP algorithms parallel multiplier are truncated and a correction is then added to
are computationally intensive and test the limits of battery life in the remaining most significant columns. The Constant Correction
portable device such as cell phones, hearing aids, MP3 players, Methods (CCM) uses a constant value, independent on the actual
digital video recorders and so on. Multiplication is the main values of the inputs, in order to estimate the LSP minor.
operation in many signal processing algorithms hence efficient The multiplier output can be written as:
parallel multipliers is desirable. A full-width digital n × n bits PCCM = truncn(SMSP + SLSP major + constant) -------- (1)
multiplier computes the 2n bits output as a weighted sum of
partial products. A multiplier with the output represented on n where SLSP major is the weighted sum of the elements of the
bits output is useful, as example, in DSP data paths which saves LSP major.
the output in the same n bits registers of the input. A truncated In this technique the LSP is eliminated and is substituted by a
multiplier is an n × n multiplier with n bits output. Since in a constant term, calculated considering only the lose carries. This
truncated multiplier the n less significant bits of the full-width approach reduces up to 50% the area of the full-width multiplier,
product are discarded, some of the partial products are removed but introduces a rather large error, which rapidly increases with
and replaced by a suitable compensation function, to trade-off n, resulting impractical in most applications.
accuracy with hardware cost. As more columns are eliminated, VARIABLE CORRECTION METHOD
the area and power consumption of the arithmetic unit are

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International Journal of Scientific and Research Publications, Volume 3, Issue 3, March 2013 2
ISSN 2250-3153

The basic design of the multiplier is the same as that of a n

constant correction fixed width multiplier. The least significant A a 2
i 1
i
i
--------- (6)
N-2 partial product columns of a full width multiplier are
truncated. The partial product terms in the N- 1 n

column are then added to the partial product terms in the Nth
B b j 1
j 2 j
----------- (7)
column using full-adders. This is done in order to offset the error
introduced due to truncation of least significant N- 2columns. n
P  AB   pi 2 i ------------ (8)
The correction term that is generated is based on the following i 1
arguments, Fig.1 shows the block diagram of standard 8x8 multiplier. Fig. 2
1) The biggest column in the entire partial product array of a full- shows the architecture of standard 8×8-bitparallel multiplier,
width multiplier is the Nthcolumn. where HA and FA are the half and full adders respectively.
2) The Nth column contributes more information to the most
significant N-1 columns than the rest of the least significant N-1 III. FPGA DESIGN AND IMPLEMENTATION RESULTS
columns. The information presented could be made more
accurate if the carry from the N- 1th column is preserved and The design of standard and truncated 8×8 bit multipliers are
passed onto the Nth column. done using VHDL and implemented in a Xilinx Spartan 3AN
3) Adding the elements in N- 1th column to the Nth column XC3S700AN (package: fgg484, speed grade: -5) FPGA using the
provides a variable correction as the information presented is Xilinx ISE 9.1i design tool. Fig. 1 shows the block diagram of
dependent on input bits. When all the partial product terms in the standard multiplier. The internal RTL schematic of the standard
N-1th column are zero, the correction added is zero. When all the 8x8 multipliers shown in fig.3.The behavioural simulation
terms are one, a different correction value is added. presents the utilization of MSB as the required value in
The accuracy of truncated multipliers can be significantly truncated multiplier for example,
improved using variable correction truncated multipliers that 255x255=(65025)10=(1111111000000001)2=(11111110)2 =(254)
compensate the effect of the dropped terms with a non constant 10 is obtained in the simulation result of truncated multiplier.
compensation function. The multiplier output is computed as:

PVCM = truncn (SMSP + SLSP major + f (IC) + Kround)--(2)

where f (IC) is a suitable compensation function.

The objective of this paper is to present a comparative study of

variable truncated and standard multiplier by implementing the
8×8-bit respective multiplier using Spartan-3AN FPGA device.
This paper is organized as follows. In section II, the
mathematical basis of truncated multiplication is briefly
discussed. Section III presents the FPGA design and
implementation results and finally conclusion is provided in Fig.1 Block dig. of standard 8x8 multiplier
section IV.
II.MATHEMATICAL BASIS OFTRUNCATED MULTIPLIER Fig.4 shows the block diagram of truncated 8x8 multiplier.Fig.5
shows the architecture of truncated 8x8 multiplier. The internal
Considering the multiplication of two n-bit inputs A and B, a RTL schematic of truncated 8x8 multiplier is shown in fig.6.The
standard multiplier performs the following operations to obtain total equivalent gate count in case of standard 8x8 multiplier is
the 2n bit product P. 702 and that is improved to 456 using truncated 8x8 multiplier.
n
A   ai 2 i
The power consumption incase of standard 8x8 multiplier is
--------- (3) 419mW and that is also improved to 156mW using truncated 8x8
i 1
n multiplier. The number of occupied slices used in truncated
B   b j 2 j ----------- (4) multiplier is also improved. In case of standard 8x8 multiplier it
j 1 is 60 and in truncated 8x8 multiplier it is 42.
2n n n
--- (5) P   pi 2i   Ai B j 2i  j
i 1 i 1 j 1

where ai,bi and Pi represent the ith bit of A, B and P,

respectively. The output of the 8x8 truncated multiplier can be
written as below.

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International Journal of Scientific and Research Publications, Volume 3, Issue 3, March 2013 3
ISSN 2250-3153

Fig.2 Architecture of 8x8 standard multiplier.

Fig.3 RTL schematic of standard 8x8 multiplier.

Fig.5 Architecture of truncated 8x8 multiplier.

Fig.4 Block dig. of truncated 8x8 multiplier.

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International Journal of Scientific and Research Publications, Volume 3, Issue 3, March 2013 4
ISSN 2250-3153

CONCLUSION

In this paper we have presented hardware design and

implementation of FPGA based parallel architecture for standard
and truncated 8x8 multipliers utilizing VHDL. Both the design
were implemented on Xilinx Spartan 3AN XC3S700AN FPGA
device. The aim is to present a comparative study of the standard
and truncated 8x8 multipliers. The truncated multiplier as
compared to standard multiplier shows much more reduction in
device Utilization. The power consumption of standard 8x8
multiplier is 419mW and that to truncated 8x8 multiplier power
consumption is only 156 mW. The truncated 8x8 multiplier uses
only 42 slices out of 2352 slices. Truncated multiplication
provides an efficient method for reducing the power dissipation
and area of parallel multipliers.

ACKNOWLEDGMENT
The satisfaction that accompanies a successful completion of any
task would be incomplete without the mention of people, whose
constant guidance and encouragement crowned the efforts with
success. I express my heartfelt thanks to my guide Ms. Sharda
G.Mungle for providing me an opportunity and excellent
Fig.6 RTL Schematic of truncated 8x8 multiplier. environment to carry out my work under her..I would like to
further extend my heartfelt thanks to the HOD Electronics
engg.dept.KITS,Ramtek.

REFERENCES
TABLE I
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FPGA RESOURCE UTILIZATION FOR STANDARD AND width standard and truncated 6×6-bitmultipliers: A comparative
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TestWorkshop, Nov. 15-17, IEEE Xplore Press,Riyadh, Saudi
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[2] Rais, M.H., 2010a. Hardware implementation oftruncated
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Am. J. Eng. Applied Sci., 3:201-206. DOI:
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10.3844/ajeassp.2010.201.206.
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[5] Rais, M.H., 2009b. “Efficient hardware realization of
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AUTHORS
First Author –Suresh R.Rijal, Asst.Prof.KITS, Ramtek
[email protected]
Second Author – Ms.Sharda G. Mungale, Asst.Prof.PCEA,
Nagpur [email protected]

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International Journal of Scientific and Research Publications, Volume 3, Issue 3, March 2013 5
ISSN 2250-3153

SIMULATION RESULTS OF STANDARD AND TRUNCATED MULTIPLIERS

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