Coa Bcs352 Lab-6
Coa Bcs352 Lab-6
Coa Bcs352 Lab-6
APJ
GL BAJAJ
Institute of Technology & Management
Abdul Kalam Technical University, Lucknow, U.P., India]
Department of Computer Sc. & Engineering (AI)
Greater Noida
Experiment No.:6
Theory: -
Flip-flop
The memory elements in a sequential circuit are called flip-flops. A flip-flop circuit has two outputs, one
for the normal value and one for the complement value of the stored bit. Binary information can enter a
flip-flop in a variety of ways and gives rise to different types of flip-flops
SR flip-flop
The clocked SR flip-flop shown in Figure consists of a basic NOR flip-flop and two AND gates. The
outputs of the two AND gates remain at 0 as long as the clock pulse (or CP) is 0, regardless of the S and
R input values. When the clock pulse goes to 1, information from the S and R inputs passes through to
the basic flip-flop. With both S=1 and R=1, the occurrence of a clock pulse causes both outputs to
momentarily go to 0. When the pulse is removed, the state of the flip-flop is indeterminate, ie., either
state may result, depending on whether the set or reset input of the flip-flop remains a 1 longer than the
transition to 0 at the end of the pulse.
Q(t) Q(t+1) S R
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0
D- FLIP FLOP: - To avoid the forbidden case that occur in R-S Flip Flop. When R=S=1, DFlip Flop
is implemented, in the D Flip Flop. There is only one output. We can transmit the value of D at the output
the Flip Flop when CLK in high.
The D flip-flop is a modification of the clocked SR flip-flop. The D input goes directly into the S
input and the complement of the D input goes to the R input. The D input is sampled during the occurrence
of a clock pulse. If it is 1, the flip-flop is switched to the set state (unless it was already set). If it is 0, the
[Approved by AICTE, Govt. of India & Affiliated to Dr. APJ
GL BAJAJ
Institute of Technology & Management
Abdul Kalam Technical University, Lucknow, U.P., India]
Department of Computer Sc. & Engineering (AI)
Greater Noida
Q(t) Q(t+1) D
0 0 0
0 1 1
1 0 0
1 1 1
Excitation Table
Transition table
JK Flip-Flop
A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate state of the SR type is
defined in the JK type. Inputs J and K behave like inputs S and R to set and clear the flip-flop (note that
in a JK flip-flop, the letter J is for set and the letter K is for clear). When logic 1 inputs are applied to
both J and K simultaneously, the flip-flop switches to its complement state, i.e., if Q=1, it switches to
Q=0 and vice versa.
A clocked JK flip-flop is shown in Figure; Output Q is ANDed with K and CP inputs so that the flip-
flop is cleared during a clock pulse only if Q was previously 1. Similarly, output Q' is ANDed with J and
CP inputs so that the flip-flop is set with a clock pulse only if Q' was previously 1.
Q(t) Q(t+1) J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
[Approved by AICTE, Govt. of India & Affiliated to Dr. APJ
GL BAJAJ
Institute of Technology & Management
Abdul Kalam Technical University, Lucknow, U.P., India]
Department of Computer Sc. & Engineering (AI)
Greater Noida
T Flip-Flop
The T flip-flop is a single input version of the JK flip-flop. As shown in Figure, the T flip-flop is
obtained from the JK type if both inputs are tied together. The output of the T flip-flop "toggles" with
each clock pulse.
Q(t) Q(t+1) T
0 0 0
0 1 1 (b) Excitation Table
1 0 1
1 1 0
OUTPUT:
VIVA QUESTIONS
1. One example of the use of an S-R flip-flop is …?
2. The truth table for an S-R flip-flop has how many VALID entries?
4. A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?