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COUNTER

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7 views2 pages

COUNTER

Uploaded by

random help
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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module syn_counter(

input clk,
input reset,
input up_down,
output [3:0] counter
);
wire [3:0] d;
wire [3:0] q;

// Instantiate D flip-flops for each bit of the counter


d_flip_flop dff0 (.clk(clk), .reset(reset), .d(d[0]), .q(q[0]));
d_flip_flop dff1 (.clk(clk), .reset(reset), .d(d[1]), .q(q[1]));
d_flip_flop dff2 (.clk(clk), .reset(reset), .d(d[2]), .q(q[2]));
d_flip_flop dff3 (.clk(clk), .reset(reset), .d(d[3]), .q(q[3]));

// Connect the output


assign counter = q;

// Next state logic for up/down counter


assign d = up_down ? (q - 4'b0001) : (q + 4'b0001); // Decrement if up_down=1,
increment if up_down=0

endmodule

`timescale 1ns / 1ps

module tb_up_down_counter_structural;
reg clk;
reg reset;
reg up_down;
wire [3:0] counter;

// Instantiate the up-down counter


syn_counter uut (
.clk(clk),
.reset(reset),
.up_down(up_down),
.counter(counter)
);

// Clock generation with a period of 10 time units


always #5 clk = ~clk;

initial begin
// Initialize signals
clk = 0;
reset = 1;
up_down = 0;
// Apply reset for 10 time units
#10 reset = 0;

// Test counting up
up_down = 0;
#100; // Let counter increment for 100 time units

// Test counting down


up_down = 1;
#100; // Let counter decrement for 100 time units

// End simulation
$stop;
end

// Monitor the counter value, up_down, reset, and clk for debugging
initial begin
$monitor("Time = %0t | Counter = %b | Up_Down = %b | Reset = %b | CLK =
%b", $time, counter, up_down, reset, clk);
end
endmodule

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