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USR

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7 views3 pages

USR

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random help
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© © All Rights Reserved
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module UniversalShiftRegister_4bit (

input clk, // Clock signal


input reset, // Asynchronous reset signal
input [2:0] control, // Control word input (3 bits)
input serial_in_left, // Serial input for left shifting
input serial_in_right, // Serial input for right shifting
input [3:0] parallel_in, // Parallel input data (4 bits)
output reg [3:0] data_out // 4-bit Output data
);

always @(posedge clk or posedge reset) begin


if (reset) begin
data_out <= 4'b0000; // Reset the register to 0
end
else begin
case (control)
3'b000: data_out <= data_out; // No
operation
3'b001: data_out <= {data_out[2:0], serial_in_left}; // SISO (left
shift with serial input)
3'b010: data_out <= {serial_in_right, data_out[3:1]};// SISO (right
shift with serial input)
3'b011: data_out <= {data_out[2:0], serial_in_left}; // SIPO (left
shift with serial input)
3'b100: data_out <= {serial_in_right, data_out[3:1]};// SIPO (right
shift with serial input)
3'b101: data_out <= {parallel_in[3], data_out[3:1]}; // PISO
(parallel-in, left-out)
3'b110: data_out <= {data_out[2:0], parallel_in[0]}; // PISO
(parallel-in, right-out)
3'b111: data_out <= parallel_in; // PIPO
(parallel load)
default: data_out <= data_out; // Default
case (no operation)
endcase
end
end
endmodule

module tb_UniversalShiftRegister_4bit;
reg clk;
reg reset;
reg [2:0] control;
reg serial_in_left;
reg serial_in_right;
reg [3:0] parallel_in;
wire [3:0] data_out;

// Instantiate the Universal Shift Register


UniversalShiftRegister_4bit uut (
.clk(clk),
.reset(reset),
.control(control),
.serial_in_left(serial_in_left),
.serial_in_right(serial_in_right),
.parallel_in(parallel_in),
.data_out(data_out)
);

// Clock generation
always #5 clk = ~clk;

initial begin
// Initialize inputs
clk = 0;
reset = 1;
control = 3'b000;
serial_in_left = 1;
serial_in_right = 0;
parallel_in = 4'b1010;

// Reset the register


#10 reset = 0;

// Test parallel load (PIPO)


control = 3'b111;
#10;

// Test left shift (SISO with serial input from the left)
control = 3'b001;
serial_in_left = 1;
#10;

// Test right shift (SISO with serial input from the right)
control = 3'b010;
serial_in_right = 0;
#10;

// Test parallel-in, left-out (PISO)


control = 3'b101;
#10;

// Test parallel-in, right-out (PISO)


control = 3'b110;
#10;

// Complete simulation
$stop;
end

initial begin
$monitor("Time = %0t | Control = %b | Data_out = %b | Serial_in_left = %b |
Serial_in_right = %b | Parallel_in = %b",
$time, control, data_out, serial_in_left, serial_in_right,
parallel_in);
end
endmodule

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