UNIT – III

BIPOLAR JUNCTION &, FIELD-EFFECT TRANSISTORS

INTRODUCTION
 The transistor was developed by Dr.Shockley along with Bell Laboratories team in 1951

 The transistor is a main building block of all modern electronic systems

 It is a three terminal device whose output current, voltage and power are controlled by its
input current

 In communication systems it is the primary component in the amplifier

 An amplifier is a circuit that is used to increase the strength of an ac signal

 Basically, there are two types of transistors

 Bipolar junction transistor

 Field effect transistor

 The important property of the transistor is that it can raise the strength of a weak signal

 This property is called amplification

 Transistors are used in digital computers, satellites, mobile phones and other communication
systems, control systems etc.,

 A transistor consists of two P-N junctions

 The junction are formed by sand witching either p-type or n-type

semiconductor layers between a pair of opposite types which is shown below

Fig: transistor

TRANSISTOR CONSTRUCTION

 A transistor has three regions known as emitter, base and collector

 Emitter: it is a region situated in one side of a transistor, which supplies charge carriers
(ie., electrons and holes) to the other two regions

 Emitter is heavily doped region

 Base: It is the middle region that forms two P-N junction in the transistor
  The base of the transistor is thin as compared to the emitter and is a lightly doped region

 Collector: It is a region situated in the other side of a transistor (ie., side opposite to the
emitter) which collects the charge carriers

 The collector of the transistor is always larger than the emitter and base of a transistor

 The doping level of the collector is intermediate between the heavy doping of emitter and
the light doping of the base

TRANSISTOR SYMBOLS

 The transistor symbol carries an arrow head in the emitter pointing from the P- region towards
the N- region

 The arrow head indicates the direction of a conventional current flow in a transistor

 The direction of arrow heads at the emitter in NPN and PNP transistor is opposite to each
other

 The PNP transistor is a complement of the NPN transistor

 In NPN transistor the majority carriers are free electrons, while in PNP
transistor these are the holes

UNBIASED TRANSISTORS

 A transistor with three terminals (Emitter, Base, Collector) left open is called an unbiased
transistor or an open – circuited transistor

 The diffusion of free electrons across the junction produces two depletion layers

 The barrier potential of three layers is approximately 0.7v for silicon transistor and 0.3v for
germanium transistor

 Since the regions have different doping levels therefore the layers do not have the same width

 The emitter base depletion layer penetrates slightly into the emitter as it is a heavily doped
region where as it penetrates deeply into the base as it is a lightly doped region

 Similarly, the collector- base depletion layer penetrates more into the base region and less into
the collector region

 The emitter- base depletion layer width is smaller than the that of collector base depletion
layer

 The unbiased transistor is never used in actual practice. Because of this we went for transistor
 biasing

OPERATION OF NPN TRANSISTOR

 The NPN transistor is biased in forward active mode ie., emitter – base of
transistor is forward biased and collector base junction is reverse biased

 The emitter – base junction is forward biased only if V is greater than barrier potential which is
0.7v for silicon and 0.3v for germanium transistor

 The forward bias on the emitter- base junction causes the free electrons in the N –type emitter to
flow towards the base region. This constitutes the emitter current. Direction of conventional current
is opposite to the flow of electrons

 Electrons after reaching the base region tend to combine with the holes

 If these free electrons combine with holes in the base, they constitute base current ().

 Most of the free electrons do not combine with the holes in the base

 This is because of the fact that the base and the width is made extremely small and electrons do
not get sufficient holes for recombination

 Thus, most of the electrons will diffuse to the collector region and constitutes collector current.
This collector current is also called injected current, because of this current is produced due to
electrons injected from the emitter region

 There is another component of collector current due to the thermal generated carriers.

 This is called as reverse saturation current and is quite small

OPERATION OF PNP TRANSISTOR
 

 Operation of a PNP transistor is similar to npn transistor

 The current within the PNP transistor is due to the movement of holes whereas, in an NPN
transistor it is due to the movement of free electrons

 In PNP transistor, its emitter – base junction is forward biased and collector base junction is
reverse biased.

 The forward bias on the emitter – base junction causes the holes in the emitter region to
flow towards the base region

 This constitutes the emitter current ( IE).

 The holes after reaching the base region, combine with the electrons in the base and constitutes
base current.

 Most of the holes do not combine with the electrons in the base region

 This is due to the fact that base width is made extremely small, and holes does not get
sufficient electrons for recombination.

 Thus, most of the holes diffuse to the collector region and constitutes collector region

 This current is called injected current, because it is produced due to the holes injected from
the emitter region

 There is small component of collector current due to the thermally generated carriers

 This is called reverse saturation current.

TRANSISTOR CURRENTS

 We know that direction of conventional current is always opposite to the electron current in
any electronic device.

 However, the direction of a conventional current is same as that of a hole current in a PNP
transistor

 Emitter current

 Base current

 Collector current
  Since the base current is very small

TRANSISTOR CONFIGURATIONS

 A transistor is a three terminal device, but we require four terminals ( two for input and two for
output) for connecting it in a circuit.

 Hence one of the terminal is made common to the input and output circuits.

 The common terminal is grounded

 There are three types of configuration for the operation of a transistor

 Common base configuration (CB)

 This is also called grounded base configuration

 In this configuration emitter is the input terminal, collector is the output terminal
and base is the common terminal

 Common emitter configuration (CE)

 This is also called grounded emitter configuration

 In this configuration base is the input terminal, collector is the output terminal
and emitter is the common terminal

 Common collector configuration (CC)

 This is also called grounded collector configuration

 In this configuration, base is the input terminal, emitter is the output terminal
and collector is the common terminal.
 Common base configuration (CB)

 The input is connected between emitter and base and output is connected across
collector and base

 The emitter – base junction is forward biased and collector – base junction is reverse
 biased.

 The emitter current, flows in the input circuit and the collector current flows in
the output circuit.

 The ratio of the collector current to the emitter current is called current
amplification factor.

 If there is no input ac signal, then the ratio of collector current to emitter current
is called dc alpha

 The ratio of change in the collector current to change in the emitter current is known
as ac alpha
= Common-emitter current gain = Common-base current gain

= IC = IC

IB IE

 The input characteristics look like the characteristics of a forward-biased diode.

Note that VBE varies only slightly, so we often ignore these characteristics and
assume:
 Common approximation: VBE = Vo = 0.65 to 0.7V

 The higher the value of better the transistor. It can be increased by making the
base thin and lightly doped

 The collector current consists of two parts transistor action. Ie., component
depending upon the emitter current , which is produced by majority carriers

 The leakage current due to the movement of the minority carriers across base
collector junction

CHARACTERISTICS OF CB CONFIGURATION

 The performance of transistors determined from their characteristic curves that relate different
d.c currents and voltages of a transistor
 Such curves are known as static characteristics curves
 There are two important characteristics of a transistor
 Input characteristics
 Output characteristics
INPUT CHARACTERISTICS

 The curve drawn between emitter current and emitter – base voltage for a given value
of collector – base voltage is known as input characteristics

Base width modulation (or) Early effect

 In a transistor, since the emitter – base junction is forward biased there is

no effect on the width of the depletion region
 However, since collector – base junction is reverse biased as the reverse bias
voltage across the collector – base junction increase the width of the depletion region
also increases
 Since the base is lightly doped the depletion region penetrates deeper into the base
region
 This reduces the effective width of the base region
 This variation or modulation of the effective base width by the collector voltage is
known as base width modulation or early effect

 The decrease in base width by the collector voltage has the following three effects
 It reduces the chances of recombination of electrons with the holes in the base region
Hence current gain increases with increase in collector – base voltage

 The concentration gradient of minority carriers within the base increases. This
increases the emitter current
 For extremely collector voltage , the effective base width may be reduced to zero,
resulting in voltage breakdown of a transistor
 This phenomenon is known as punch through
 The emitter current increases rapidly with small increase in which means low
input resistance
 Because input resistance of a transistor is the reciprocal of the slope of the input
characteristics

Output characteristics

 The curve drawn between collector current and collector – base voltage, for a given value
of emitter current is known as output characteristics

ACTIVE REGION

 There is a very small increase in IE with increase in IC

 This is because the increase in IE expands the collector – base depletion region and
shorten the distance between two depletion region
 Hence due to the early effect does not increase very much with increase in
 Although, the collector current is independent of it is increased beyond a certain value,
eventually increases rapidly because of avalanche effects
 This condition is called punch – through or reach – through
 When it occurs, large current can flow destroying the device
 CUT – OFF REGION
 small collector current flows even when emitter current
 this is the collector leakage current

SATURATION REGION
 collector current flows even when the external applied voltage is reduced to zero. There is a low
barrier potential existing at the collector – base junction and this assists in the flow of collector
current

(II) COMMON – EMITTER CONFIGURATION

 The input is connected between base and emitter, while output is connected between collector and
emitter
 Emitter us common to both input and output circuits.

 The bias voltage applied are VCE and VBE

 The emitter-base junction is forward biased and collector-emitter junction is reverse biased.
 The base current IB flows in the input circuit and collector current Ic flows sin the output circuit.
 CE is commonly used because its current, Voltage, Power gain are quite high and output to
input impedance ratio is moderate
 The rate of change in collector current to change in base current is called amplification
factor B.
 The current gain in the common-emitter circuit is called BETA (b). Beta is the relationship of
collector current (output current) to base current (input current).

 Two voltages are applied respectively to the base and collector with respect to the common
emitter

 Same as the CB configuration, here in the CE configuration, the BE junction is forward biased
while the CB junction is reverse biased. The voltages of CB and CE configurations are related
by:

 The base current is treated as the input current, and the collector current is treated as the output
current:

 Solving this equation for collector current, we get the relationship between the output collector
current and the input base current:

 Here we have also defined the CE current gain or current transfer ratio
  which is approximately the ratio of the output current and the input current . The two
parameters α and β are related by:

Characteristics of CE configuration

i) Input Characteristics

 Same as in the case of common-base configuration, the junction of the common-emitter

configuration can also be considered as a forward biased diode, the current-voltage
characteristics is similar to that of a diode:

 The Curve drawn between base current and base-emitter voltage for a given value of collector-
emitter voltage is known as input characteristics.

 The input characteristics of CE transistors are similar to those of a forward biased diode because
the base-emitter region of the transistor is forward-biased.
 Input Resistance i s larger in CE configuration than in CB configuration.
This is because the I/P current increases less rapidly with increase in Vbe.
 An increment in value of VCE causes the input current to be lower for a given level of VBE.
 This is explained on the basis of early effect.
 As a result of early effect, more charge carriers from the emitter flows across the
collector-base junction and flow out through the based lead.

Output Characteristics
  It is the curve drawn between collector current Ic and collector-emitter voltage VCE for a
given value of base current Ib.

 The collector current Ic varies with VCE and becomes a constant.

 Output characteristics in CE configuration has some slope while CB configuration has
almost horizontal characteristics.
 This indicates that output resistance in case of CE configuration is less than that in CB
configuration.

Active Region

 For small values of base current, the effect of collector voltage Vc over Ic is small but for large
values of Ib, this effect increases.
 The shape of the characteristic is same as CB configuration
 The difference that Ic is larger than input current
 Thus, the current gain is greater than unity.

Saturation Region

 With low values of VCE, the transistor is said to be operated in saturation region and in this region,
base current IB does not correspond to Ic,

Cut off Region

 A small amount of collector current Ic flows even when Ib=0, This is called emitter leakage
current.

If the transistor is not biased properly, it would work inefficiently and produce distortion
in output signal.

Transistor as a Amplifier

Transistors are can be configured in three different ways depending on whether the common terminal b/w
the input and output ports is base, collector or emitter and are named common base (CB), common
collector(CC) and common emitter(CE), accordingly.

These can be used as switches or amplifiers based on the choice of OPERATING POINT AND REGION
OF OPERATION. For switching the transistor circuits when made to operate between cut-off and
saturation regions and for amplifiers when made to operate in their active region.

In addition, it is to be kept in mind that the transistors are inherently nothing but the current-controlled
devices wherein a small change in the base current, IB results in a large variation in the collector current,
IC
(IE=IB+IC) .
Figure shows a simple common emitter circuit which uses an npn transistor whose
 Collector terminal (output terminal) is connected to supply voltage VCC through the collector resistor
RC.
 Base terminal is provided with the AC signal which needs to be amplified.
 Emitter terminal is grounded (hence also referred to as Grounded Emitter configuration).

1). For 1st half of input signal, as the inputi voltage V increases, the base current I also increases which
in turn increases the collector current IC. B
This causes an increase in the voltage drop across the collector resistor, RC which results in a decreased
output voltage V0 as emphasized by the following relationship

2). For the 2nd half of the input signal the input voltage goes on
B decreasing, I and hence I decrease, due

to which the voltage drop across RC also decreases thereby increasing

C the output voltage.
3). Thus, for the positive half-cycle of the input waveform, one would get amplified negative half-cycle
while for the negative input signal, the output would be a amplified positive pulse. Hence there exists a
phase-shift of 180o between the input and the output waveforms of the common emitter amplifier (also
called as inverting amplifier).

Faithful, Undistorted or practical amplifier

However, in order to obtain an faithful(undistorted) amplification gain the transistor needs to be biased
properly by setting a suitable operating point (Q-point). This indicates that practically one has to resort to

a stable network (Figure 2)

which will be resistant to the changes in temperature and other transistor parameters.
CONSTRUCTION

1).The resistors R1 and R2 are used to provide bias for the base of the transistor (voltage-divider transistor
biasing)
 2). The emitter resistor RE is used to ensure that proper DC conditions are maintained for the circuit by
regulating the amount of DC feedback.

3). The capacitors Ci and Co which are the decoupling capacitors used to provide AC coupling between the
amplifier stages or blocks the DC from entering or leaving the ckt. The values of these capacitances are
chosen to such that they provide negligible reactance at the frequency of operation.

4). The emitter bypass capacitor CE when added into the circuit, increases its gain considerably by short-
circuiting the emitter resistance RE for high frequency signals, which results in the reduction of the overall
transistor load. OPTIONAL (The value of this CE is chosen such that the capacitor offers a reactance value
which is equal to the 1/10th of RE at the lowest operating frequency.)

Mathematical expression β=gain factor for CE mode and AV is Voltage gain.

These common emitter amplifiers are most widely used, say for example as low noise amplifiers and
radio frequency amplifiers, as they offer medium input resistance, medium output resistance, medium
voltage gain, medium current gain and high power gain.

Principle and working of Hartley oscillator

The Hartley oscillator is an electronic circuit that generates an oscillatory output by using a tuned LC
circuit and an amplifier. The principle of the Hartley oscillator is based on the following:
 LC circuit

The tuned LC circuit is made up of capacitors and inductors. The circuit's oscillation frequency is
determined by the values of the inductor and capacitor.
 Feedback
A portion of the signal from the collector or drain is coupled to the base or gate of an active device, such
as a transistor or vacuum tube, to produce feedback.
 Phase shift
The common emitter or common source amplifier provides a phase shift of 180°. The LC feedback
network provides an additional 180° phase shift at the resonant frequency, resulting in a total phase shift
of 360°.
Oscillation
The oscillation occurs at the frequency where the total phase shift is 360°.
LC oscillator:
 The oscillators which use the elements L and C to produce the oscillations arecalled LC
oscillators.
 The circuit using elements L and C is called tank circuit or oscillatory circuit,which is an
important part of LC oscillators.
 These oscillators are used for high frequency range from 00 kHz up to few GHz.
 The LC tank circuit consists of elements L and C connected in parallel

Figure Operation of LC tank circuit

[Source: Microelectronics by J. Millman and A. Grabel, Page-395]

 The energy keeps oscillating between electric potential energy and magnetic fieldenergy
 The capacitor stores energy in the form of an electrostatic field and which produces a potential
(static voltage) across its plates, while the inductive coil stores its energy in the form of an
electromagnetic field.
 The capacitor is charged up to the DC supply voltage, V by putting the switch in position 1.
 When the capacitor is fully charged the switch changes to position 2.
 The charged capacitor is now connected in parallel across the inductive coil sothe capacitor
begins to discharge itself through the coil.
 The voltage across C starts falling as the current through the coil begins to rise. This rising
current sets up an electromagnetic field around the coil whichresists this flow of current.
 When the capacitor, C is completely discharged the energy that was
originally stored in the capacitor, C as an electrostatic filed is now stored in the inductive
coil, L as an electromagnetic field around the coils windings.
 As there is now no external voltage in the circuit to maintain the currentwithin the
coil, it starts to fall as the electromagnetic field begins to collapse. A back emf is induced in
the coil (e=-Ldi/dt) keeping the current flowing in the original direction. This current now
charges up the capacitor, c with the opposite polarity to its original charge.
 Capacitor continues to charge up until the current reduces to zero and the electromagnetic
field ofthe coil has collapsed completely.
 The capacitor now starts to discharge again back through the coil and the whole process so
repeated.
  The polarity of the voltage changes as the energy is passed back and forth between the
capacitor and inductor producing an AC type sinusoidal voltage and current waveform.
 The frequency of oscillations generated by LC tank circuit depends on the values L and C is
given by,
1
ƒ=
2𝜋√𝐿𝐶
Hartley Oscillator:

 A LC oscillator which uses two inductive reactance and one capacitivereactance in its
feedback network is called Hartley oscillator.

Figure. Hartley oscillator

  CE amplifier provides a phase shift of 1800 and LC feedback network provides additional 1800
phase shift.
 The resistance R1 and R2 are the biasing resistances. The RFC is the radio frequency choke.
 Its reactance value is very high frequencies; hence it can be treated as open circuit. While for d.c
conditions, the reactance is zero hence cause no problem for d.c capacitors.
 Hence due to RFC, the isolation between a.c. and d.c operation is achieved.

Principle and working of RC phase shift oscillator

The principle of an RC phase shift oscillator is to generate a 360° phase shift in order to produce positive
feedback and a sine wave output:
 Phase shift

The RC phase shift oscillator uses a network of resistors and capacitors to generate a 180° phase shift, and an
op-amp to generate another 180° phase shift. This results in a total phase shift of 360°, which means the input
and output signals are in-phase.
 Feedback
The feedback network shifts the phase of the amplifier output by 180° at the oscillation frequency to give
positive feedback.
 Configuration
The RC phase shift oscillator uses a common emitter configuration of a transistor.

Frequency
The RC phase shift oscillator has a fixed frequency and is used at lower frequencies.

R-C Phase shift Oscillator

RC phase shift oscillator basically consists of an amplifier and a feedback network consisting of
resistor and capacitors arranged in ladder fashion. Hence such an oscillator is also called ladder
type RC phase shift oscillator.
RC network is used in feedback path. In oscillator, feedback network must introduce a phase shift
of 1800 to obtain total phase shift around a loop as 3600

Thus, if one RC network produces phase shift of φ=600 then to produce phase shift of 1800 such
three RC networks must be connected in cascade.
Hence in RC phase shift oscillator, the feedback network consists of three RC sections each
producing a phase shift of 600, thus total phase shift due to feedback is 1800.
Transistorized RC phase shift oscillator, a transistor is used as an active device element of the
amplifier.
 Figure: RC phase shift oscillator
Fig shows a practical transistorized RC phase shift oscillator which uses a common
emitter single stage amplifier and a phase shifting network consisting of three
identical RC sections.
The output of the feedback network gets loaded due to the low input impedanceof
a transistor. Hence an emitter follower input stage before the common emitter
amplifier stage can be used, to avoid the problem of low input impedance.
But if only single stage is to be used then the voltage shunt feedback, denoted by
resistance R3 in the figure is used, connected in series with the amplifier input
resistance.
A phase shifting network is a feedback network, so output of the amplifier is given
as an input to the feedback network.
While the output of the feedback network is given as an input to the amplifier. Thus,
amplifier supplies its own input, through the feedback network. Neglecting R1 and R 2
as these are sufficiently
Advantages of RC Phase Shift Oscillator

• The advantages of R-C phase shift oscillator are,

1. The circuit is simple to design.

2. Can produce output over audio frequency range.

3. Produces sinusoidal output waveform.

4. It is a fixed frequency oscillator.

Disadvantages of RC Phase Shift Oscillator

1. To vary the frequency, values of R and C of all three sections are to be varied simultaneously which
is practically difficult. Hence frequency cannot be varied.

2. Frequency stability is poor due to changes in the values of various components due to effect of
temperature, aging etc.
JFET

JFET is a unipolar-transistor, which acts as a voltage controlled current device

and is a device in which current at two electrodes is controlled by the action of an electric field at
a p-n junction. A JFET, or junction field-effect transistor, or JUGFET, is a FET in which the gate
is created by reverse-biased junction (as opposed to the MOSFET which creates a junction via a
field generated by conductive gate, separated from the gate region by a thin insulator).

Construction
n-channel JFET
The figure shows construction and symbol of n-channel JFET. A small bar of extrinsic
semiconductor material, n type is taken and its two ends, two ohmic contacts are made which is
the drain and source terminals of FET. Heavily doped electrodes of p type material form p-n
junctions on each side of the bar. The thin region between the two p gates is called the channel.
Since this channel is in the n type bar, the FET is known as n-channel JFET. The electrons enter
the channel through the terminal called source and leave through the terminal called drain. The
terminals taken out from heavily doped electronics of p type material are called gates. These
electrodes are connected together and only one terminal is taken out, which is called gate, as
shown in the figure.
p-channel JFET
The device could be made of p type bar with two n type gates as shown in the figure. This
will be p-channel JFET. The principle of working of n-channel JFET and p- channel JFET are
similar. The only difference being that in n-channel JFET the current is carried by electrons
while in p-channel JFET, it is carried by holes.

Operation
In JFET, the p-n junction between gate and source is always kept in reverse biased
conditions. Since the current in a reverse biased p-n junction is extremely small, practically zero.
The gate current in JFET is often neglected and assumed to be zero.

Let us consider the circuit in the figure, voltage V DD is applied between drain and source.
Gate terminal is kept open. The bar is of n-type material. Due to the polarities of applied voltage
as shown in the fig, the majority carriers i.e. the electrons start flowing from the source to the
drain. The flow of electrons makes the drain current, ID.
 The majority carriers move from source to drain through the space between the gate
regions. The space is commonly known as channel. The width of this channel can be controlled
by varying the gate voltage. To see the effect of gate voltage on channel- width and on drain
current ID, consider the diagram below.

The figure (a) shows that an n-channel JFET with the gate directly connected to the
source terminal. When drain voltage VDS is applied, a drain current ID flows in the direction
shown. Since the n-material is resistive, the drain current causes a voltage drop along the
channel. This voltage drop reverse biases the pn junctions, and causes the depletion regions to
penetrate into the channel. Since gate is heavily doped and the channel is lightly doped the width
of the depletion region will mainly be spread in the channel as shown in fig (a). This penetration
depends on the reverse bias voltage.

From the fig it can be observed that depletion region width is more at the drain side as compared
to source side because near the junction, voltage at drain side is more than the voltage at the
source side. This shows that reverse bias is not uniform near the junction as it gradually increases
from source side to drain side.
The depletion region does not contain charge carriers. The space between two depletion
regions is available for conducting portion of the channel. When reverse bias voltage is applied
externally to the gate, the reverse bias will increase and hence increase the penetration of the
depletion region which reduces the width of the conducting portion of the channel. When the
width of the conducting portion of the channel reduces, the no. of electrons flowing from source
to drain reduces and hence the current flowing from drain to source reduces.
When the external reverse bias voltage at the gate is increased as shown in fig
(b) & (c) the depletion regions will increase more and at a particular stage the width of the
depletion region will be equal to the original width of the depletion regions will increase more
and more, and stage will come when the width of the depletion regions will be equal to the
original width of the channel, leaving zero width for conducting portion of the channel, as shown
in the fig (c). This will prevent any current flow from drain to source and this will cut off the
drain current. The gate to source voltage that produces cutoff is known as cutoff voltage (V GS
(OFF)).

When the gate is shorted to source, there is minimum reverse bias between gate and
source p-n junction, making depletion region width minimum and conducting channel width
maximum. In this case maximum drain current flows which is designated by IDSS and this is the
possible drain current in JFET. It is clear that the gate to source voltage controls the current
flowing through the channel and hence FET is also called voltage controlled current source.
Characteristics
Drain (or) current voltage characteristics of JFET
The current voltage characteristics of an n-channel JFET is shown in the figure. The drain
current (ID) is plotted with VDS for different values of VGS. This characteristic is also known as
drain characteristics of JFET. From the fig, we see that as the voltage increased from 0 to a few
volts, the current increases as determined by ohm’s law. The straight nature of the curve at low
values for VDS reveals that for this region the resistance is essentially constant for a fixed valued
of VGS. But the slope of the ID - VDS curve near the origin is a function of the gate voltage. This
region of operation is known as the linear region or ohmic region. As VDS increases and
approaches a value VP (referred to as pinch – off voltage), slope of the curve changes and the
channel resistance increases. If VDS increases beyond pinch-off value, characteristics curve
becomes more horizontal and ID maintains a saturation level. For VGS = 0v , the saturated value
of ID is designated as IDSS , which is the drain – to – source current with source – gate short
circuit. Thus, IDSS is the maximum drain current for a JFET, obtained under the conditions V GS =
0V and VDS > |VP|. As the VDS increases beyond VP, the level of ID remains essentially the same
and this region of the characteristics is known as saturation region. It may also be noted that once
VDS > Vp, the JFET has the characteristics of a current source. Thus the current – voltage
characteristics displayed in fig can be divided into ohmic (linear) and saturation regions with the
pinch-off condition as the boundary.
 As the negative bias of VGS increases, depletion region forms similar to those to those
with VGS = 0 V but at a lower level of VDS. Thus, the result of applying a negative bias to the
gate is to reach the saturation level at a lower level of VDS, as shown in the fig. it is seen that
VGS = -VP, the saturation level of ID is essentially 0mA and the devices have been turned off. The
region of the right of the pinch-off locus in figure is normally employed in linear amplifiers. The

region to the left of the pinch-off locus is referred to as voltage controlled resistance region,
where the JFET can be used as voltage- controlled resistor. The channel resistance (RD) increases
with increase of VGS values and empirical relation between the two is given by

Where R0 is the resistance with VGS = 0. For an n-channel JFET with R0 = 10kΩ at VGS
= -2V.
The drain currents suddenly rise in an unbounded manner at very high levels of VDS. The
vertical rise in current is an indication that breakdown has occurred and the current through the
channel is now limited solely by external circuit. In practical applications, the level of VDS is kept
less than the breakdown voltages (VDSmax) that are mentioned in specification sheets of JFET.
Transfer characteristics
The transfer characteristics of JFET is a plot of output (drain) current versus input
controlling quantity (gate-source voltage) and is used extensively in JFET amplifiers. In contrast
to linear input-output relationship of BJT (IC = βIB), the input-output relationship of JFET is not
linear. The relationship between ID and VGS is defined by Shockley’s equation:

The squared term on the right-hand side of the equation suggests that the relationship of ID vs
VGS is nonlinear and exponential in nature. The transfer characteristics defined by Shockley’s
equation are unaffected by the network in which the device is employed. The transfer curve can
be obtained using Shockley’s equation or from the o/p characteristics.

Expression for pinch off voltage and Drain Current

For the transfer characteristics,VDS is maintained constant at a suitable value greater than the
pinch off voltage VP.The gate voltage VGS is decreased from zero till ID is reduced to zero. The

transfer characteristics ID versus VGS are shown in figure.

 (1)
Where IDS is the saturation drain current, IDSS is the value of IDS when VGS=0 and VP is the pinch
off voltage

MOSFET
MOSFET stands for metal oxide semiconductor field effect transistor. It is capable of voltage
gain and signal power gain. The MOSFET is the core of integrated circuit designed as thousands
of these can be fabricated in a single chip because of its very small size. Every modern electronic
system consists of VLST technology and without MOSFET, large scale integration is impossible.
It is a four terminals device. The drain and source terminals are connected to the heavily
doped regions. The gate terminal is connected top on the oxide layer and the substrate or body
terminal is connected to the intrinsic semiconductor.
MOSFET has four terminals which is already stated above, they are gate, source drain and
substrate or body. MOS capacity present in the device is the main part. The conduction and
valance bands are position relative to the Fermi level at the surface is a function of MOS
capacitor voltage. The metal of the gate terminal and the sc acts the parallel and the oxide layer
acts as insulator of the state MOS capacitor. Between the drain and source terminal inversion
layer is formed and due to the flow of carriers in it, the current flows in MOSFET the inversion
layer is properties are controlled by gate voltage. Thus it is a voltage controlled device.
Two basic types of MOSFET are n channel and p channel MOSFETs. In n channel MOSFET
is current is due to the flow of electrons in inversion layer and in p channel current is due to the
flow of holes. Another type of characteristics of clarification can be made of those are
enhancement type and depletion type MOSFETs. In enhancement mode, these are normally off
and turned on by applying gate voltage. The opposite phenomenon happens in depletion type
MOSFETs.

Working Principle of MOSFET

The working principle of MOSFET depends up on the MOS capacitor. The MOS capacitor
is the main part. The semiconductor surface at below the oxide layer and between the drain and
source terminal can be inverted from p-type to n-type by applying a positive or negative gate
voltages respectively. When we apply positive gate voltage the holes present beneath the oxide
layer experience repulsive force and the holes are pushed downward with the substrate. The
depletion region is populated by the bound negative charges, which are associated with the
acceptor atoms. The positive voltage also attracts electrons from the n+ source and drain regions
in to the channel. The electron reach channel is formed. Now, if a voltage is applied between the
source and the drain, current flows freely between the source and drain gate voltage controls the
electrons concentration the channel. Instead of positive if apply negative voltage a hole channel
will be formed beneath the oxide layer.
Now, the controlling of source to gate voltage is responsible for the conduction of current
between source and the drain. If the gate voltage exceeds a given value, called the three voltage
only then the conduction begins.
The current equation of MOSFET in triode region is –

Where, un = Mobility of the electrons Cox = Capacitance of the oxide layer W = Width of the gate
area L = Length of the channel VGS = Gate to Source voltage VTH = Threshold voltage VDS =
Drain to Source voltage.
P-Channel MOSFET
MOSFET which has p - channel region between source any gate is known as p - channel
MOSFET. It is a four terminal devices, the terminals are gate, drain, source and substrate or
body. The drain and source are heavily doped p+ region and the substrate is in n-type. The
current flows due to the flow of positively charged holes that’s why it is known as p-channel
MOSFET. When we apply negative gate voltage, the electrons present beneath the oxide layer,
experiences repulsive force and they are pushed downward in to the substrate, the depletion
region is populated by the bound positive charges which are associated with the donor atoms.
The negative gate voltage

also attracts holes from p+ source and drain region in to the channel region. Thus hole which
channel is formed now if a voltage between the source and the drain is applied current flows. The
gate voltage controls the hole concentration of the channel. The diagram of p- channel
enhancement and depletion MOSFET are given below.
N-Channel MOSFET
MOSFET having n-channel region between source and drain is known as n-channel MOSFET .
It is a four terminal device, the terminals are gate, drain and source and substrate or body. The
drain and source are heavily doped n+ region and the substrate is p-type. The current flows due
to flow of the negatively charged electrons, that’s why it is known as n- channel MOSFET.
When we apply the positive gate voltage the holes present beneath the oxide layer experiences
repulsive force and the holes are pushed downwards in to the bound negative charges which are
associated with the acceptor atoms. The positive gate voltage also attracts electrons from n+
source and drain region in to the channel thus an electron reach channel is formed, now if a
voltage is applied between the source and drain. The gate voltage controls the electron
concentration in the channel n-channel MOSFET is preferred over p-channel MOSFET as the
mobility of electrons are higher than holes. The diagrams of enhancements mode and depletion
mode are given below.
Enhancement and Depletion Mode MOSFET EMOSFET
Symbol

Construction

Figure shows the construction of an N-channel E-MOSFET. The main difference between
the construction of DE-MOSFET and that of E-MOSFET, as we see from the figures given
below the E-MOSFET substrate extends all the way to the silicon dioxide (SiO2) and no channels
are doped between the source and the drain. Channels are electrically induced in these
MOSFETs, when a positive gate-source voltage VGS is applied to it.
Operation

As its name indicates, this MOSFET operates only in the enhancement mode and has no
depletion mode. It operates with large positive gate voltage only. It does not conduct when the
=
gate-source voltage VGS 0. This is the reason that it is called normally-off MOSFET. In
these MOSFET’s drain current ID flows only when VGS exceeds VGST [gate-to-source
threshold voltage].
When drain is applied with positive voltage with respect to source and no potential is applied to
the gate two N-regions and one P-substrate from two P-N junctions connected back to back with
a resistance of the P-substrate. So, a very small drain current that is, reverses leakage current
flows. If the P-type substrate is now connected to the source terminal, there is zero voltage across
the source substrate junction, and the–drain-substrate junction remains reverse biased.
When the gate is made positive with respect to the source and the substrate, negative (i.e.
minority) charge carriers within the substrate are attracted to the positive gate and accumulate
close to the-surface of the substrate. As the gate voltage is increased, more and more electrons
accumulate under the gate. Since these electrons cannot flow across the insulated layer of silicon
dioxide to the gate, so they accumulate at the surface of the substrate just below the gate. These
accumulated minority charge carriers N -type channel stretching from drain to source. When this
occurs, a channel is induced by forming what is termed an inversion layer (N-type). Now a drain
current starts flowing. The strength of the drain current depends upon the channel resistance
which, in turn, depends upon the number of charge carriers attracted to the positive gate. Thus
drain current is controlled by the gate potential.
Since the conductivity of the channel is enhanced by the positive bias on the gate so this
device is also called the enhancement MOSFET or E- MOSFET.
The minimum value of gate-to-source voltage VGS that is required to form the inversion layer (N-
type) is termed the gate-to-source threshold voltage VGST. For VGS below VGST, the drain current
ID = 0. But for VGS exceeding VGST an N-type inversion layer connects the source to drain and
the drain current ID is large. Depending upon the device being used, VGST may vary from less
than 1 V to more than 5 V.
JFETs and DE-MOSFETs are classified as the depletion-mode devices because their
conductivity depends on the action of depletion layers. E-MOSFET is classified as an
enhancement-mode device because its conductivity depends on the action of the inversion layer.
Depletion-mode devices are normally ON when the gate-source voltage VGS = 0, whereas the
enhancement-mode devices are normally OFF when VGS = 0.
Characteristics Drain
Characteristics
Drain characteristics of an N-channel E-MOSFET are shown in figure. The lowest curve is
the VGST curve. When VGS is lesser than VGST, ID is approximately zero. When VGS is greater
than VGST, the device turns- on and the drain current ID is controlled by

the gate voltage. The characteristic curves have almost vertical and almost horizontal parts.

The almost vertical components of the curves correspond to the ohmic region, and the
horizontal components correspond to the constant current region. Thus E-MOSFET can be
operated in either of these regions i.e. it can be used as a variable-voltage resistor (WR) or as a
constant current source.
Transfer Characteristics
Figure shows a typical transconductance curve. The current IDSS at VGS <=0 is very
small, being of the order of a few nano-amperes. When the VGS is made positive, the drain
current ID increases slowly at first, and then much more rapidly with an increase in VGS. The
manufacturer sometimes indicates the gate-source threshold voltage VGST at which the drain
current ID attains some defined small value, say 10 u A. A current ID (0N, corresponding
approximately to the maximum value given on the drain characteristics and the values of V GS
required to give this current VGs QN are also usually given on the manufacturers data sheet.

The equation for the transfer characteristic does not obey equation. However it does follow a
similar “square law type” of relationship. The equation for the transfer characteristic of E-
MOSFETs is given as:
ID=K(VGS-VGST)2

Depletion Mode MOSFET Symbol

Construction

Fig Depletion Mode N Channel MOSFET

The depletion mode MOSFET shown as a N channel device (P channel is also available) in Fig
is more usually made as a discrete component, i.e. a single transistor rather than IC form. In this
device a thin layer of N type silicon is deposited just below the gate−insulating layer, and forms
a conducting channel between source and drain.
Therefore when the gate source voltage VGS is zero, current (in the form of free electrons) can
flow between source and drain. Note that the gate is totally insulated from the channel by the
layer of silicon dioxide. Now that a conducting channel is present the gate does not need to cover
the full width between source and drain. Because the gate is totally insulated from the rest of the
transistor this device, like other IGFETs, has a very high input resistance.
Operation
In the N channel device, shown in Fig. 5.2 the gate is made negative with respect to the
source, which has the effect of creating a depletion area, free from charge carriers, beneath the
gate. This restricts the depth of the conducting channel, so increasing channel resistance and
reducing current flow through the device. Depletion mode MOSFETS are also available in
which the gate extends the full width of the channel

(from source to drain). In this case it is also possible to operate the transistor in
enhancement mode. This is done by making the gate positive instead of negative.
 Fig. Operation of a Depletion Mode MOSFET
The positive voltage on the gate attracts more free electrons into the conducing channel, while
at the same time repelling holes down into the P type substrate. The more positive the gate
potential, the deeper, and lower resistance is the channel. Increasing positive bias therefore
increases current flow. This useful depletion/enhancement version has the disadvantage that, as
the gate area is increased, the gate capacitance is also larger than true depletion types. This can
present difficulties at higher frequencies.

FET as Voltage-Variable Resistor

FET is operated in the constant-current portion of its output characteristics for the linear
applications. In the region before pinch-off , where VDS is small , the drain to source resistance
rd can be controlled by the bias voltage VGS . The FET is useful as a voltage variable resistor
(VVR) or voltage dependent resistor (VDR) .
In JFET , the drain to source conductance gd =ID/VDS for small values of VDS , which may
also be expressed as
gd=g do [1-(VGS/VP)1/2]
where gdo is the value of drain conductance when the bias voltage VGS is zero. The variation of
the rd with VGS can be closely approximated by the empirical expression ,
rd =ro/(1-KVGS)
Where ro=drain resistance at zero gate bias, and K=a constant , dependent upon FET type .
Comparison of MOSFET and JFET
1. In enhancement and depletion types of MOSFET, the transverse
electric field induced across an insulating layer deposited on the semiconductor material
 controls the conductivity of the channel. In the JFET the transverse electric field across
the reverse biased PN junction controls the conductivity of the channel.
2. The gate leakage current in a MOSFET is of the order of 10-12A.Hence the input
resistance of a MOSFET is very high in the order of 1010 to 1015 ohm. The gate leakage
current of a JFET is of the order of 10-9A and its input resistance is of the order of 108
ohm.
3. The output characteristics of the JFET are flatter than those of the MOSFET and hence,
the drain resistance of a JFET(0.1 to 1Mohm) is much higher than that of a MOSFET(1
to 50 K ohm)
4. JFETs are operated only in the depletion mode. The depletion type MOSFET may be
operated in both depletion and enhancement mode.
5. Comparing to JFET, MOSFETs are easier to fabricate.
6. MOSFET is very susceptible to overload voltage and needs special handling during
installation. It gets damaged easily if it is not properly handled.
7. MOSFET has zero offset voltage. As it is a symmetrical device, the source and drain can
be interchanged. These two properties are very useful in analog signal switching.
8. Special digital CMOS circuits are available which involves near –zero power dissipation
and very low voltage and current requirements. This makes them most suitable for
portable systems.
Comparison of JFET And BJT
1. FET operations depend only on the flow of majority carrier-holes for P-channel FETs and
electrons for N-channel FETs. Therefore, they are called Unipolar devices. Bipolar
transistor (BJT) operation depends on both minority and majority current carrier.
2. As FET has no junctions and the conduction is through an N-type or P-type
semiconductor material, FET is less noisy than BJT.
3. As the input circuit of FET is reverse biased, FET exhibits as much higher input
impedance (in the order of 100MOHM) and lower output impedance and there will be a
high degree of isolation between input and output. So, FET can act as excellent buffer
amplifier but the BJT has low input impedance because its input circuit is forward biased.
4. FET is a voltage control device, i.e. voltage at the input terminal controls the output
current, whereas BJT is a current control device, i.e. the input current controls the output
current.
5. FETs are much easier to fabricate and are particularly suitable for ICs because they
occupy less space than BJTs.
 6. The performance of BJT is degraded by neutron radiations because of reduction in
minority carrier life time, whereas FET can tolerate a much higher level of radiation since
they do not rely on minority carrier for their operation.

7. The performance of FET is relatively unaffected by ambient temperature changes. As it

has a negative temperature coefficient at high current levels, it prevents the FET from
thermal break down. The BJT has a positive temperature coefficient at high current levels which
leads to thermal break down.
8. Since FET does not suffer from minority carrier storage effects, it has a higher switching
speeds and cut off frequencies’ suffers a minority carrier storage effects and therefore has
lower switching speed and cut off frequencies.
9. FET amplifiers have low gain bandwidth product due to the junction capacitive effects
and produce more signal distortion except for small signal operation.
10. BJT are cheaper to produce than FETs.

JFET Applications
 JFET is used as a switch.
 JFET is used as a chopper.
 Used as an amplifier.
 Used as a buffer.
 Used in the oscillatory circuits because of its low frequency drift.
 Used in communication equipment’s, such as FM and TV receivers because of their low
modulation distortion.
 Used as voltage-controlled resistors in operational amplifiers.
 JFETs are used in cascade amplifiers and in RF amplifiers.