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0% found this document useful (0 votes)
18 views8 pages

QBDLD1

dld

Uploaded by

krishna
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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BAPATLA WOMEN’S ENGINEERING COLLEGE::BAPATLA

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

CLASS/SEM: II\IV B.TECH - I ISEM BRANCH: E.C.E (A &B)


A.Y:2023-2024
SUBJECT/CODE: DLD\EC-213(R22)
NAME OF THE FACULTY: G.Krishnaveni

QUESTION BANK

UNIT –I
Binary Systems, Boolean Alegebra & Logic Gates
2 MARKS QUESTIONS

1. What are the characteristics of Digital Systems. (L1) (2M)

2. Convert (15) 10 to Binary (L2) (2M)

3. Explain about Diminished Radix complement (L2) (2M)

4 .What is meant by parity bit? (L1) (2M)

5. Define duality property. (L1) (2M)

6. Define binary logic? (L4) (2M)

7. Which gates are called as the universal gates? What are its advantages? (L3) (2M)

8. State the associative property of Boolean algebra. (L2) (2M)

9 Explain classification of Number system (L2) (2M)

10. What is a prime implicate? (L1) (2M)

10 MARKS QUESTIONS

1 a) Convert the following numbers (L5) (5M)


i)(163.789)10 to Octal number ii)(11001101.0101)2 to base-8 and base-4
iii)(4567)10 to base2 iv) (4D.56)16 to Binary
b) Subtract (111001)2 from (101011) using 1’s complement? (L5) (5M)

2. a) Represent the decimal number 3452 in i)BCD ii)Excess-3 (L5) (5M)


b) perform (-50)-(-10) in binary using the signed-2’s complement (L4) (2M)
c) Determine the value of base x if(211)x=(152)8 (L4) (2M)
3. a) Convert the following numbers (L5) (3M)
i) (250.5)10 = ( )2 ii) ) (673.23)10 = ( )8 iii)(101110.01)2=( )8
b) Convert the following to binary and then to gray code (AB33)16 (L2) (2M)
Digital Logic Design Page 1
Digital Logic Design Page 2
c) Perform the following Using BCD arithmetic (7129) 10 + (7711) 10 (L3) (3M)

4. Explain the Binary codes with examples? (L5) (10M)

5. a) What is Digital System? Characteristics of digital systems. (L5)(5M)

b) Explain the difference between analog and digital systems (L5) (5M)
6. a) Design the circuit by Using NAND gates F= ABC’+ DE+ AB’D’ (L5) (5M)
b) Simplify and implementation the following SOP function using NOR gates (L3)
(5M) F(A,B,C,D)= ∑m(0,1,4,5,10,11,14,15)
7. Convert the following (L2) (5M)
a)(1AD)16=( )10 b) (453)8=( )10 c) (10110011)2=( )10 d) (5436)10=( ) 3.
8 a)Explain binary to Gray & Gray to binary conversion with example? (L5) (5M)
b) State and Explain the DeMorgan’s Theorem and Consensus Theorem (L3) (5M)
9) Convert the following numbers (L2) (5M)
i) (615)10 = ( )16 ii) ) (214)10 = ( )8 iii)(0.8125)10=( )2
iv) (658.825)10=( )8 v)(54)10=( )2
10) Explain the Excess-3 code? Write about Error correction & Detection? (L5) (5M)

Digital Logic Design Page 3


Gate Level Minimization

2 MARKS QUESTIONS

1. What is meant by karnaugh map or K-Map method? (2M)


2. Define Pair, Quad, and Octet (2M)
3. What are called don’t care conditions? (2M)
4. What are the 2 forms of Boolean expression? (2M)
5. Define Minterm & Maxterm (2M)
6. Explain SOP and POS form (2M)
7. Explain Canonical SOP form (2M)
8. State De Morgan's theorem (2M)
9. Explain demorgan’s law (2M)
10. What is an essential prime implicante (2M)

10 MARKS QUESTIONS
1.Simplify the Boolean expression using K-MAP (L5) (10M)

F(A,B,C,D,E)= ∑m(0,1,4,5,16,1721,25,29)
2.Simplify the Boolean expression using K-MAP (L5) (10M)
F(A,B,C,D) = ∑m(1,2,3,8,9,10,11,14) +d(7,15)

3.Simplify the Boolean expression using K-map and implement using NAND gates
F(A,B,C,D) = ∑m(0,2,3,8,10,11,12,14) (L4) (10M)

4.Simplify the Boolean expressions to minimum number of literals


i) (A + B)(A + C’ )(B’ + C’ ) (L3) (3M)

ii) AB + (AC)’ + AB’C (AB + C) (L3)(4M)

iii) (A+B)’ (A’+B’)’ (L5) (3M)

5.Reduce the expression f(x,y,z,w)= πM(0,2,7,8,9,10,11,15) .d (3,4) using K-Map?


(L5) (10M)

6.Simplify the Boolean expression using K-map? (L5) (10M)

F(A,B,C,D,E)= ∑m(0,2,4,6,9,11,13,15,17,21,25,27,29,31)
7. Obtain the a) SOP b) POS expression for the function given below (L5) (10M)
F(A,B,C,D)= = ∑m(0,1,2,5,8,9,10)

8.a) Simplify the Boolean expressions to minimum number of literals (L4) (5M)
i) X’ + XY + X Z’ + XYZ’ ii) (X+Y) (X+Y’)
9.b) Obtain the Complement of Boolean Expression (L4) (5M)
i) A+B+A’B’C ii) AB + A (B +C) + B’(B+D)
10. Determine the minimal sum of product form of (L4) (5M,5M)
a) f(w,x,y,z)=∑m(4,5,7,12,14,15) +d(3,8,10)
b) F(A,B,C,D)=πM(0,3,5,6,8,12,15)

Digital Logic Design Page 4


UNIT –II
Combinational Logic
2 MARKS QUESTIONS

1. Define combinational logic. (2M)


2. Explain the design procedure for combinational circuits (2M)
3. Define Half adder and full adder (2M)
4. What is Decoder (2M)
5. Define Encoder? (2M)
6. Construct 2:1 multiplexer? (2M)
7. Define subtractor? (2M)
8. Difference between encoder and decoder (2M)
9. Define de-multiplexer? (2M)
10. Explain Applications of Multiplexer (2M)

10 MARKS QUESTIONS

1. Implement BCD to 7-segment decoder for cathode type using 4:16 decoder? (L5) (10M)
2. A)Implement the following Boolean function using 8:1 multiplexer (L5) (5M)
F(A, B, C, D) = A’BD’ + ACD + A’C’ D +B’CD

B)Explain about Full Adder? (L2) (5M)


3. A) Explain about 2-bit Magnitude Comparator? (L2) (5M)
B) Explain Full binary subtractor in detail? (L2) (5M)
4. Design the combinational circuit binary to gray code? (L5) (10M)
5. A)Explain about Binary Multiplier ? (L2) (5M)
B)What is memory decoding? Explain about the construction of 4 X 4 RAM ? (L2) (5M)

6. A) Implement the following Boolean function using 8:1 multiplexer (L5)(5M)

F(A,B,C.D) = Σ𝑚 (0,1,2,5,7,8,9,14,15)
B) Explain about Decimal Adder? (L2) (5M)
7. A)Design a 4 bit adder-subtractor circuit and explain the operation in detail? (L5) (5M)
B) Explain the functionality of a Multiplexer? (L2) (5M)
8. Explain The Half adder? Implement the full adder using two half adders (L5) (10M)
9. A)Design a 4 bit binary parallel subtractor and the explain operation in detail? (L5) (5M)
B) Design the combinational circuit of 4 Bit Parallel Adder? (L5) (5M)
10. a)What is the truth table of Half-subtractor? (L1) (2M)
b) Define priority encoder? (L1) (2M)
c) Explain the design procedure for combinational circuit? (L1) (2M)
d) Design 4 bit parallel Adder? (L5) (2M)
e)Define Multiplexer and applications of multiplexer? (L1) (2M)

Digital Logic Design Page 5


UNIT –III
Synchronous Sequential Logic
2 MARKS QUESTIONS

1. What are the classifications of sequential circuits? (2M)


2. What is the operation of D flip-flop? (2M)
3. What is flip-flop (2M)
4. Define Race Around Condition (2M)
5. Difference between latch and flip-flop (2M)
6. Define Propagation Delay (2M)
7. What is Master Slave Flip-flop (2M)
8. Explain Shift Registers (2M)
9. What are the applications of Flip-flops (2M)
10. What is state diagram (2M)

10 MARKS QUESTIONS
1. A) Explain the Logic diagram of JK flip-flop? (L2) (5M)
B) Write difference between Combinational & Sequential circuits? (L4) (5M)
2. A) Explain the Logic diagram of SR flip-flop? (L2) (5M)
B) Design and draw the 3 bit up-down synchronous counter? (L5) (5M)
3. A) Draw and explain the operation of D Flip-Flop? (L5) (5M)
B) Explain about Shift Registers? (L2) (5M)
4. A) Draw and explain the operation of SR LATCH? (L5) (5M)
B) Explain about Ring counter? (L2) (5M)
5. A) Explain about ripple counter? (L2) (5M)
B) What is state assignment? Explain with a suitable example? (L2) (5M)
6. Explain the working of the following (L2 & L5) (10M)
i) J-K flip-flop ii) S- R flip-flop iii) D flip-flop
7. Explain the design of a 4 bit binary counter with parallel load in detail? (L2) (10M)
8. How does it set eliminate is a Master –slave J-K flip-flop? (L2)(10M)
9. A) Explain synchronous and ripple counters compare their merits and demerits? (L2) (5M)
B) Design a 4 bit binary synchronous counters with D-flip flop? (L5 (5M)
10. a)Write the truth table of clocked T- Flip Flop? (L1) (2M)
b) Define shift registers? (L1) (2M)
c) Write the differences between latches and flip flops? (L1)(2M)
d) Write the differences between synchronous and asynchronous counters? (L1) (2M)
e) Define Flip-
flop and various types of flip flops? (L1) (2M)

Digital Logic Design Page 6


Digital Logic Design Page 7
UNIT –V
Memory and Programmable Logic , Digital Logic Circuits
2 MARKS QUESTIONS

1. Explain the Classification of memory (2M)


2. Define ROM (2M)
3. What is Read and Write Operations (2M)
4. List the major differences between PLA and PAL (2M)
5. Define PLA (2M)
6. Differentiate volatile and non-volatile memory (2M)
7. What are the different types of ROM (2M)
8. Define the Static RAM and Dynamic RAM (2M)
9. What is BIT,BYTE and WORD (2M)
10. What is Cache Memory (2M)

10 MARKS QUESTIONS
1. A) Write difference between PROM ,PLA &PAL? (L4) (5M)
B) Explain about Hamming code? (L2) (5M)
2. Encode the 11-bit code 10111011101 into 15 bit information code? (L3)(10M)
3. Implement the following function using PLA (L5)(10M)
A(x,y,z)=∑m(1,2,4,6) B(x,y,z)=∑m(0,1,6,7) C(x,y,z)=∑m(2,6)
4. Design PAL for a combinational circuit that squares a 3 bit number? (L5)(10M)
5. Write about the following (L2)(10M)
i) Transistor-transistor Logic (TTL)
ii) Emitter – coupled Logic (ECL)
iii) CMOS Logic
6. Construct the PROM using the conversion from BCD code to Excess-3 code? (L5)(10M)

7. Implement the following functions using PLA. (L5)(10M)


A(x,y,z) = ∑m(1,2,4,6) B(x,y,z) = ∑m(0,1,6,7) c(x,y,z) = ∑m(2,6)
8. A)Construct the PROM using the conversion from BCD code to Excess-3 code? (L5)(10M)

9. A)Explain about TTL family ? (L2)(5M)

B) Explain about memory decoding error detection and correction? (L2)(5M)


10. a)Write the difference between PLA & PAL? (L1) (2M)
b) Define fan out of a logic gate ? (L1) (2M)
c) What is the function of EAROM? (L1) (2M)
d) Define CMOS? (L1) (2M)
e) Write a short notes on Programmable array Logic? (L1) (2M)

Digital Logic Design Page 8

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