C 0800csr20312200r

Reg No.:

APJ ABDUL KALAM TECHNOLOGICAL UN

Third Semester B.Tech Degree Examination December 2020 (2019

Course Code: CST203

Course Name: LOGIC SYSTEM DESIGN
Max. Marks: 100 Duration: 3 Hours
PART A
Answer all questions. Each question corries 3 marks Marks
ii.

I' hexadecimal
Convert (456.78)10 to a) binary b) octal and c) (3)
2 Write a) l's complement and2) 2's complement representations of (-126) (3)
3 State and prove De Morgan's Theorem (3)
4 Design a circuit using NAND gates for implementing EXCLUSNE-OR (3)
function
5 Design a half adder circuit using any universal gate. (3)
6 Draw the logic diagram of a2xl multiplexer circuit (3)
7 Derive the characteristic equation of a D flip flop from its excitation table. (3)
8 How is a sequential circuit different from a combinational circuit? Give an (3)
example for each circuit.
9 Distinguish between a ring counter and Johnson counter (3)
10 When do you implement a combinational circuit using ROM and when do (3)
implement a combinational circuit using PLA in preference to ROM.
PART B
Answer any onefull questionfrom each module. Each question curries 14 marks
Module I
l l a) Convert i) (13AF)r6 to octal ii) (10110101.101)2 to decimal (6)
b) Add i) BCD numbers 1567 and 968 ii) octal numbers 2376 and 5677 (8)
12 a) Perform the following operations using 2's complement representation (10)
i) (-34) + (+2t) ii) (+26) - (-r2) iii) (-33) + (-22) iv) (+a5) - (+32)
b) Convert D (1001l0l0) in 2's complement form to decimal (4)
ii) (l0l I l00l) in l's complement form to decimal '
Module 2
13 a) Using K Map simplify the function (8)

F(w, x. y, z) : > (0,1,2,3,5,7,8,9,10, 1 3, I 5)

b) Express the above function in product of maxterms form. (6)

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 0800csT20312200r

14 a) Using tabulation method simpli$ the function

(8)
F(w,x,y,z) = | (0,2,4,5,6,7,g,12,13,14,1 5)
b) Express the following functions in a canonical form
(6)
i) F= D+BC' ii) F: AB, +BC,

Module 3
l5 a) Design a full subtractor circuit. (6)
b) Design a code converter for converting a BCD to excess-3
code. (8)
16"\lna) Explain BCD adder using a block diagram.
(7)
b) Design a2bit magnitude comparator. (7)
r. Module 4

':l.
17 a) With a logic diagram explain how a master slave flip flop
overcomes race (7)
around problem.
b) Design a2bit synchronous counter. (7)
l8 a) Draw the state diagram and logic diagram of a BCD ripple
counter. (6)
b) Design a 3 bit synchronous up-down counter. (g)
Module 5
19 a) Explain the working of a diagram (7)
3 stage Johnson ring counter with a block
b) Explain the working of a 3 bit bidirectional shift register
with parallel load. Q)
20 a) Illustrate the algorithm for addition and subtraction of two floating point (7)
numbers.
b) Illustrate the algorithm for addition and subtraction two binary
numbers in (7)
sign magnitude form.
ri+***

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