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LPC2148 Watchdogtimer

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88 views10 pages

LPC2148 Watchdogtimer

Uploaded by

Sania Kawade
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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LPC214x WDT (Watchdog Timer)

Application of Watchdog Timer


• The purpose of the watchdog is to reset the microcontroller within a
reasonable amount of time if it enters an erroneous state.

• When enabled, the watchdog will generate a system reset if the user
program fails to feed (or reload) the watchdog within a
predetermined amount of time.
Features
• Internally resets chip if not periodically reloaded.

• Debug mode.

• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled.

• Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.

• Flag to indicate Watchdog reset.

• Programmable 32-bit timer with internal pre-scaler.

• Selectable time period from (TPCLK x 256 x 4) to (TPCLK x 232 x 4) in multiples of TPCLK x 4.
Watchdog Block Diagram
WDMOD (Watchdog Mode Register)

• It is an 8-bit read-write register.


• It is used to control the operation of the watchdog.
• Bit 0 – WDEN (Watchdog Interrupt Enable)
• Bit 1 – WDRESET (Watchdog Reset Enable)
• Bit 2 – WDTOF (Watchdog Time-Out Flag)
This bit is set when the watchdog times out. It is cleared by
software.
• Bit 3 – WDINT (Watchdog Interrupt Flag)
This bit is set when the watchdog times out. This bit is
cleared when any reset occurs. It is a read only bit.
WDRESET WDEN Mode of Operation

0 or 1 0 Debug/Operate without watchdog running

Watchdog Interrupt Mode: Debug with watchdog interrupt but


no WDRESET enabled.
0 1
A watchdog counter underflow will set the WDINT flag and the
watchdog interrupt request will be generated.

Watchdog Reset Mode: Operate with the watchdog interrupt


and WDRESET enabled.
A watchdog counter underflow will reset the microcontroller.
1 1
Although the watchdog interrupt is also enabled (WDEN=1), it
will not be recognized since the watchdog reset will clear the
WDINT flag.
WDTC (Watchdog Timer Constant Register)

• It is a 32-bit read-write register.


• Every time a sequence feed occurs, the WDTC
content is loaded into the watchdog timer.
• The 8 least significant bits (bits 7:0) of this register are
set to 1 on reset.
• Any value below 0xFF will cause 0xFF to be loaded in
this register. Hence, the minimum timeout interval is
(TPCLK * 256 * 4) i.e. (TPCLK*WDTC*4)
WDFEED (Watchdog Feed Register)

• It is an 8-bit write only register.


• Writing a 0xAA followed by 0x55 to this register will reload the
watchdog timer with the WDTC value.
• This operation will also start the watchdog if it is enabled via the
WDMOD register.
• Making WDEN bit 1 in the WDMOD register is not sufficient to start
the watchdog. A valid feed sequence must be completed so that the
watchdog is able to generate an interrupt/reset. Until then, the
watchdog will ignore feed errors.
• Once a 0xAA is written to the FEED register, the next operation should
be a 0x55 write to the FEED register, otherwise, the watchdog is
triggered.
• The interrupt/reset will be generated during the second PCLK following
an incorrect access to a watchdog timer register during a feed
sequence.
• Interrupts should be disabled during the feed sequence. An abort
condition will occur if an interrupt occurs during the feed sequence.
WDTV (Watchdog Timer Value Register)

• It is a 32-bit read only register.


• It is used to read the current value of watchdog timer.
Steps to program watchdog timer
• Set the watchdog timer constant reload value in the WDTC register
• Select the mode using the WDMOD register
• Start the watchdog by feeding it with 0xAA followed by 0x55 in the
WDFEED register
• Make sure to feed the watchdog again before the timer counter
underflows in order to prevent reset/interrupt
• The Watchdog Time-Out Flag (WDTOF) can be monitored to
determine if the watchdog has caused reset condition. The WDTOF
flag must be cleared using software.

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