2017 International Conference on circuits Power and Computing Technologies [ICCPCT]

Design of a low power, high speed double tail

comparator
Aakash.S, Anisha.A, Jaswanth Das G, Abhiram T,Anita J.P
Department of Electronics and Communication Engineering
Amrita School of Engineering, Coimbatore
Amrita VishwaVidyapeetham
Amrita University, India
[email protected],[email protected]

Abstract—In the fast moving digital world, it becomes

imperative to constantly come up with innovation in digitization.
The analog to digital converter is the second most widely used
device in the world of electronic circuits.ADCs are composed of
dynamic comparators. To overcome the challenges faced due to
the digital change, improved versions of the conventional
comparator design for high-speed functioning and low power
consumption has been proposed. Area is another main factor
when keeping in mind the design of these dynamic comparators.
180 nm CMOS technology and a constant supply voltage of 0.8V
have been used. A conventional double tail comparator has been
designed by adding transistors without hindering the
functionality. This provides faster, more efficient modification of
the comparator design. A new design for a dynamic regenerative
double-tail comparator has been proposed which uses clock- Fig 1. Operational Amplifier in open loop
gating techniques. This further reduces the power consumption (comparator)
and provides higher speed by reducing the delay time of the
circuit.
small chip area is a must. Compensation on the area of the
Keywords—Comparator; Analog to digital converter(ADC); design for achieving the desired high speed and low power
dynamic comparator; regenerative comparator; clock-gating. becomes inevitable. Hence there exists a trade-off between
area and speed of the comparator.
I. INTRODUCTION
A comparator is a decision making electronic device that
uses an operational amplifier having a high gain. A There are three main stages in a comparator; the first stage is
comparator compares an input voltage level with another the pre-amplifier stage. In this stage the input signal which is
voltage level or a preset voltage VREF. It produces a binary fed to the comparator is being amplified. The second stage is a
output depending on which analog input voltage is larger. positive feedback stage. This is mainly used to identify the
Dynamic regenerative comparators are used to begin with, input signal which is high or low. The final stage is the
dynamic signifies the addition of clocks to the input of the decision making stage and an output buffer stage. Here the
circuit design. The outputs are produced depending upon the main purpose of buffer is to amplify the information which is
state of the clock. Regenerative comparators are those obtained and produce a digital signal as its output. Designing a
comparators using positive feedback like a latch to compare comparator is done by considering input common mode range,
the signals. The feedback aids in providing higher speed in the power dissipation, propagation delay and area of the entire
circuit. chip.

In a comparator, when the non-inverting terminal is at a higher The implementation of comparators with 4 stages and
voltage potential than the inverting terminal, the output is integrated inductors was done. This used a 10GHz 4-stage
pulled up to +Vsatas shown in the Fig 1. Similarly when the comparator in 0.11ȝm/1.2V CMOS, which was used to obtain
inverting terminal is at a higher voltage potential than non- every 4th bit of the data stream. With supply voltage being 1V
inverting terminal, the output is pulled down to –Vsat. at the input side, a bit error rate of < 10-12 was achieved
[3].The comparators are used under very low supply voltages
The comparators are most widely used in analog to digital
convertors like the flash ADC. The comparator design has a
predominant influence on the overall performance of ADCs.
For any comparator a low supply voltage, high speed and

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 2017 International Conference on circuits Power and Computing Technologies [ICCPCT]

with help of supply boosting techniques which are based on

the usage of static, dynamic and switched voltage sources [4].

The circuit in [3][4] was further modified and the delay time
of the comparator was measured with the help of an additional
on-chip circuit and the delay time variation of the comparator
was found to be ı§11ps [5].

In [2][3][5] additional circuit has been added to the

comparatorso as to improve its speed under very low supply
voltages. The modified comparator in [2] works under a
lowsupply voltage of 0.5V thereby consuming only 18ȝw
power. Even though the approach is effective the mismatch of
components in the added circuit on performance needs to be
taken into account.

The structure of double-tail comparator which was proposedin

[9] is actually based on designing withtwo stages. The input
and the cross coupled stages which are separated. Due to this
separation the comparator is able to perform at much faster Fig 2. Conventional Comparator
rate over a variety of common-mode voltage and a wide range
of supply voltage [9].In the paper, an elaborated analysis on
delay, area and power ofdynamic comparators has been A. Conventional comparator
presented for numerous architectures. A typical comparator circuit has a TAIL MOSFET and two
back to back inverters that operates like a latch..The
According to the double-tail structure which is put forward schematic design for the conventional comparator is shown
in [9], a very new dynamic comparator was presented, which in Fig 2[1].
do not need a high input voltage or stacking of too many
transistors as that in the existing literature. Just by adding very The comparator circuit works with the supply voltage of
few minimum size transistors to the original double-tail 0.8V and the technology used is 180nm CMOStechnology.
comparator structure, the latch delay time was observed to be Initially when the clk=0 , the TAILMOSFET is OFF
reduced drastically. Another added advantage to this soOUTP and OUTN are charged to VDD.When the clock
modification is that a reasonable amount of power is saved becomes 1, it turns ON the TAIL MOSFET, depending
when compared to the conventional comparator and double upon the input. If INP>INN, OUTP discharges at much
tail comparator. higher rate than OUTN.Once OUTP completely
discharges, it turns ON the MOSFET M5 which pulls back
In this paper, four designs for a comparator are presented. The OUTN to VDD.The same process happens when
conventional comparator, double-tail comparator and modified INN>INP.The simulation of the above schematic was
double tail comparator and an enhanced double tail performed in CADENCE VIRTUOSO IC 6.1 and their
comparator using clock-gating technique. In conclusion a results are shown in Fig 3.
comparison of the performances of all fourdesigns is done and
thepower, delay and area are analyzed. B. Double tail comparator
II. CLOCKED REGENERATIVE COMPARATOR
The major difference between a conventional and a double tail
comparator is that this circuit is employed with two TAIL
Comparators play a vital role in analog to digital conversion; MOSFETs thereby providing two paths for the current to
hence having a high-speed comparator is crucial. Here discharge. Hence reducing the delay of the circuit. This
regenerative comparator provides a helping hand in this case, structure also has less stacking of transistors when compared
as these comparators have strong positive feedback. In this to the normal comparator. The schematic for the double tail
paper a brief analysis on power, area and delay is done for the comparator is shown in Fig 4[1].
comparator, double tail, modified double tail and proposed
design, which uses clock-gating technique to reduce the power
consumption.
.

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 2017 International Conference on circuits Power and Computing Technologies [ICCPCT]

it turns ON the MOSFET MR2 which pulls OUTP back to

ground before it can reach VDD. By this time OUTN gets
charged to VDD. This can be observed in the simulation results
that are obtained from the schematic. The simulation results
are shown in Fig 5.

Fig 3. Transient analysis of conventional comparator

Fig 5. Transient analysis of double-tail comparator

C. Modified double-tail comparator

The schematic of the modified double-tail comparator as is

shown in Fig 6[1].When the clk=0, i.e. during the initial phase,
its operation is similar to that of a double tail comparator.
During the set phase, when clk=VDD, MOSFETs M3and M4
are in OFF condition thus FN and FPstart to discharge at
different rates according to the input voltages. If INP > INN,
FN discharges at a much higher rate than FP, thereby turning
the MOSFET, Mc1 ON, which pulls FP back to VDD. By this
time Mc2 is still OFF, thereby allowing FNto discharge
completely. When the control transistors either Mc1or Mc2 is
turned ON, it leads to the static power consumption in the
circuit. To reduce the static power consumption, to the original
Fig 4. Double-Tail Comparator double tail circuit we introduce the two NMOS (Msw1 and
Msw2) which act as a switch. The simulation of the above
design schematic was done and the simulation results are
During the initial phase (when clock=0), the TAIL1 and shown in Fig 7.
TAIL2 MOSFETs are in OFF condition. Due to
this,MOSFETS M3 and M4 is turned ON which charges FNand
FPto VDD. FN and FP turn ON the MOSFETs MR1 and MR2,
which pulls down the node OUTN and OUTP to ground, this
turns ON the MOSFETs M7 and M8. When clk =1, MOSFETs
M3and M4 are in OFF condition and both the tail MOSFETs
are turned ON. OUTN and OUTP are charged to VDD at
different rates. If INP > INN,FN discharges at much higher rate
than FP. During this stage, OUTN gets charged to VDD at a
much faster rate than OUTP. As FN discharges at a higher rate,

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 2017 International Conference on circuits Power and Computing Technologies [ICCPCT]

when FN discharges completely. In other wordsFN becomes 0.

So FN is given as one of the inputs to the NOR gate and other
input is given as pulsating clock signal. Hence when both FN
and clock are zero, the output of NOR gate is high. Hence
turning ON the TAIL2 MOSFET. The schematic design of the
proposed circuit is as shown in Fig 8.The simulation results
for the above design were obtained as shown in the Fig 9.
III.PERFORMANCE ANALYSIS
By performing a detailed analysis on power, area and
dealy, the results for the conventional, double tail,
modified double tail and proposed comparator have been
compared and the results are shown in Table 1.

Fig 6. Modified double-tail comparator

Fig 8. Proposed double-tail comparator with clock gating.

Fig 7. Transient analysis of modified double-tail

comparator.

D.Proposed Method using clock-gating technique

In order to further reduce the power consumed by the

modified double-tail comparator as proposed in [1], clock-
gating technique has been used.
Clock gating is a technique where the clock is kept idle for
certain duration of time thereby leading to zero power
consumption in the circuit. In this paper, this has been Fig 9. Transient analysis of proposed double-tail
achieved by adding additional logic to the circuit i.e. by comparator.
compensating on the area, the power of the circuit and the
delay is reduced. Here the conventional double tail circuit in
[1] has been modified using a NOR gate. A NOR gate is TABLE I Comparison of the four-comparator designs
chosen because TAIL2 MOSFET needs to be turned ON only

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 2017 International Conference on circuits Power and Computing Technologies [ICCPCT]

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