A Verilog-A Compact Model

for Negative Capacitance FET

Version 1.1.0

Muhammad Abdul Wahab and Muhammad Ashraful Alam

Purdue University
West Lafayette, IN 47907
Last Updated: Apr 05, 2016

Table of Contents

1. Introduction...................................................................................................................................... 2
2. Terminal Voltages and Parameters List...................................................................................... 2
2.1. Terminal Voltages .................................................................................................................. 3
2.2. Parameters List....................................................................................................................... 4
3. Model System and Equations....................................................................................................... 4
4. Device Characteristics ................................................................................................................... 6
5. Summary ....................................................................................................................................... 10
References ............................................................................................................................................ 11
Appendix ................................................................................................................................................ 13
A. Transient performance ............................................................................................................ 13
B. Parameters of Conventional MOSFET ................................................................................. 14
C. HSPICE toolkit ...................................................................................................................... 14
D. Simulating HSPICE netlist .................................................................................................. 14
E. Checklist for model analysis ................................................................................................... 14

1
1. Introduction
Continuous downscaling of the physical dimensions of MOSFET has helped increase transistor
density and improved the performance of the integrated circuit (IC). It has been difficult however
to reduce the supply voltage (VDD) significantly below 1 V without sacrificing the ON current and
the ON/OFF ratio. This “1V-limit” translates to a floor for minimum power consumption (Pmin) [1],
[2]. The increasing thermal resistance (RTH) of the novel transistors (FINFET, SOI-FET, or Gate-
all-around (GAA) FET) has further acerbated the problem. Indeed, temperature rise due to self–
heating (Δ𝑇 = 𝑃 × 𝑅𝑇𝐻 ) affects the reliability of the transistors [3], [4]. Therefore, any scheme
that reduces VDD will also reduce power consumption and self-heating. One option to reduce
VDD involves improving the sub-threshold slope (S) of a transistor by overcoming Boltzmann
limit (S=60 mV/dec). Negative capacitance (NC) dielectric such as ferroelectric (FE) material
improves S through amplification of gate bias [5]–[13] in a NC-FET (Fig. 1(a))). In this work, we
developed a verilog-A compact model of a generic NC-FET [11], [12]. In the model, NC
dielectric is integrated as gate dielectric stack with conventional MOSFET. The model deployed
involves a two-component circuit: we used MVS and BSIM4 for classical MOSFET and a non-
linear voltage source for NC dielectric. The MOSFET model and Landau theory work self-
consistently to provide the characteristics of NC-FET. This manual discusses the theoretical
model, the circuit representation, and results through illustrative examples of the NC-FET.

For someone new to NC-FET, a tutorial (https://nanohub.org/resources/23157) from Purdue

University provides a helpful resource [14]. Beside verilog-A, we separately deployed the
MATLAB model of NC-FET (https://nanohub.org/resources/23185) [15]. This revised verilog-A
version (1.1.0) of NC-FET includes (i) dipole response of the NC dielectric in transient
simulation, (ii) explicit definition of all variables (1.0.0), and (iii) a modified expression for ID
leakage to ensure that MVS model produces ID=0 µA/µm at VD=0 V. The selector ‘leak_select’
allows the user to include or exclude the ID leakage current.

2. Terminal Voltages and Parameters List

(a) (b) (c)

G (NC)
G(NC)
FE G (NC) VFE
G(MOS)
OX G (MOS)
S D
S D
B S D
B B
NMOS

Fig. 1 (a) The schematic diagram describes the geometry of the NC-FET. (b) Symbolic
representation of the NMOS NC-FET. (c) The NC dielectric is represented as a dependent
voltage source (VFE) for HSPICE simulation. The NC-FET is represented by two series-
connected components, i.e., the NC dielectric and the MOSFET.

2
 (a) G (NC)
(b)
G (NC)
CFE
CFE
G (MOS) G (MOS)
COV COV
S D S D
B RS S’ B D’ RD

Fig. 2 (a) Ferroelectric acts as an additional gate dielectric capacitor with the conventional
MOSFET. (b) All the parasitic components: source resistance (RS), drain resistance (RD), gate-
source overlap and fringing capacitance (COV) and gate-drain overlap and fringing capacitance
(COV) are included in the analysis.

2.1. Terminal Voltages

The NC-FET has two components: (i) NC dielectric and (ii) the conventional MOSFET.

(i) NC dielectric: The NC dielectric is treated as an external capacitor connected in

series to the gate of the conventional MOSFET. For the DC analysis, the inclusion of
a capacitor in the gate terminal as an external element cannot provide meaningful
results. Therefore, in HSPICE simulation, NC dielectric element is represented as a
dependent voltage source which is a function of gate charge. The inclusion of the NC
dielectric as a voltage source enables circuit simulation. Using the same concept
multiple layers of NC dielectric as dielectric stack can be considered in the model.

(ii) Conventional MOSFET: The second element is a conventional MOSFET transistor

with drain, gate, source, and body terminals. This model and method work for any
structure (planar, double gate, FinFET, SOI FET, GAA-FET, etc) and model
(MVS/BSIM4/BSIM-CMG/etc) of the MOSFET so long it is supported by the circuit
simulator.
In addition to the standard elements, we introduce a dummy node to facilitate exchange of
information between the NC dielectric and the conventional MOSFET. In other words, the NC
dielectric is now represented by 3 terminals and the MOSFET by 5 terminals. The dummy node
(as a voltage terminal) exchanges information regarding the gate charge between the two
elements. HSPICE solves the circuit of the NC-FET self-consistently to compute the unknown
variables (voltages, currents, etc). The introduction of the dummy node for the MOSFET
requires access to the source code. The modified source codes of BSIM4 and MVS are
provided along with the source code of NC dielectric.
The nodes and corresponding node voltages of the NC dielectric and conventional MOSFET are
defined as follows:

3
NC dielectric:

Node Description Voltage

ncp Electrode with positive bias V(ncp)
ncn Electrode with negative (or zero bias) V(ncn)
qg_as_v Dummy node to input the gate charge V(qg_as_v)

Conventional MOSFET (MVS/BSIM/etc):

Node Description Voltage

drain Drain voltage V(drain)
gate Gate voltage V(gate)
source Source voltage V(source)
bulk Bulk voltage V(bulk)
qg_as_v Dummy node to output the gate charge V(qg_as_v)

2.2. Parameters List

Parameters used in the negative capacitance FET model are listed below. Table also lists the
physical meaning of each parameter.
Math Verilog-A Description Default Unit
Symbol Symbol
𝛼𝐹𝐸 alpha Alpha coefficient of the
ferroelectric −1.8 × 1011 𝑐𝑚/𝐹
𝛽𝐹𝐸 beta Beta coefficient of the
ferroelectric 5.8 × 1022 𝑐𝑚5 /𝐹/𝐶𝑜𝑢𝑙2
𝛾𝐹𝐸 gamma Gamma coefficient of the
ferroelectric 0 𝑐𝑚9 /𝐹/𝐶𝑜𝑢𝑙 4
𝜌𝐹𝐸 rho Rho coefficient of the
ferroelectric 9 𝑐𝑚 − 𝑠/𝐹
𝑡𝐹𝐸 tFE Thickness of the ferroelectric 10 × 10−7 𝑐𝑚
dielectric

For details regarding the physical interpretation of the model parameters, see Ref. [6]–[9].

3. Model System and Equations

We develop the model of the NC-FET [11], [12] by integrating the BSIM4/MVS model [16] of the
conventional short channel MOSFET with the Landau theory of negative capacitor [5]. The
subthreshold swing of a MOSFET is defined as

4
 𝑑𝑉𝐺𝑆 𝑑𝑉𝐺𝑆 𝑑𝜓𝑆
𝑆= =( )( )=𝑚×𝑝 (1)
𝑑𝑙𝑜𝑔10 (𝐼𝐷 ) 𝑑𝜓𝑆 𝑑𝑙𝑜𝑔10 (𝐼𝐷 )

where, VGS is the applied gate bias, for NC-FET it is VG(NC)-S. ID is the drain current, 𝜓𝑆 is the
surface potential. The body-factor m can be obtained from the voltage divider rule assuming the
gate-source and gate-drain overlap capacitances (COV) have negligible effect on gate charge
(QG).

𝑑𝑉𝐺𝑆 1 1
𝑚=( ) = (1 + 𝐶𝑆 ( + )) (2)
𝑑𝜓𝑆 𝐶𝑂𝑋 𝐶𝐹𝐸

Landau model for the negative capacitor: Ferroelectric (FE) material exhibits negative
capacitance [5]. The dynamic of FE capacitor can be explained by Landau Khalatnikov (LK)
equation
𝑑𝑄𝐺
𝜌𝐹𝐸 + ∇𝑄𝐺 𝑈 = 0 (3)
𝑑𝑡

The Gibb’s free energy of a ferroelectric material is represented by a two well energy landscape,
as follows,
𝑉𝐹𝐸
𝑈 = 𝛼𝐹𝐸 𝑄𝐺2 + 𝛽𝐹𝐸 𝑄𝐺4 + 𝛾𝐹𝐸 𝑄𝐺6 − 𝑄 .
𝑡𝐹𝐸 𝐺 (4)

The potential (VFE) - charge (QG) relation of the ferroelectric material is represented from eq (4)
as

𝑑𝑄𝐺
𝑉𝐹𝐸 = 2𝛼𝐹𝐸 𝑡𝐹𝐸 𝑄𝐺 + 4𝛽𝐹𝐸 𝑡𝐹𝐸 𝑄𝐺3 + 6𝛾𝐹𝐸 𝑡𝐹𝐸 𝑄𝐺5 + 𝜌𝐹𝐸 𝑡𝐹𝐸 (5)
𝑑𝑡

From eq (5) we can write the capacitance (CFE) - charge (QG) relation of the ferroelectric
material, in steady-state, as

1
𝐶𝐹𝐸 =
2𝛼𝐹𝐸 𝑡𝐹𝐸 + 12𝛽𝐹𝐸 𝑡𝐹𝐸 𝑄𝐺2 + 30𝛾𝐹𝐸 𝑡𝐹𝐸 𝑄𝐺4 (6)

In this work, negative capacitance dielectric and conventional MOSFET are represented as two
different components. The I-V and C-V of the NC-FET are computed through charge and
potential balance in HSPICE. We represented the ferroelectric dielectric as a dependent voltage
source which is a function of QG. To account this dependency we modified the available verilog-
A models of MVS/BSIM4.

5
4. Device Characteristics
We introduced dummy nodes in both NC dielectric and the MOSFET model to exchange
information of gate charge (QG) between them (Fig. 3(a)). We modified the source code of MVS
model to take the gate charge out through dummy node and use that charge as input to the
negative capacitor (Fig. 3(b)). We illustrated this for MVS model in Fig. 3. We followed similar
approach for BSIM4 model. We can use this approach for other MOSFET models such as
BSIM-CMG, BSIM-IMG, BSIM-SOI, etc.

(a) G(NC)

dQG
VFE  2 FE tFE QG  4  FE tFE QG3  6 FE tFE QG5   FE tFE
dt
Dummy voltage
node to share G(MOS)
gate charge (QG)

BSIM4,
S D MVS, etc.
B

(b)
Dummy node in
MVS model
Modification Line 59: module mvs_5t_mod(d, g, s, b, qg_as_v);
in MOSFET’s
source code
Line 358: V(qg_as_v) <+ Qg/W/Lgdr*1e6;
Taking the gate charge (Qg) out as voltage
with unit µC/cm2 through dummy node

Dummy node in
negative capacitor
Line 46: module neg_cap_3t(ncp, ncn, qg_as_v);
Negative
capacitor’s Line 61: V(ncp,ncn) <+ 2*alpha*tFE*(V(qg_as_v)*1e-6)+.....;
code
Line 62: V(ncp,ncn) <+ rho*tFE*ddt(V(qg_as_v)*1e-6);
Input the gate charge (Qg) (of MVS model) as
voltage with unit µC/cm2 through dummy node

Fig. 3 (a) Two elements (MOSFET and negative capacitor) depend on each other through gate
charge (QG). Dummy voltage nodes connect the MOSFET and negative capacitor self-

6
consistently through QG. (b) Verilog-a codes of the MVS model and negative capacitor explain
the inclusion dummy nodes.

To illustrate the model of the NC-FET, we simulate the performance of the conventional
MOSFET (NCFET with tFE=0 nm) and the behavior of the NC dielectric capacitor in Fig. 4. Then
we evaluated the characteristics of the NMOS NC-FET, PMOS NC-FET, NC-FET CMOS
inverter in Figs. 5, 6, and 7, respectively. The improved performance of the NC-FET sustains for
different gate lengths (Fig. 8). The transient performance of the NC-FET CMOS inverter is
evaluated in Fig. 9 (in Appendix).

(a)
4
Conventional
MOSFET 3 CGSOV+CGDOV+COX
CG [F/cm ]
2

1 LG=32 nm
CGSOV+CGDOV+CD VD=1 V
0
0 0.2 0.4 0.6 0.8 1
VG(MOS) [V]
(b)
1.2 Sim.
FE 0.9 Exp.
0.6
P [C/cm ]
2

0.3
0
-0.3
-0.6 tFE=60 nm
-0.9
-1.2
-1 -0.5 0 0.5 1
VFE [V]
(c) tFE=10 nm
1.5 1.5
0.35 VFE=0 to 0.20 V 1.2 1.2
0.25 (3 steps) 0.9 0.9
P [C/cm ]
P [C/cm ]

0.6 0.6
2
2

0.15
U [J/cm ]
3

0.05 0.3 0.3

0 0
-0.05 -0.3 -0.3
-0.15 -0.6 -0.6
-0.25 -0.9 -0.9
-1.2 -1.2
-0.35 -1.5
-1.5
-1.5 -1 -0.5 0 0.5 1 1.5 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 -10 -5 0 5 10
P [C/cm2] VFE [V] CFE [F/cm2]

Fig. 4 (a) C-V characteristics of the conventional MOSFET (using BSIM4). At VGS=0 V, gate
capacitance is dominated by the gate-source (COV) and gate-drain (COV) overlap and parasitic
capacitances. (b) Polarization (P) vs applied bias (VFE) of the ferroelectric dielectric P(VDF-
TrFE). 𝛼𝐹𝐸 and 𝛽𝐹𝐸 coefficients of the ferroelectric dielectric are extracted through fitting of eq
(5) with experiment (from Ref. [10], [17]). We neglect the 5th order term of QG and dipole
response to extract the coefficients of ferroelectric. (c) Energy landscape for different applied
bias (VFE) (eq (4)), polarization (P) vs applied bias (VFE) (eq 5), and polarization (P) vs
capacitance (CFE) (eq 6) of the ferroelectric dielectric.

7
 LG= 32 nm VD= 1V BSIM4 P(VDF-TrFE)
(a) 10 4
(b) 1.2
3
10 0.9

QG [C/cm ]
0.6

2
2
ID [A/m]

10
1 tFE=10 nm 0.3
10 0 tFE=10 nm
10
0 tFE=13 nm -0.3
-1
-0.6 tFE=13 nm
10 -0.9
-2 -1.2
10
0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1
VG(NC) [V] VG(NC) [V]
(c) (d)180 (e) 1.2
1
VG(NC) 0.9
tFE=13 nm

QG [C/cm ]
0.6

2
0.8 150
VG(MOS) 0.3
S [mV/dec]

0.6 120 0
-0.3 Device
V [V]

0.4 90
VFE -0.6 Material
0.2 60 tFE=10 nm -0.9
0 30 -1.2
tFE=13 nm tFE=13 nm -0.3 -0.2 -0.1 0 0.1 0.2 0.3
-0.2 0
0 0.2 0.4 0.6 0.8 1 0 0.1 0.2 0.3 0.4 VFE [V]
VG(NC) [V] VG(NC) [V]

Fig. 5 (a) ID-VGS and (b) Gate charge (QG) vs VGS characteristics of the NMOS NC-FET for
different tFE using BSIM4 and Landau theory. (c) Different potential components of the NC-FET:
applied gate bias (VG(NC)), voltage across the ferroelectric dielectric (VFE), and voltage in the
intermediate node G(MOS), VG(MOS). (d) Subthreshold slope (S) vs VGS for different tFE. (e) QG vs
VFE profile from the circuit simulation (red) and from eq (5) (blue).

8
 LG= 32 nm VD= 1V BSIM4 P(VDF-TrFE)
4
(a) (b) 10 (c) 1.2

S
3
10 0.9

QG [C/cm ]
2 0.6 tFE=10 nm

2
ID [A/m]
10
G (NC)

0.3
10
1 tFE=10 nm 0
B -0.3
0
10
-1
-0.6
10 -0.9
D

-2 -1.2
10
-1 -0.8 -0.6 -0.4 -0.2 0 -1 -0.8 -0.6 -0.4 -0.2 0
VG(NC) [V] VG(NC) [V]
(d) 0.2 (e) 180
tFE=10 nm
0 VFE 150

S [mV/dec]
-0.2 120
VG(MOS)
V [V]

-0.4 90 tFE=10 nm
-0.6 60
-0.8 VG(NC) 30
-1
-1 -0.8 -0.6 -0.4 -0.2 0 -0.4 -0.3 -0.2 -0.1 0
VG(NC) [V] VG(NC) [V]

Fig. 6 (a) Symbolic representation of the PMOS NC-FET. (b) ID-VGS and (c) Gate charge (QG) vs
VGS characteristics of the PMOS NC-FET for different tFE using BSIM4 and Landau theory. (d)
Different potential components of the NC-FET: applied gate bias (VG(NC)), voltage across the
ferroelectric dielectric (VFE), and voltage in the intermediate node G(MOS), VG(MOS). (e)
Subthreshold slope (S) vs VGS for different tFE.

VDD VDD= 1 V BSIM4

(a) (b) 1
LG= 32 nm
0.8 MOSFET
NC-FET
tFE=10 nm
Vout [V]

0.6
Vin Vout 0.4
0.2
0
0 0.2 0.4 0.6 0.8 1
Vin [V]

Fig. 7 (a) Symbolic representation of the NC-FET CMOS inverter. (b) Performance comparison
of the different CMOS inverters. With the incorporation of NC dielectric, NMOS (black arrow)
and PMOS (magenta arrow) are turning-on at lower effective threshold voltage compared to
conventional counterpart.

9
 LG= 45 nm VD= 1V P(VDF-TrFE)
BSIM4 MVS
4
(a) 10 (b)10 4

3 3
10 10
2 2
ID [A/m]

ID [A/m]
10 10
1
10
tFE=10 nm
1
10 tFE=10 nm
0 0
10
tFE=13 nm 10 tFE=13 nm
-1 -1
10 10
-2 -2
10 10
0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1
VG(NC) [V] VG(NC) [V]

(c) 180 (d)180

150 150
tFE=10 nm
S [mV/dec]

S [mV/dec]
120 120
90 90 tFE=13 nm
60 tFE=10 nm 60
30 tFE=13 nm 30
0 0
0 0.1 0.2 0.3 0.4 0 0.1 0.2 0.3 0.4
VG(NC) [V] VG(NC) [V]

Fig. 8 ID vs VGS characteristics of the NMOS NC-FET from (a) BSIM4 and Landau theory and (b)
MVS and Landau theory for 45 nm technology node. Subthreshold slope (S) vs VGS of the
NMOS NC-FET from (a) BSIM4 and Landau theory and (b) MVS and Landau theory for 45 nm
technology node. We compared the ID-VG(MOS) of the conventional MVS and BSIM4 MOSFET
models. Unlike MVS, the ID in BSIM4 model saturates with VG(MOS) beyond off-states while
moving toward the accumulation region. Saturation in ID-VG(MOS) results U-shaped S vs VG(MOS),
whereas conventional MVS model provides mirrored L-shape. To improve the matching of the
simulated results of the two models, we added a leakage current component (ID (@VG(MOS) =0))
to ID-VG(MOS) in the source code of MVS model. In version 1.0.0 of the NCFET model, this
leakage current component was independent of VD. We corrected this in the revised version
1.1.0 by multiplying the leakage current with (VD/VDSAT)/(1+ (VD/VDSAT)β)1/β. VDSAT is the saturation
drain bias and β is the saturation-transition-region fitting parameter [16], [18]. In version 1.1.0,
ID=0 at VG(MOS)=VD=0. In addition, in version 1.1.0, we added a selector ‘leak_select’ to include
and exclude the ID (@VG(MOS) =0). leak_select=1 includes ID (@VG(MOS) =0).

5. Summary
The manual describes the electrical model of the NC-FET by integrating MVS/BSIM4 model with
Landau theory. Please contact Muhammad A. Wahab ([email protected]) regarding any
questions/comments about the negative capacitance FET compact model.

10
References

[1] “International Technology Roadmap for Semiconductors.” [Online]. Available:

http://www.itrs.net/.

[2] “Predictive Technology Model (PTM).” [Online]. Available: http://ptm.asu.edu/latest.html.

[3] S. H. Shin, M. Masuduzzaman, M. A. Wahab, K. Maize, J. J. Gu, M. Si, A. Shakouri, P. D.

Ye, and M. A. Alam, “Direct observation of self-heating in III–V gate-all-around nanowire
MOSFETs,” in 2014 IEEE International Electron Devices Meeting, 2014, pp. 20.3.1–
20.3.4.

[4] M. A. Wahab, S. Shin, and M. A. Alam, “3D Modeling of Spatio-temporal Heat-transport in

III-V Gate-all-around Transistors Allows Accurate Estimation and Optimization of
Nanowire Temperature,” IEEE Trans. Electron Devices, vol. 62, no. 11, pp. 3595–3604,
Nov. 2015.

[5] S. Salahuddin and S. Datta, “Use of negative capacitance to provide voltage amplification
for low power nanoscale devices.,” Nano Lett., vol. 8, no. 2, pp. 405–10, Feb. 2008.

[6] A. Jain and M. A. Alam, “Stability Constraints Define the Minimum Subthreshold Swing of
a Negative Capacitance Field-Effect Transistor,” IEEE Trans. Electron Devices, vol. 61,
no. 7, pp. 2235–2242, Jul. 2014.

[7] A. Jain and M. A. Alam, “Proposal of a Hysteresis-Free Zero Subthreshold Swing Field-
Effect Transistor,” IEEE Trans. Electron Devices, vol. 61, no. 10, pp. 3546–3552, Oct.
2014.

[8] A. Jain and M. A. Alam, “Prospects of Hysteresis-Free Abrupt Switching (0 mV/decade) in

Landau Switches,” IEEE Trans. Electron Devices, vol. 60, no. 12, pp. 4269–4276, Dec.
2013.

[9] K. Karda, A. Jain, C. Mouli, and M. A. Alam, “An anti-ferroelectric gated Landau transistor
to achieve sub-60 mV/dec switching at low voltage and high speed,” Appl. Phys. Lett.,
vol. 106, no. 16, p. 163501, Apr. 2015.

[10] Y. Li, Y. Lian, K. Yao, and G. S. Samudra, “Evaluation and optimization of short channel
ferroelectric MOSFET for low power circuit application with BSIM4 and Landau theory,”
Solid. State. Electron., vol. 114, pp. 17–22, Dec. 2015.

[11] M. A. Wahab and M. A. Alam, “Compact Model of Short-Channel Negative Capacitance

(NC)-FET with BSIM4/MVS and Landau Theory,” in NEEDS Annual Meeting and
Workshop, 2015.

[12] M. A. Alam, P. Dak, M. A. Wahab, and X. Sun, “Physics-Based Compact Models for
Insulated-Gate Field-Effect Biosensors, Landau Transistors, and Thin-Film Solar Cells,”
in IEEE Custom Integrated Circuits Conference (CICC), 2015.

[13] M. Masuduzzaman and M. A. Alam, “Effective nanometer airgap of NEMS devices using
negative capacitance of ferroelectric materials.,” Nano Lett., vol. 14, no. 6, pp. 3160–5,
Jul. 2014.

11
[14] M. A. Alam, “A Tutorial Introduction to Negative--Capacitor Landau Transistors:
Perspectives on the Road Ahead,” NEEDS nanoHUB, 2015.
(https://nanohub.org/resources/23157)

[15] M. A. Wahab and M. A. Alam, “MATLAB: Negative Capacitance (NC) FET Model,”
NEEDS nanoHUB, 2015. (https://nanohub.org/resources/23185)

[16] S. Rakheja and D. Antoniadis, “MVS Nanotransistor Model (Silicon).” NEEDS nanoHUB.

[17] G. Salvatore, A. Rusu, and A. Ionescu, “Analytical model for predicting subthreshold
slope improvement versus negative swing of S-shape polarization in a ferroelectric FET.,”
in In: MIXDES, 2012, pp. 55–59.

[18] A. Khakifirooz, O. M. Nayfeh, and D. Antoniadis, “A Simple Semiempirical Short-Channel

MOSFET Current–Voltage Model Continuous Across All Regions of Operation and
Employing Only Physical Parameters,” IEEE Trans. Electron Devices, vol. 56, no. 8, pp.
1674–1680, Aug. 2009.

[19] T. S. Boscke, J. Muller, D. Brauhaus, U. Schroder, and U. Bottger, “Ferroelectricity in

hafnium oxide: CMOS compatible ferroelectric field effect transistors,” in 2011
International Electron Devices Meeting, 2011, pp. 24.5.1–24.5.4.

12
 Appendix
A. Transient performance

VDD= 0.3 V BSIM4

(a) with MOSFET 0.4

Vin [V]
0.2

0 Vin Vout
0 50 100 150
with NC-FET t [ps]
(b)
( =0 cm-s/F) 0.4
0.4
VVinout[V][V]

0.2
0.2
00
Vin Vout
00 50
50 100
100 150
150
with NC-FET tt [ps]
(c) [ps]
( =9 cm-s/F)
0.4
0.4
Vout [V]

Vin Vout
0.3 0.2
0.2
Vin [V]

0
0.1

0 0 50 100 150
t [ps]
-0.1
0 200 400 600 800 1000 1200 1400 1600 1800
t [ps]

0.4 developed NC-FET model can be used for transient simulation of CMOS circuits.
Fig. 9 Our
Results 0.3
of the transient simulation of the NC-FET CMOS inverter of Fig. 7(a). Ferroelectric
material HfSiO (𝛼𝐹𝐸 = −8.7 × 1010 𝑐𝑚/𝐹, 𝛽𝐹𝐸 = 1.92 × 1020 𝑐𝑚5 /𝐹/𝐶𝑜𝑢𝑙 2 , 𝛾𝐹𝐸 = 0 𝑐𝑚9 /𝐹/
Vout [V]

0.2
𝐶𝑜𝑢𝑙 4, and 𝑡𝐹𝐸 = 15 × 10−7 𝑐𝑚) is used as NC dielectric in the gate dielectric stack [9], [19]. (a)
Input gate
0.1 pulse (Vin) and output (Vout) vs time (t) of the conventional MOSFET CMOS Inverter.
(b) Vin and0
Vout vs t of the NC-FET CMOS Inverter neglecting dipole response of the ferroelectric
(𝜌𝐹𝐸 = 0 𝑐𝑚 − 𝑠/𝐹). (c) Vin and Vout vs t of the NC-FET CMOS Inverter accounting dipole
400 𝐹𝐸 = 600
9 𝑐𝑚 − 𝑠/𝐹).
response-0.1 of the ferroelectric (𝜌
0 200 800 Dipole response
1000 1200slows 1400
down the1600
performance
1800
of the NC-FET and their circuits. The value of 𝜌𝐹𝐸 = 9 𝑐𝑚 − 𝑠/𝐹 is assumed in this work and not
t [ps]
necessarily the parameter of HfSiO.

13
B. Parameters of Conventional MOSFET

Conventional MOSFET parameters are directly collected or extracted from the predictive
technology model ( http://ptm.asu.edu/ ). A sample set of parameters for NMOS device is
provided below as an illustration.
Math Symbol Description 𝐿𝐺 = 45 𝑛𝑚 𝐿𝐺 = 32 𝑛𝑚 Unit
(Default value) (Default value)
𝑊 Channel width 1 1 𝜇𝑚
𝐸𝑂𝑇 Effective oxide thickness 0.9 0.75 𝑛𝑚
𝜀𝑂𝑋 Oxide dielectric constant 3.9 3.9
𝜀0 Free space permittivity 8.854×10-14 8.854×10-14 𝐹/𝑐𝑚
𝑁𝑠𝑢𝑏 Substrate doping density 6.5×1018 8.7×1018 𝑐𝑚−3
𝑉𝑇0 Threshold voltage 0.3423 0.3558 𝑉
𝜇 2
Carrier mobility 295 238 𝑐𝑚 /𝑉𝑆
𝑣𝑥0 Saturation velocity 1.595×107 1.821×107 𝑐𝑚/𝑆
𝑅𝑆 = 𝑅𝐷 Source/Drain resistance 52.5 40 Ω − 𝜇𝑚
𝐶𝐺𝑆𝑂𝑉 = 𝐶𝐺𝐷𝑂𝑉 Source/Drain overlap 2.1×1012 2×1012 𝐹/𝑐𝑚
capacitance
𝑛 Subthreshold coefficient 1.15 1.15
𝛿 DIBL factor 0.0332 0.0424 𝑉/𝑉
𝛽 Saturation-transition- 1.8 1.8
region fitting parameter
𝛼 3.5 3.5
𝛾 Body factor 0.1 0.1 √𝑉

C. HSPICE toolkit

In order to analyze the HSPICE output data, HSPICE toolkit available in Matlab is used. This
can be downloaded from http://www.cppsim.com/InstallFiles/hspice_toolbox.tar.gz . Make sure
to add it in the Matlab path. You can use the following Matlab command to add this to the
default path: addpath(location_of_hspice_toolbox_folder).

D. Simulating HSPICE netlist

HSPICE code can be run on file “filename.sp” using following command: hspice filename.sp

E. Checklist for model analysis

1. Install the HSPICE toolkit to enable data extraction from HSPICE files.

2. Download the complete package in folder NCFET. Compile the following HSPICE files
NCFET\Negative Capacitance FET Model 1.1.0 HSPICE
Netlists\ncfet_nmos_bsim4_Lg32nm\ncfet_nmos.sp

NCFET\Negative Capacitance FET Model 1.1.0 HSPICE

Netlists\ncfet_pmos_bsim4_Lg32nm\ncfet_pmos.sp

14
 NCFET\Negative Capacitance FET Model 1.1.0 HSPICE
Netlists\ncfet_inverter_bsim4_Lg32nm\ncfet_inverter.sp

NCFET\Negative Capacitance FET Model 1.1.0 HSPICE

Netlists\ncfet_inverter_tran_bsim4_Lg32nm\ncfet_inverter.sp

NCFET\Negative Capacitance FET Model 1.1.0 HSPICE

Netlists\ncfet_nmos_mvs_Lg45nm\ncfet_nmos.sp

NCFET\Negative Capacitance FET Model 1.1.0 HSPICE

Netlists\ncfet_pmos_mvs_Lg45nm\ncfet_pmos.sp

NCFET\Negative Capacitance FET Model 1.1.0 HSPICE

Netlists\ncfet_inverter_mvs_Lg45nm\ncfet_inverter.sp

NCFET\Negative Capacitance FET Model 1.1.0 HSPICE

Netlists\ncfet_nmos_bsim4_Lg45nm\ncfet_nmos.sp
…………………………………

3. Compilation of the files will generate the filename.sw0 and filename.tr0 files for dc and
transient simulations respectively. These files can be analyzed using the
perform_analysis.m file.

4. Go to the folder containing the “perform_analysis.m” file and run it.

Usage Notes and Known Issues

1. The MVS model produces identically zero drain current at zero voltage when simulated
by HSpice and Spectre. When the Negative capacitor is included, the combined model
still produces the zero drain-current at zero voltage in Spectre, but the current is small
(but non-zero) for Hspice simulation, see Fig. 10(a). Apparently, this is a numerical
issue, but none of the results will be substantially affected by the numerical issue.

2. We find the BSIM4 model produces a small but non-zero current even as a standalone
model, see Fig. 10(b). The effect propagates into the NC-FET. Again, the current is too
small to affect any result in any meaningful way.

15
 VD=0 V LG= 45 nm
0
10
MVS -4
10

ID [A/m]
4 -8 BSIM4
(a) 10 10
-12
10 (b) 10
4

0 2
10 -16
10 10
-20
10 0
-4 10
ID [A/m]

ID [A/m]
10 P(VDF-TrFE) 0.4 0.42 0.44
-2
VG(NC) [V]
-8 10
10 tFE=10 nm -4
-12 10
10 -6
-16
10
10 10
-8
-20 -10
10 10
0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6
VG(NC) [V] VG(MOS) [V]
Fig. 10 (a) ID vs VGS characteristics of the NMOS NC-FET from MVS and Landau theory at VD=0
V. (b) ID vs VGS characteristics of the NMOS MOSFET from BSIM4 at VD=0 V.

16