VM-

Paging example(single level)

Main Memory 4GB (232) Frame No offset
Frame size 256KB (218) 14-bit 18-bit

CPU address 24bit(Virtual address space) Page No offset

page size 256KB 6-bit 18-bit

Page mapping table is NOT shown but frame-numbers are given corresponding to page index (offset)
(If the frame-number is not present for given page index -marked as No Frame)

VA page No offset framenumber PA page status

8B4567 22 34567 1869 61A74567 No FAULT
334873 C 34873 1CFF 73FF4873 No FAULT
E8944A 3A 944A 1F29 7CA4944A No FAULT
E87CCD 3A 7CCD 17AB 5EAC7CCD No FAULT
B141F2 2C 141F2 No Frame ------- Page FAULT
E2A9E3 38 2A9E3 7C 1F2A9E3 No FAULT
D062C2 34 62C2 27F8 9FE062C2 No FAULT
16231B 5 2231B DE7 379E231B No FAULT
EF438D 3B 3438D 255A 956B438D No FAULT
9CF92E 27 F92E 233 8CCF92E No FAULT
EFD79F 3B 3D79F 79A 1E6BD79F No FAULT
6AFB66 1A 2FB66 No Frame ------- Page FAULT
9B500D 26 3500D 3A31 E8C7500D No FAULT
83E458 20 3E458 195A 656BE458 No FAULT
6C6125 1B 6125 3105 C4146125 No FAULT
1DA317 7 1A317 1AE9 6BA5A317 No FAULT
63845E 18 3845E 3DAB F6AF845E No FAULT
838CB2 20 38CB2 20C6 831B8CB2 No FAULT
9A769B 26 2769B 2454 9152769B No FAULT
A88611 2A 8611 1D82 76088611 No FAULT

How works- VA page No offset

8B4567 bit 10 0010 11 0100 0101 0110 0111 split VA in page No. And offset
hex 22 34567
frame-number
1869 bit 01 1000 0110 1001 search frame-number at index (page No) in
generate PA by shifting frame-number 18-bits left and add offset page mapping table
01 1000 0110 1001 11 0100 0101 0110 0111
61A74567 0110 0001 1010 0111 0100 0101 0110 0111

Effective memory access time (not considering cache or TLB)

MM access time is 100ns and page fault service time (penalty) of 8 ms, if 0.1% page fault occurs
Tav= 100+0.001(8000000) = 8.1 microsec

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 VM-

Segmentation example(single level)

Main Memory 4GB (2**32) contiguous memory space of 4GB

CPU address 24bit(Virtual address space) seg No offset

segment size 1024KB 4-bit 20-bit
(VM is smaller than PA)

Segment mapping table is NOT shown but base-addresses and segment length are given corresponding to segment index (offset)
(If the base-address is not present or seg offset > seg length for given seg index -marked as segmentFault)
VA segment No offset base address segment length PA Seg status
95F874 9 5F874 8138641 FF708 8197EB5 No FAULT
3DBD3D 3 DBD3D 737B8DDC AF755 ------- Seg FAULT
221A70 2 21A70 4516DDE9 6CB3E 4518F859 No FAULT
4FD4A1 4 FD4A1 419AC241 7FE38 ------- Seg FAULT
BADFC 0 BADFC 5072367 485BE ------- Seg FAULT
465F01 4 65F01 7724C67E 8305B 772B257F No FAULT
63B9EA 6 3B9EA 5E884ADC AD889 5E8C04C6 No FAULT
517796 5 17796 580BD78F EA58B 580D4F25 No FAULT
55585C 5 5585C 70A64E2A 3498E ------- Seg FAULT
487CB0 4 87CB0 1D4ED43B A0E20 1D5750EB No FAULT
D89A32 D 89A32 57E4CCAF D94E2 57ED66E1 No FAULT
588F54 5 88F54 542289EC 921F6 542B1940 No FAULT
437FDB 4 37FDB 7644A45C FFC31 76482437 No FAULT
4A481A 4 A481A 579478FE AC28C 579EC118 No FAULT
C240FB C 240FB 1BA026FA 1E644 ------- Seg FAULT
C6C33A C 6C33A 12E685FB 6AC35 ------- Seg FAULT
EEDD1 0 EEDD1 374A3FE6 EF4F9 37592DB7 No FAULT
F9C13C F 9C13C 649BB77C ACA09 64A578B8 No FAULT
386575 3 86575 1CF10FD8 1173E ------- Seg FAULT
5BA861 5 BA861 47398C89 FED4D 474534EA No FAULT

How works- VA segment No offset

95F874 bit 1001 0101 1111 1000 0111 0100 split VA in segment No. And offset
hex 9 5F874
offset is less the segment length (FF708)

seg base address 8138641 generate PA by adding offset Search base-address at index (seg No) in
ADD offset oo5F874 in segment base address segment mapping table
PA 8197EB5

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Q1
Segmentation(single level) problem
Main Memory 256MB (228)

CPU address 32bit(Virtual address space) (VM is greater than PA)

segment size 256MB
calculate/fill this table
VA segment No offset base address segment length PA Seg status
7C3DBD3D 7 C3DBD3D 37B8DDC CEAF08D
22221A70 2 2221A70 516DDE9 6C841
614FD4A1 6 14FD4A1 19AC241 577F8E6
440BADFC 4 40BADFC 5072367 8048241
77465F01 7 7465F01 724C67E C482A9C
2463B9EA 2 463B9EA E884ADC 1EAD370
2D517796 2 D517796 80BD78F 53EA439
3855585C 3 855585C A64E2A A2342F2
2A487CB0 2 A487CB0 D4ED43B 25A0702

Q2
Paging(single level) problem
Main Memory 4PB (252)
Frame size 4MB (222)
CPU address 32bit(Virtual address space)
Q2a
calculate/fill this table
VA page No offset frame-number PA page status
6B8B4567 1AE B4567 243C9869
66334873 198 334873 19495CFF
2AE8944A AB 28944A 238E1F29
46E87CCD 11B 287CCD 107ED7AB
2EB141F2 BA 3141F2 No Frame
5BD062C2 16F 1062C2 DB127F8
216231B 8 16231B 1190CDE7
66EF438D 19B 2F438D 3352255A

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 VM-april-2017

Q2 b Repeat Q2a for given TLB

Four entries with 2-way set associative
Paging(single level) CPU address for VA
Main Memory 4PB (252) page No offset
Frame size 4MB (222) 10 22
CPU address 32bit(Virtual address space) (interpretation of CPU address to TLB, similar to cache)
CPU address to TLB
(TLB data is given below for above paging problem Q2) tag set offset
TLB 9 1 22
tag V D frame-number Four entries with 2-way set associative
01 1001 100 1 0 19495CFF Set 0
00 0000 100 1 0 1190CDE7
00 1010 101 1 0 238E1F29 Set 1
01 0001 101 1 0 107ED7AB
TLB is updated for every miss
Q3
Assume- TLB access time is 2ns, Page table time is 120ns(as PT in memory),cache access time 5ns
Calculate memory access time for first four VA given in paging problem Q2 in above sheet
(Assume here-Cache is 100% hit .When TLB miss occurs ,memory is accessed twice before getting PA for cache)
Q4a
Draw CPU address format to 8-lines direct mapped TLB
Fill the 8-line direct mapped TLB with data given in above paging problem Q2
Q4b
Draw CPU address format to 8-lines 2-way set associative TLB
Fill the 8-line 2-way set associtive TLB with data given in above paging problem Q2

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