Sequential Logic

Sequential logic refers to a type of digital logic circuit that uses

memory elements to store information.

It consists of a combinational circuit to which storage elements are

connected to form a feedback path. The storage elements are devices
capable of storing binary information.

a sequential circuit is specified by a time sequence of inputs, outputs,

and internal states.
Differentiate between combinational logic and sequential logic

The storage elements (memory) used in clocked sequential circuits are

called flip-flops.

A flip-flop is a binary storage device capable of storing one bit of

information.

Storage Elements: 1)
Latches:

Latches are digital circuits that serve as basic building blocks in the
construction of sequential logic circuits.

They are bi-stable, meaning they have two stable states and can be
used to store binary information. Latches are often used for
temporary storage of data within a digital system.

There are several types of latches, with the most common being the
1) SR latch (Set-Reset latch), 2) D latch (Data latch),3) JK latch.
Storage elements that operate with signal levels (rather than signal
transitions) are referred to as latches; those controlled by a clock
transition are flip-flops. Latches are said to be level sensitive
devices; flip-flops are edge-sensitive devices. The two types of storage
elements are related because latches are the basic circuits from
which all flip- flops are constructed.

SR Latch (Set-Reset Latch):

The SR latch has two inputs, S (Set) and R (Reset).It has two outputs,
Q and ~Q (complement of Q).
When S is asserted, Q is set to 1, and when R is asserted, Q is reset
to 0.The SR latch is sensitive to the input conditions, and having both
S and R asserted simultaneously can lead to unpredictable behavior.

SR Latch with nor gates

Where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR logic gates.
The stored bit is present on the output marked Q.
While the S and R inputs are both low, feedback maintains the Q and Q outputs in a constant state,
with Q the complement of Q. If S (Set) is pulsed high while R (Reset) is held low, then the Q output is forced
high, and stays high when S returns to low; similarly, if R is pulsed high while S is held low, then the Q
output is forced low, and stays low when R returns to low.

SR latch with control input

It consists of the basic SR latch and two additional NAND gates. The control input En
acts as an enable signal for the other two inputs. The outputs of the NAND gates stay
at the logic-1 level as long as the enable signal remains at 0. This is the quiescent
condition for the SR latch. When the enable input goes to 1, information from the S or
R input is allowed to affect the latch. The set state is reached with S = 1, R = 0, and
En = 1 active-high enabled). To change to the reset state, the inputs must be S = 0, R
= 1, and En = 1. In either case, when En returns to 0, the circuit remains in its
current state. The control input disables the circuit by applying 0 to En, so that the
state of the output does not change regardless of the values of S and R. Moreover,
when En = 1 and both the S and R inputs are equal to 0, the state of the circuit does
not change. These conditions are listed in the function table accompanying the
diagram.
D latch (transparent latch)
A D latch can store a bit value, either 1 or 0. When its Enable pin is HIGH, the value
on the D pin will be stored on the Q output.
The D Latch is a logic circuit most frequently used for storing data in digital systems.
It is based on the S-R latch, but it have an or state
problem.

One way to eliminate the undesirable condition of the indeterminate state in the
SR latch is to ensure that inputs S and R are never equal to 1 at the same time.
This is done in the D latch, shown in Fig. 5.6. This latch has only two inputs: D
(data) and En (enable). The D input goes directly to the S input, and its
complement is applied to the R input. As long as the enable input is at 0, the
cross-coupled SR latch has both inputs at the 1 level and the circuit cannot
change state regardless of the value of D. The D input is sampled when En = 1.
If D = 1, the Q output goes to 1, placing the circuit in the set state. If D = 0,
output Q goes to 0, placing the circuit in the reset state.

The graphic symbols for the various latches are shown in Fig. 5.7. A latch is
designated by a rectangular block with inputs on the left and outputs on the
right. One output designates the normal output, and the other (with the bubble
designation) designates the complement output

STORAGE ELEMENTS: FLIP FLOPS

Flip-flops are fundamental building blocks in digital electronics and

sequential logic circuits.

They are bi-stable multivibrators, like latches, but they are edge-
triggered and use a clock signal to control the timing of state changes.

Flip-flops are widely used for storing binary information in electronic

systems.

Edge triggered DFF

The construction of a D flip-flop with two D latches and an inverter is shown in
Fig. 5.9. The first latch is called the master and the second the slave. The
circuit samples the D input and changes its output Q only at the negative edge
of the synchronizing or controlling clock (designated as Clk ). When the clock is
0, the output of the inverter is 1. The slave latch is enabled, and its output Q is
equal to the master output Y. The master latch is disabled because Clk = 0.
When the input pulse changes to the logic-1 level, the data from the external D
input are transferred to the master. The slave, however, is disabled as long as
the clock remains at the 1 level, because its enable input is equal to 0. Any
change in the input changes the master output at Y, but cannot affect the slave
output. When the clock pulse returns to 0, the master is disabled and is isolated
from the D input. At the same time, the slave is enabled and the value of Y is
transferred to the output of the flip-flop at Q . Thus, a change in the output of
the flip-flop can be triggered only by and during the transition of the clock from
1 to 0.

Comparison between Latch and Flipflop

 Construction of a positive edge-triggered D flip-flop uses three SR latches

Clk D S R Q

0 1
Assume(previous output)
0 0 1 1 0 1

No Change
0 1 1 1 No Change

1 1 0 1 1 0

0 0 1 1 No change

1 0 1 0 0 1

JK FLIPFLOP

When J = 1 and K = 0, D = + Q = 1, so the next clock edge sets the output to 1.

When J = 0 and K = 1, D = 0, so the next clock edge resets the output to 0.

When both J = K = 1 and D = Q, the next clock edge complements the output.

When both J = K = 0 and D = Q, the clock edge leaves the output unchanged.
T Flip-flop

T Flip-flop using JK Flip-flop

T = 0 (J = K = 0), a clock edge does not change the output. When T = 1 (J = K = 1), a
clock edge complements the output. The complementing flip-flop is useful for
designing binary counters.

Implementation of TFF using DFF

The T flip-flop can be constructed with a D flip-flop and an exclusive-OR gate as

shown in Fig. (b). The expression for the D input is D = T Q= + When T =
the output
complements.

D=T^Q
 Characteristic tablesA characteristic table defines the logical properties of a flip-flop by
describing its operation in tabular form. They define the next state (i.e., the state that results
from a clock transition) as a function of the inputs and the present state

Q(t) denotes the state of the flip-flop immediately before the clock edge, and

Q(t + 1) denotes the state that results from the clock transition.

Characteristic equation

It is the Boolean expression in terms of its input and output which determines
the next state of the flipflop.

T FF
DFF

JKFF

Write Verilog code for Flipflops

SR flip-flop JK Flip-flop
D flip-flop T Flip-flop

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