LABORATORY MANUAL

Lab Course name Digital Electronics Lab

Lab Course code 21BTCS382
Semester III
Academic year 2023-24
Course Coordinator Upendra Verma
Program name B. Tech
School SoCSE

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Lab Course Objectives:

Sr. No. Objectives

Understand Boolean expressions and realize them using logic gates.

1

Design and implementation of various combinational circuits using logic

2
gates/universal gates.

Design and implementation of various sequential circuits using logic gates and
3
flip flops.

Lab Course Outcomes:

Course Outcome no. Course Outcomes

Understand Boolean expressions and realize them using logic

Lab Course code.1
gates.

Design and implementation of various combinational circuits

Lab Course code.2
using logic gates/universal gates.

Understand the flip-flops and Latches

Lab Course code.3

Design and implementation of various sequential circuits using

Lab Course code.4
logic gates and flip flops.

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 LIST OF EXPERIMENTS

Sr. No. Title of Experiment Pg. No.

1 Simplify the given Boolean expression and to realize them

using logic gates/universal gates.

2 Design and implementation of half adder and subtracter

using logic gates/universal gates.

3 Design and implementation of full adder and subtracter

using logic gates/universal gates.

4 Design and implementation of i) parallel adder/subtracter

and ii) BCD-to- excess-3code converter and vice versa.

5 Design and implementation of code conversion from

gray-to- binary and vice-versa.

6 Design and implementation of full adder/subtracter and

code converters using i) multiplexer and ii) decoder IC‟s.

7 Design and implementation of one bit, two bit and

magnitude comparators.

8 Implementation of i) priority encoders and ii) LED decoder

driver circuit.

9 Design and verify the 4-bit synchronous counter.

10 Design and verify the 4-bit asynchronous counter.

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 EXPERIMENT NO.: 1

Title of Experiment:

Simplify the given Boolean expression and to realize them using logic gates/universal gates.

Aim/Objectives: To simplify a Boolean expression and realize it using logic gates.

Apparatus required: Trainer kit, Logic gate ICs, Connecting wires.
Learning Outcome: Understand to simplify a Boolean expression and realize it using logic gates.
Theory/Principle: Gates are the fundamental building blocks of digital logic circuitry. These

devices function by “opening” or “closing” to admit or reject the passage of

a logical signal. From only a handful of basic gate types (AND, OR, XOR,

and NOT), a vast array of gating functions can be created.

Diagram:

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 Various gate symbols.
Procedure/Algorithm: 1. F=A‟B‟C+A‟BC+AB‟

2. Choose correct ICs

3. Make connections according to (a) given expression and (b) after

simplification.

4. Turn on power supply

5. Verify truth table.

Code/Program: NA
Observations: Verify result with truth table.
Calculations: NA
Precautions: 1. Connection must be correct.

2. Avoid any loose connections.

3. Make sure all the ICs, LEDs, input supply are properly working.
Results: Boolean expression has been realized using logic gates.
Viva questions: 1. How many pins are there in 74 series ICs?

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 2. Which pins are used for power supply to ICs of 74 series?

3. Give the truth table of NAND and XNOR gate?

4. What maximum voltage can be applied on 74 series ICs?

Applications/Significance: Realization of various digital logics.

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 EXPERIMENT NO.: 2

Title of Experiment:

Design and implementation of halfadder and subtracter using logic gates/universal gates.

Aim/Objectives: Design and implementation of halfadder and subtracter using logic

gates/universal gates.
Apparatus required: Trainer kit, Logic gate ICs, Connecting wires.
Learning Outcome: Understand to simplify a Boolean expression of a combinational circuit and

realize it using logic gates.

Theory/Principle:
Half Adder

A logic circuit used for adding two 1-bit numbers or simply two bits is
called as a Half Adder circuit. This circuit has two inputs and two
outputs. The inputs are the two 1-bit binary numbers (known as Augend
and Addend) and the outputs are Sum and Carry.

Half Subtractors

A Half Subtractor is a multiple output Combinational Logic Circuit that

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 does the subtraction of two 1-bit binary numbers. It has two inputs and
two outputs. The two inputs correspond to the two 1-bit binary numbers
and the two outputs corresponds to the Difference bit and Borrow bit (in
contrast to Sum and Carry in Half Adder).

Diagram:

Procedure/Algorithm: 1. Choose correct ICs

2. Make connections according to circuit diagram

3. Turn on power supply

4. Verify truth table.

Code/Program: NA
Observations: Verify result with truth table.
Calculations: NA
Precautions: 1. Connection must be correct

2. Avoid any loose connections.

3. Make sure all the ICs, LEDs, input supply are properly working.
Results: Halfadder and subtracter have been implemented using logic
gates/universal gates.
Viva questions: 1. What is half adder and half substractor?

2. Give the truth table of half adder.

3. Write the truth table of half substractor.

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 4. Give the gate implementation of half adder.

5. Give the gate implementation of half substractor .

Applications/Significance: Understand the concept of basic building block of digital systems.

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 EXPERIMENT NO.: 3

Title of Experiment:

Design and implementation of full adder and subtracter using logic gates/universal gates.

Aim/Objectives: Design and implementation of full adder and subtracter using logic
gates/universal gates.
Apparatus required: Trainer kit, Logic gate ICs, Connecting wires.
Learning Outcome: Understand to Design and implementation of full adder and subtracter

using logic gates/universal gates

Theory/Principle:
Full Adder

A Full Adder is a combinational logic circuit which performs addition

on three bits and produces two outputs: a Sum and a Carry. As we have
seen that the Half Adder cannot respond to three inputs and hence the
full adder is used to add three digits at a time.

It consists of three inputs, of which two are input variables representing

the two significant bits to be added, whereas the third input terminal is
the carry from the previous addition. The two outputs are a Sum and
Carry outputs.

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 Full Subtractor

A Full Subtractor is a combinational logic circuit which performs a

subtraction between the two 1-bit binary numbers and it also considers
the borrow of the previous bit i.e., whether 1 has been borrowed by the
previous minuend bit.

So, a Full Subtractor has three inputs, in which two inputs

corresponding to the two bits to be subtracted (minuend A and
subtrahend B), and a borrow bit, usually represented as BIN,
corresponding to the borrow operation. There are two outputs, one
corresponds to the difference D output and the other Borrow output BO.

Diagram:

Procedure/Algorithm: 1. Choose correct ICs

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 2. Make connections according to circuit diagram

3. Turn on power supply

4. Verify truth table.

Code/Program: NA
Observations: Verify result with truth table.
Calculations: NA
Precautions: 1. Connection must be correct.

2. Avoid any loose connections.

3. Make sure all the ICs, LEDs, input supply are properly working.
Results: Fulladder and subtracter have been implemented using logic
gates/universal gates.
Viva questions: 1. What is half adder and full substractor?

2. Give the truth table of full adder.

3. Write the truth table of full substractor.

4. Give the gate implementation of full adder.

5. Give the gate implementation of full substractor .

Applications/Significance: Understand the concept of basic building block of digital systems.

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 EXPERIMENT NO.: 4

Title of Experiment:

Design and implementation of i) parallel adder/subtracter and ii) BCD-to- excess-3code converter and vice
versa.

Aim/Objectives: Design and implementation of i) parallel adder/subtracter and ii)

BCD-to- excess-3code converter and vice versa.
Apparatus required: Trainer kit, Logic gate ICs, Connecting wires.
Learning Outcome: Understand to simplify Design and implementation of i) parallel

adder/subtracter and ii) BCD-to- excess-3code converter and vice

versa.
Theory/Principle:
Parallel Binary Adders

As we discussed, a single Full Adder performs the addition of two one

bit numbers and also the carry input. For performing the addition of
binary numbers with more than one bit, more than one full adder is
required and the number of Full Adders depends on the number bits.
Thus, a Parallel Adder, is a combination of Multiple Full Adders and is
used for adding all bits of the two numbers simultaneously.

By connecting „n‟ number of full adders in parallel, an n-bit Parallel

Adder can be constructed. From the below figure, it is to be noted that
there is no carry at the least significant position, hence we can use either
a half adder or make the carry input of full adder as zero at this position.

The following figure shows a Parallel 4-bit Binary Adder, which has
three full adders and one half adder. The two binary numbers to be
added are „A3 A2 A1 A0„ and „B3 B2 B1 B0„ , which are applied to the
corresponding inputs of the Full Adders. This parallel adder produces
their result as „C4 S3 S2 S1 S0„ , where C4 is the final carry.

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Parallel Binary Subtractors

To perform the subtraction of binary numbers with more than one bit,
we have to use the Parallel Subtractors. This parallel subtractor can be
designed in several ways, including combination of half and full
subtractors, all full subtractors, all full adders with subtrahend
complement input, etc.

The below figure shows a 4 bit Parallel Binary Subtractor formed by

connecting one half subtractor and three full subtractors.

In this subtractor, 4 bit minuend „A3 A2 A1 A0„ is subtracted by 4 bit

subtrahend „B3 B2 B1 B0„ and the result is the difference output „D3
D2 D1 D0„ . The borrow output of each subtractor is connected as the
borrow input to the next subtractor.

ii) BCD to Excess-3 conversion

To understand the process of converting BCD to Excess-3, it is required

to have knowledge of Number System and Number Base Conversion.

The Excess-3 binary code is an example of a self-complementary BCD

code. A self-complementary binary code is a code which is always
complimented in itself. By replacing the bit 0 to 1 and 1 to 0 of a
number, we find the 1's complement of the number. The sum of the 1'st

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complement and the binary number of a decimal is equal to the binary
number of decimal 9.

The process of converting BCD to Excess-3 is quite simple from other

conversions. The Excess-3 code can be calculated by adding 3, i.e.,
0011 to each four-digit BCD code. Below is the truth table for the
conversion of BCD to Excess-3 code. In the below table, the variables
A, B, C, and D represent the bits of the binary numbers. The variable 'D'
represents the LSB, and the variable 'A' represents the MSB. In the
same way, the variables w, x, y, and z represent the bits of the Excess-3
code. The variable 'z' represents the LSB, and the variable 'w' represents
the MSB. The 'don't care conditions' is expressed by the variable 'X'.

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Diagram:

Procedure/Algorithm: 1. Choose correct ICs

2. Make connections according to circuit diagram

3. Turn on power supply

4. Verify truth table.

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Code/Program: NA
Observations: Verify result with truth table.
Calculations: NA
Precautions: 1. Connection must be correct.

2. Avoid any loose connections.

3. Make sure all the ICs, LEDs, input supply are properly working.
Results: Binary adder, subtracter, and BCD to Ex-3 convertor have been
implemented using logic gates/universal gates.
Viva questions: 1. What is binary adder and binary substractor?

2. How can you achieve binary adder and binary substractor from a

single circuit?

3. What is BCD code.

4. Give the truth table for BCD to Ex-3 conversion.

5. Give the truth table for Ex-3 to BCD conversion.

Applications/Significance: Understand the concept of basic building block of various code conversions.

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 EXPERIMENT NO.: 5

Title of Experiment:

Design and implementation of code conversion from gray-to- binary and vice-versa.

Aim/Objectives: Design and implementation of code conversion from gray-to- binary

and vice-versa.
Apparatus required: Trainer kit, Logic gate ICs, Connecting wires.
Learning Outcome: Understand to simplify Design and implementation of code conversion

from gray-to- binary and vice-versa.

Theory/Principle:
Binary to Gray code conversion

The Binary to Gray code converter is a logical circuit that is used to

convert the binary code into its equivalent Gray code. By putting the
MSB of 1 below the axis and the MSB of 1 above the axis and reflecting
the (n-1) bit code about an axis after 2n-1 rows, we can obtain the n-bit
gray code.

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Diagram:

Procedure/Algorithm: 1. Choose correct ICs

2. Make connections according to circuit diagram

3. Turn on power supply

4. Verify truth table.

Code/Program: NA
Observations: Verify result with truth table.
Calculations: NA
Precautions: 1. Connection must be correct.

2. Avoid any loose connections.

3. Make sure all the ICs, LEDs, input supply are properly working.
Results: BCD to Gray convertor has been implemented.
Viva questions: 1. What is Gray code.

2. What is BCD code.

3. Give the truth table for BCD to Gray conversion.

4. Give the truth table for Gray to BCD conversion.

5. Give corresponding circuit diagram.

Applications/Significance: Understand the concept of basic building block of gray to bcd and vise versa

conversions.

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 EXPERIMENT NO.: 6

Title of Experiment:

Design and implementation of full adder/subtracter and code converters using i) multiplexer and ii) decoder
IC‟s.

Aim/Objectives: Design and implementation of full adder/subtracter and code

converters using i) multiplexer and ii) decoder IC‟s.
Apparatus required: Trainer kit, Logic gate ICs, Connecting wires.
Learning Outcome: Understand to simplify Design and implementation of full
adder/subtracter and code converters using i) multiplexer and ii)
decoder IC‟s.
Theory/Principle: For Sum - f(A,B,C-In)=Σ(1,2,4,7)
For Carry:- f(A,B,C-In)=Σ(3,5,6,7)
Using Multiplexer

Using Decoder:

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Diagram:

Procedure/Algorithm: 1. Choose correct ICs

2. Make connections according to circuit diagram

3. Turn on power supply

4. Verify truth table.

Code/Program: NA
Observations: Verify result with truth table.
Calculations: NA
Precautions: 1. Connection must be correct.

2. Avoid any loose connections.

3. Make sure all the ICs, LEDs, input supply are properly working.
Results: Implementation of full adder has been done using i) multiplexer and ii)
decoder IC‟s.
Viva questions: 1. What is multiplexer?

2. Give the Boolean function for it.

3. What is decoder?

4. Give the Boolean function for 1:2 decoder.

5. Give the circuit for implementing 8:1 mux using 2:1 mux.
Applications/Significance: Understand the application of mux and decoder.

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 EXPERIMENT NO.: 7

Title of Experiment:

Design and implementation of one bit, two bit and magnitude comparators.

Aim/Objectives: Design and implementation of one bit, two bit and magnitude
comparators.
Apparatus required: Trainer kit, Logic gate ICs, Connecting wires.
Learning Outcome: Understand to simplify Design and implementation of one bit, two bit

and magnitude comparators.

Theory/Principle:
Digital Comparator

The Digital Comparator is another very useful combinational logic

circuit used to compare the value of two binary digits

There are two main types of Digital Comparator available and these
are.

 1. Identity Comparator – an Identity Comparator is a digital

comparator with only one output terminal for when A = B, either
A = B = 1 (HIGH) or A = B = 0 (LOW)
 2. Magnitude Comparator – a Magnitude Comparator is a
digital comparator which has three output terminals, one each
for equality, A = B greater than, A > B and less than A < B

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When we are comparing two binary or BCD values or variables against
each other, we are comparing the “magnitude” of these values, a logic
“0” against a logic “1” which is where the term Magnitude
Comparator comes from.

As well as comparing individual bits, we can design larger bit

comparators by cascading together n of these and produce a n-bit
comparator just as we did for the n-bit adder in the previous tutorial.
Multi-bit comparators can be constructed to compare whole binary or
BCD words to produce an output if one word is larger, equal to or less
than the other.

Some commercially available digital comparators such as the TTL

74LS85 or CMOS 4063 4-bit magnitude comparator have additional
input terminals that allow more individual comparators to be
“cascaded” together to compare words larger than 4-bits with
magnitude comparators of “n”-bits being produced.

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Diagram:

Procedure/Algorithm: 1. Choose correct ICs

2. Make connections according to circuit diagram

3. Turn on power supply

4. Verify truth table.

Code/Program: NA
Observations: Verify result with truth table.
Calculations: NA
Precautions: 1. Connection must be correct.

2. Avoid any loose connections.

3. Make sure all the ICs, LEDs, input supply are properly working.
Results: One bit, two bit and magnitude comparators have been implemented.
Viva questions: 1. What is the IC no. for 4 Bit digital comparator?

2. How can you make 2 bit magnitude comparator using 4bit

comparator?

3. Give the truth table digital comparator for 1 bit.

4. What the types of a digital comparator circuit?

Applications/Significance: Understanding of digital comparator circuits.

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 EXPERIMENT NO.: 8

Title of Experiment:

Implementation of i) priority encoders and ii) LED decoder driver circuit.

Aim/Objectives: Implementation of i) priority encoders and ii) LED decoder driver

circuit.
Apparatus required: Trainer kit, ICs, Connecting wires.
Learning Outcome: Understand to Implementation of i) priority encoders and ii) LED

decoder driver circuit.

Theory/Principle:
Priority Encoder

The priority encoders output corresponds to the currently active input

which has the highest priority. So when an input with a higher priority is
present, all other inputs with a lower priority will be ignored.

Priority encoders are available in standard IC form and the TTL

74LS148 is an 8-to-3 bit priority encoder which has eight active LOW
(logic “0”) inputs and provides a 3-bit code of the highest ranked input
at its output.

Binary Decoders

These circuits in IC form are often called Decoders/Demultiplexers and

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 perform the opposite function to an encoder (or multiplexer).

Binary data is used in digital circuits in the form of one or another

binary code, which is an arrangement of the binary bits in a particular
order to represent „real‟ quantities such as a set of decimal numbers
(BCD code) or text (ASCII). In a complete digital system therefore it is
often necessary to convert one code to another, or to convert a binary
code to drive some user interface such as a LED display.

A decoder is a combinational logic circuit that takes a binary input,

usually in a coded form, and produces a one-bit output, on each of a
number of output lines. The logic state (1 or 0) on any of the output lines
depends on a particular code appearing on the input lines.
Diagram:

Procedure/Algorithm: 1. Choose correct ICs

2. Make connections according to circuit diagram

3. Turn on power supply

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 4. Verify truth table.
Code/Program: NA
Observations: Verify result with truth table.
Calculations: NA
Precautions: 1. Connection must be correct.

2. Avoid any loose connections.

3. Make sure all the ICs, LEDs, input supply are properly working.
Results: Implementation of i) priority encoders and ii) LED decoder driver
circuit has been done.
Viva questions: 1. What is encoder?

2. What do you mean by priority encoder?

3. Write the advantage of priority encoder.

4. What is decoder?

5. Give application of encoders and decoders.

Applications/Significance: Understand basics of encoder/decoders.

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 EXPERIMENT NO.: 9

Title of Experiment:

Design and verify the 4-bit synchronous counter.

Aim/Objectives: Design and verify the 4-bit synchronous counter.

Apparatus required: Trainer kit, 74193 ICs, Connecting wires.
Learning Outcome: Understand to Design and verify the 4-bit synchronous counter.
Theory/Principle:
Synchronous Counter

Synchronous Counters are so called because the clock input of all the
individual flip-flops within the counter are all clocked together at the
same time by the same clock signal.

Synchronous Counter, the external clock signal is connected to the

clock input of EVERY individual flip-flop within the counter so that all
of the flip-flops are clocked together simultaneously (in parallel) at the
same time giving a fixed time relationship. In other words, changes in
the output occur in “synchronisation” with the clock signal.

The result of this synchronisation is that all the individual output bits
changing state at exactly the same time in response to the common
clock signal with no ripple effect and therefore, no propagation delay.

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Diagram:

Procedure/Algorithm: 5. Choose correct ICs

6. Make connections according to circuit diagram

7. Turn on power supply

8. Verify truth table.

Code/Program: NA
Observations: Verify result with truth table.
Calculations: NA
Precautions: 6. Connection must be correct.

7. Avoid any loose connections.

8. Make sure all the ICs, LEDs, input supply are properly working.
Results: 4-bit synchronous counter has been implemented and verified.
Viva questions: 1. What are counters in digital electronics?

2. Write the applications of it.

3. What are the types of counters?

4. What do you mean by synchronous counters?

Applications/Significance: Understand the basics of counters.

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 EXPERIMENT NO.: 10

Title of Experiment:

Design and verify the 4-bit asynchronous counter.

Aim/Objectives: Design and verify the 4-bit asynchronous counter.

Apparatus required: Trainer kit, 74196 ICs, Connecting wires.
Learning Outcome: Understand to Design and verify the 4-bit asynchronous counter.
Theory/Principle: An Asynchronous counter can have 2n-1 possible counting states e.g.

MOD-16 for a 4-bit counter, (0-15) making it ideal for use in Frequency

Division applications. But it is also possible to use the basic asynchronous

counter configuration to construct special counters with counting states less

than their maximum output number.

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Diagram:

Procedure/Algorithm: 1. Choose correct ICs

2. Make connections according to circuit diagram

3. Turn on power supply

4. Verify truth table.

Code/Program: NA
Observations: Verify result with truth table.
Calculations: NA
Precautions: 1. Connection must be correct.

2. Avoid any loose connections.

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 3. Make sure all the ICs, LEDs, input supply are properly working.
Results: 4-bit asynchronous counter has been implemented and verified.
Viva questions: 1. What is decade counter in digital electronics?

2. How can you say a counter is a frequency divider?

3. What are the types of counters?

5. What do you mean by asynchronous counters?

Applications/Significance: Understand the basics of counters.

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