IJE TRANSACTIONS C: Aspects Vol. 32, No.

3, (March 2019) 381-392

International Journal of Engineering

Journal Homepage: www.ije.ir

Reversible Logic Multipliers: Novel Low-cost Parity-Preserving Designs

F. Eslami-Chalandar, M. Valinataj*, H. Jazayeri

School of Electrical and Computer Engineering, Babol Noshirvani University of Technology, Babol, Iran

PAPER INFO A B S T R A C T

Paper history:
Received 05 April 2018
Reversible logic is one of the new paradigms for power optimization that can be used instead of the
Received in revised form 27 February 2019 current circuits. Moreover, the fault-tolerance capability in the form of error detection or error correction
Accepted 07 March 2019 is a vital aspect for current processing systems. In this paper, as the multiplication is an important
operation in computing systems, some novel reversible multiplier designs are proposed with the parity-
preserving property which will be useful for error detection. At first, two optimal signed serial multipliers
Keywords: are presented based on the Booth’s algorithm and its enhanced version called the K-algorithm, utilizing
Reversible Logic the new arrangements of reversible gates. Then, another low-cost serial multiplier is proposed based on
Parity-Preserving Gates the conventional Add & Shift method to be utilized in the applications in which unsigned numbers are
Multiplication
used. Finally, a new signed parallel multiplier is proposed based on the Baugh -Wooley method that is
Booth’s Algorithm
Error Detection
useful for speed-critical applications. The comparative results showed that the proposed multipliers are
Fault-Tolerance much better than the existing designs regarding the main criterions used in reversible logic circuits
including quantum cost, gate count, constant inputs, and garbage outputs.
doi: 10.5829/ije.2019.32.03c.05

1. INTRODUCTION1 Similar to irreversible circuits, reversible circuits are

fault-prone in their operations because a fault inside a
Generally, the VLSI circuits are built using irreversible reversible gate caused by an environmental effect can
gates and circuits that always lead to power dissipation. corrupt the resultant output vector which makes the input
It is proved in literature [1] that each bit in irreversible vector not to be recovered from the output vector, and the
logic consumes at least kTln2 Joules of energy in which information is lost. Therefore, the fault-tolerance
k is the Boltzmann’s constant and T is the absolute capability, at least in the form of fault or error detection,
temperature at which the computation is performed. is an important aspect in reversible circuits. A well-
Reversible logic is one of the best solutions to decrease known and low-cost method to detect errors is parity-
energy consumption since there is no energy dissipation based coding. However, in reversible gates and circuits,
in this kind of circuit as the internal power consumption this coding can be used in the form of parity-preserving
[2]. Reversible circuits are made of reversible gates, and characteristic. A gate having this characteristic is called
it is required that a one by one mapping exists between a parity-preserving reversible gate. In this type of
the input vector and the output vector of each gate or reversible gate, the parity of the input vector is equal to
circuit. This way, the number of outputs is equal to the the parity of the output vector. However, since fan-out
number of inputs, and the input vector can be retrieved and feedback are not allowed in reversible logic [3,4]; the
from the output vector. That means no information is lost implementation of this type of circuits is more difficult
in these circuits. This fact helps to decrease power compared to irreversible circuits.
consumption. Reversible circuits may have lots of The multiplication is one of the important arithmetic
applications in designing low power circuits, quantum operations in different computing systems including the
computing and nanotechnology although nowadays there quantum computers. Thus, designing a better multiplier
are some problems in the design of quantum circuits. with respect to different design aspects assists to reach a
more efficient processing system. Until now, different

*Corresponding Author Email: [email protected] (M. Valinataj)

Please cite this article as: F. Eslami-Chalandar, M. Valinataj, H. Jazayeri, Reversible Logic Multipliers: Novel Low-Cost Parity-Preserving Designs,
International Journal of Engineering (IJE), IJE TRANSACTIONS C: Aspects Vol. 32, No. 3, (March 2019) 381-392
382 F. Eslami-Chalandar et al. / IJE TRANSACTIONS C: Aspects Vol. 32, No. 3, (March 2019) 381-392

types of reversible multipliers have been designed [5-13]. In a reversible gate or circuit, the constant inputs are the
However, many of the designs are not fault-tolerant or inputs whose values do not change in a gate, and are
parity-preserving circuits. In this paper, some new low- maintained at either 0 or 1 in order to perform the
cost parity-preserving reversible multipliers are intended functions. These inputs are also added to a gate
proposed; in which more beneficial parity-preserving to make it reversible [18]. In addition, the outputs that
gates as well as better arrangements of the existing gates would not be used in the subsequent computations are
are exploited. The proposed multipliers include both called the garbage outputs. In other words, the garbage
serial and parallel architectures to be used for signed and outputs are needed just to maintain the circuit's
unsigned multiplications in different applications. These reversibility or to make it parity-preserving [19].
designs are based on different multiplication algorithms In a reversible circuit, the delay is defined as the
comprising the Booth’s algorithm and K-algorithm [14], maximu m number of gates on the paths from the inputs
Add & Shift, and Baugh-Wooley algorithm [15]. It is to the outputs [19]. Another parameter considered in
shown that the proposed multipliers have better design reversible circuits is the hardware complexity which is
parameters compared to previous reversible multipliers the number of AND, XOR and NOT operations,
especially with respect to quantum cost. separately, appeared in the output expressions. In other
The rest of the paper is organized as follows. In words, the hardware complexity shows the
section 2, some basic concepts and definitions as well as computational complexity of a reversible circuit that can
the parity-preserving reversible gates are described. In be important in some types of implementations . This
section 3 the related works are characterized. Sections 4 way, if α, β, and γ are the representatives for XOR, AND,
and 5 explain the proposed parity-preserving serial and and NOT operations in the outputs, respectively. Then,
parallel multipliers, respectively. The evaluation of the the hardware complexity i.e. H.C. can be computed
proposed reversible multipliers compared to the existing according to Equation (2):
designs is presented in s ection 6. Finally, some H.C.=N(α).α+N(β).β+N(γ). Γ (2)
conclusions are drawn in section 7.
In the above equation, N(*) is the number of *-type
operations in the output expressions.
2. BACKGROUND As stated in literature [20], in calculating the
hardware complexity, it would be desired and more
In this section, at first, we discussed the basic concepts precise if the common operations in the output
and definitions regarding reversible logic. Then, we expressions would be accounted once. Therefore, in this
introduced the parity-preserving reversible gates, paper, the calculation approach presented in literature
required for the next sections of this paper. [20] is used.
The most important parameter in designing the
2. 1. Basic Concepts and Definitions A reversible circuits is the quantum cost. This criterion is
reversible gate or circuit is an n×n circuit so that for any defined as the number of 1×1 and 2×2 quantum
n-tuple input vector, a unique n-tuple output vector will primitives required for implementing a reversible circuit.
appear at the circuit's output. Due to the fact that the input The NOT gate is the only 1×1 quantum primitive which
vector can be retrieved by the output vector, as well, we has the quantum cost of one unit. The quantum primitives
can write Iv ↔ Ov in which Iv = (I0 ,I1 ,…,In-1 ) and Ov = are used to build the reversible gates bigger than 2×2. In
(O0 ,O1 ,…,On-1 ) as the input and output vectors, a point of view, the reversible gates can be classified in
respectively. two general groups, parity-preserving reversible gates
A parity-preserving reversible gate is a gate in which the and non-parity-preserving reversible gates. In this paper,
parity of the inputs is equal to the parity of the outputs we are only dealing with the parity-preserving circuits;
according to the following equation: the main parity- preserving gates are introduced in the
following section.
I0⊕I1⊕…⊕In-1= O 0⊕O 1⊕…⊕O n-1 (1)

The parity-preserving characteristic for a gate makes 2. 2. Parity-Preserving Reversible Gates

possible single error detection and in some cases multiple 1. Double Feynman gate (F2G) [21] as a parity-
error detection at its outputs. It is worth mentioning that preserving 3×3 reversible gate with the quantum cost of
a reversible circuit containing only the parity-preserving two is shown in Figure 1a. The hardware complexity of
gates has itself the parity-preserving property. Therefore, this gate is equal to 2𝛂. This gate can be used as a fan-
if a reversible circuit with error detection capability is out generator in reversible circuit synthesis.
intended; it should only include the parity-preserving 2. Fredkin gate (FRG) [22] (Figure 1b) as the oldest
gates. After designing a parity-preserving circuit, the parity-preserving reversible gate with the quantum cost
error detection process can be performed using the rules of five has the hardware complexity equal to 2𝛼 + 4𝛽 +
stated in literature [16,17]. 1𝛾 due to the fact that there exist two distinct XOR
 F. Eslami-Chalandar et al. / IJE TRANSACTIONS C: Aspects Vol. 32, No. 3, (March 2019) 381-392 383

operations, four distinct AND operations, and only a This gate can be used as a parity-preserving full adder
distinct NOT operation in its output expressions. This when the D and E inputs are set to zero. In this case, the
gate is a universal gate that means all logic operations or sum and carry are produced on the R and S outputs,
reversible logic circuits can be implemented only by respectively. In addition, this gate produces the minimu m
using this type of gate. cost full adder.
3. New fault-tolerant gate (NFT) [23] as another parity- 8. Low-cost gate (LCG) [20] is another 5×5 parity-
preserving reversible gate with the quantum cost of five preserving reversible gate which has the quantum cost of
has the hardware complexity equal to 3𝛼 + 3𝛽 + 2𝛾. 10. The hardware complexity of this gate is equal to 6𝛼 +
Similar to FRG, this gate is a universal gate. 2𝛽. Similar to ZPLG, this gate can be used as a parity-
4. Modified Islam gate (MIG) [24] is a 4×4 parity- preserving full adder when its two last inputs are set to
preserving reversible gate with the quantum cost of 7 and zero. In this case, the sum and carry are produced,
the hardware complexity of 3𝛼 + 2𝛽 + 1𝛾. This gate is accordingly. Despite the fact that the quantum cost of
also a universal gate. In addition, this gate can be used as LCG is higher than that of ZPLG, its hardware
a parity-preserving half adder when its two last inputs are complexity is much less than that of ZPLG which makes
set to zero. In this case, the sum and carry are produced, it more desirable in some applications.
accordingly.
5. LMH [25] shown in Figure 2 is a 4×4 parity-preserving
reversible gate with the quantum cost of six and the 3. RELATED WORKS
hardware complexity equal to 3𝛼 + 2𝛽 + 1𝛾. The
obtained hardware complexity is based on the fact that 3. 1. Parity-Preserving Reversible Full Adders
the common or the same operations are accounted once Both types of serial and parallel multiplications somehow
according to the approach presented in literature [20]. require the addition operation. This operation is usually
Thus, as two XOR operations in the output expressions performed by using full adders and half adders.
operate on the same operands (in R and S outputs shown As stated before, there exist some parity-preserving gates
in Figure 2), it results in 3α instead of 4α. In addition, two that can perform the operation of a parity-preserving full
same A'C operations and two same AB operations exist adder (LCG [20] and ZPLG [26]) or half adder (MIG [24]
in the output expressions which are result in a simpler and ZCG [26]) after setting some of their inputs to zero.
term 2β instead of 4β. Finally, a distinct NOT operation However, a full adder can be constructed by connecting
(A') results in 1γ. two half adders, as well. In addition, a parity-preserving
6. ZCG [26] shown in Figure 3a is another 4×4 parity- full adder may be constructed by using a few parity -
preserving reversible gate with the quantum cost of six. preserving gates similar to SNFA (single NFT full adder)
The hardware complexity of this gate is equal to 5𝛼 + [27] in which three F2Gs and a NFT gate have been used.
2𝛽 + 1𝛾. Similar to MIG, this gate can be used as a This gate has the quantum cost of 11 which is more than
parity-preserving half adder when its C and D inputs are that of LCG and ZPLG, and its hardware complexity is
set to zero. In addition, this gate produces the minimum equal to 9𝛼 + 3𝛽 + 2𝛿.
cost half adder.
7. ZPLG [26] shown in Figure 3b is a 5×5 parity- 3. 2. Parity-Preserving Reversible Multipliers
preserving reversible gate with the quantum cost of eight Since the multiplier is one of the important elements of a
and its hardware complexity is equal to 8𝛼 + 3𝛽 + 1𝛾. computing system, many studies have been performed to
design optimal multipliers. However, despite the fact that

A P = AB’ C
B Q = A B
C ZCG R = AB  C
(a) (b) S = A  CD
D
Figure 1. Block diagrams of (a) double Feynman gate, and
(b) Fredkin gate (a)
A P=A D
B Q=A  B D
A P=A C ZPLG R=A  B  C D
B Q=B  C D S= (A D) (B  C)  BCD
LMH
C R=A’C AB E T=(A D) (B  C) BC’D  E
D S=A’C  AB  D (b)
Figure 2. Block diagram of LM H gate Figure 3. Block diagrams of (a) ZCG, and (b) ZPLG
384 F. Eslami-Chalandar et al. / IJE TRANSACTIONS C: Aspects Vol. 32, No. 3, (March 2019) 381-392

there are many works [5-11] regarding reversible logic TABLE 1. Operations in the Booth’s algorithm versus
multipliers and even the recent designs reported in consecutive bits of multiplier
literature [12, 13, 28-32], there is not much work 𝒙𝒊 𝒙𝒊− 𝟏 Required operation
incorporating the parity-preserving multipliers. The 0 0 Addition with zero, equivalent to no operation
multipliers are designed in two manners, serial or
0 1 Add A to partial product
parallel. When a low-cost design is very important, serial
multipliers are better because of having a lower cost. On 1 0 Subtract A from partial product
the other hand, if a high speed design is intended, parallel 1 1 Addition with zero, equivalent to no operation
multipliers are better because they require a lower delay.

3. 2. 1. Serial Multipliers As stated above, there TABLE 2. Operations in the K-algorithm versus consecutive
is not much work with respect to the parity-preserving bits of multiplier [14]
serial multipliers. In fact, this type of multipliers is only
𝒙𝒊 𝒙𝒊−𝟏 𝒚𝒊 Required operation
proposed in literature [14] based on the well-known
Booth’s algorithm and its modified version called 0 0 - No operation
Keshuv or K-algorithm for multiplying signed numbers. Pass A as it is to the addition
0 1 0
The general structure of a 4-bit multiplier based on the stage
Booth’s algorithm is shown in Figure 4. As stated in Pass A as it is to the addition
literature [14], this circuit has been implemented using 46 1 0 1
stage
reversible gates and with the total quantum cost of 200. 1 1 - No operation
It should be noted that in Figure 4, A is the first operand
or multiplicand, X is the second operand or multiplier,
and Z is the product.
Table 1 is used in the Booth’s-based multiplier.
However, the K-algorithm proposed in literature [14]
(shown in Figure 5) utilizes Table 2 to perform the
required operations. This table results in simpler circuit
by using 2 to 1 multiplexers instead of 4 to 1 multiplexers
used in the Booth’s-based multiplier. In addition, it does
not require copying the first operand opposed to the
Booth’s-based multiplier. As shown in Figure 5, in the K-
algorithm the select line's value of 2 to 1 multiplexer is
equal to xi ⨁ xi-1 . If this value equals '0', a 4-bit zero
number is selected; otherwise the first operand (A) is
selected. The two's complement of A is produced by an
XOR operation between each bit of A and y i shown in
Table 2, and then, adding to the input carry equal to y i .
This method produces the two's complement of A if yi
equals '1'. The proposed multiplier in literature [14] based
on the K-algorithm includes 39 reversible gates with the
quantum cost of 126.
Figure 5. Block diagram of a 4-bit multiplier based on the
3. 2. 2. Parallel Multipliers One of the popular K-algorithm [14]
parallel multiplier architectures is array multiplier that
includes two steps, partial product generation (PPG) and multi-operand addition (MOA) in which the partial
products will be added together. Despite the fact that
various reversible array multipliers exist in the literature,
few designs are parity-preserving, as well. The first
COMPLEMENT

parity-preserving signed array multiplier is proposed in

2's

Xi Xi-1
literature [9] based on the Baugh-Wooley method [15].
4 4 4
0 Z7-Z4 As stated in literature [9], this multiplier includes 57
SHIFTER

COPYING 4 4
4 4:1 4 ADDER 4
A FIRST 4
MUX gates with the quantum cost of 401 for 5-bit input
4
OPERAND 0
4
Initial 4 Z3-Z0 operands. In this design, two new parity-preserving gates
Value: X called MNFT (modified NFT) and F2PG are used in
Figure 4. Block diagram of a 4-bit Booth’s-based multiplier addition to the well-known parity-preserving gates
according to literature [14] including F2G, FRG and MIG.
 F. Eslami-Chalandar et al. / IJE TRANSACTIONS C: Aspects Vol. 32, No. 3, (March 2019) 381-392 385

In literature [8] a parity-preserving unsigned array and the other copy is sent to the multiplexer in stage
multiplier is proposed utilizing F2Gs and FRGs to (3). However, in the first proposed multiplier, the
implement the PPG part, and MIGs to construct half one's complement of multiplicand is produced as
adders and full adders of the MOA part. This multiplier well, by the same number of F2Gs and is sent to the
requires a quantum cost of 244 for 4-bit input operands. next stage to compute the two's complement. In other
In literature [25] another parity-preserving unsigned words, different from literature [14], half of the stage
array multiplier is presented which reduces the required (2) is performed along with the stage (1). The
quantum cost to 205. This design utilizes FRG and a new quantum cost of this section with the operation shown
gate called LMH (Lafifa-Mushfiq-Hafiz) to implemen t in Figure 6 is equal to eight because of using four
the PPG part, and incorporates MIG and SNFA to F2Gs.
construct half adders and full adders, respectively, for the (2) For generating the two’s complement of multiplicand ,
MOA part. the received one's complement from stage (1) is
added to one. However, in literature [14] four NOT
gates have been used for inverting four bits of
4. PROPOSED PARITY-PRESERVING SERIAL multiplicand before adding to one. Thus, due to the
MULTIPLIERS fact that the NOT gate is not parity-preserving, two
F2Gs should be used for this purpose according to
In this section, the new parity-preserving serial Figure 7. By this modification, the quantum cost of
multipliers with better criteria compared to the existing the multiplier proposed in literature [14] does not
designs are introduced in details. The preliminary work change. However, according to Figure 7, both the
regarding serial multipliers is proposed in literature [33]. number of constant inputs and the number of garbage
Similar to previous parity-preserving designs, the outputs are increased by one while the number of
proposed multipliers help to detect at least single errors. gates is decreased by two.
As stated in section 2, after designing a parity-preserving To perform the required addition and prepare the
multiplier, the error detection process can be performed last two's complement result four half adders are
using the methods illustrated in literature [16,17]. required. In the proposed multiplier, four ZCGs are
used instead of MIGs in literature [14] with the total
4. 1. Signed Multipliers The Booth’s algorithm quantum cost of 24.
which is the base of signed serial multipliers has five (3) Each one-bit 4 to 1 parity-preserving multiplexer is
stages according to Figure 4: made by three one-bit 2 to 1 multiplexers. Since each
Stage (1): copying the first operand's bits (multiplicand's one-bit 2 to 1 multiplexer can be constructed by a
bits) FRG, the stage (3) requires 12 FRGs with the total
Stage (2): computing the two’s complement of first quantum cost of 60 for a 4×4 multiplier. The outcome
operand of this section is shown in Figure 8.
Stage (3): using a multiplexer to select among the first (4) The main adder of the proposed multiplier requires a
operand, it's two's complement, and zero (based on Table 4-bit adder which includes a half adder in the least
1) significand bit and three full adders. In the proposed
Stage (4): using an adder to perform the required multiplier, ZCG and ZPLG are utilized to construct
additions the only half adder and three full adders, respectively,
Stage (5): shifting the result to right arithmetically using instead of using MIGs. Therefore, this stage, shown
a parallel shifter in Figure 9, has the quantum cost of 3×8+6=30.
Stages 1 and 2 are performed once. However, the next (5) Different from literature [14] in which seven FRGs
stages should be run more times dependent to the size of and one F2G are used to implement the parallel
operands. shifter, eight F2Gs are utilized in the first proposed
As stated before, a reversible circuit should only include multiplier to realize the parallel right shift which
the parity-preserving gates if the error detection leads to lower quantum cost. However, some extra
capability is intended. Therefore, the proposed F2Gs are required to feedback some bits to the
multipliers comprise only the parity-preserving gates. parallel input in the manner that a direct feedback is
The first proposed signed serial multiplier is based on the not produced from a gate's output to its input to
Booth’s algorithm. In this multiplier, different stages prevent unallowable feedbacks. In the proposed
mentioned above are implemented as follows for 4-bit Booth’s-based multiplier, four F2Gs are used for this
operands that will be extended to n-bit operands (n×n purpose instead of seven F2Gs in literature [14].
multiplier): Therefore this section that is depicted in Figure 10 has
(1) In literature [14] for copying multiplicand's bits, four the quantum cost of 24.
F2Gs are used. One of the copies is sent to the stage According to the explanation above, the first
(2) to compute the two’s complement of multiplicand , proposed signed serial multiplier which is a Booth’s -
386 F. Eslami-Chalandar et al. / IJE TRANSACTIONS C: Aspects Vol. 32, No. 3, (March 2019) 381-392

0
based design includes 36 gates with the quantum cost of X7
0
0
F2G F2G F2G F2G F2G
0 0
F2G
0 0
F2G
0 0
F2G
0 0
X6
F2G F2G F2G F2G
146 by exploiting new arrangements of the well-known X5
X4
X3
X2
X1
X0
to X3 to X2 to X1 to X0

gates to rebuild the different parts in addition to utilizin g 0

0 1 A3 0 1 A2 0 1 A1 0 1 A0
some newer gates. This multiplier is shown in Figure 11. X7 X7 X6 X5 F2G F2G F2G F2G
A3 A2 A1 A0
To extend the size of first proposed multiplier to be A2’
A1’ A0’

A3’
used for larger operands, Equation (3) can be used to 0 0 0 0 0 0 0 0

compute the number of different gates and total quantum ZCG ZCG ZCG ZCG 1

cost. The generalized circuit of proposed Booth’s -based

multiplier is shown in Figure 12 for n-bit operands. 0 0 0 0 0 0 0 0 Xi

FRG FRG FRG FRG FRG FRG FRG FRG

𝑅𝑒𝑞𝑢𝑖𝑟𝑒𝑑 𝑔𝑎𝑡𝑒𝑠 𝑜𝑓 (𝑛× 𝑛) 𝑚𝑢𝑙𝑡𝑖𝑝𝑙𝑖𝑒𝑟 to 0

Xi-1

FRG FRG FRG FRG

= 4𝑛 × 𝐹2𝐺 + 3𝑛 × 𝐹𝑅𝐺 + (𝑛 + 1 ) × 𝑍𝐶𝐺 + (3)

(𝑛 − 1) × 𝑍𝑃𝐿𝐺
FULL FULL FULL HALF
Cout
ADDER ADDER ADDER ADDER

S3 S2 S1 S0
to X7 to X6 to X5 to X4

Figure 11. Proposed 4-bit parity-preserving Booth’s-based

0 1 A3 0 1 A2 0 1 A1 0 1 A0 multiplier

F2G F2G F2G F2G

0
0 F2G F2G F2G F2G F2G F2G
0
X2n-1 0 0 0 0 0 0
X2n-2 F2G F2G F2G
A3 A3’ A2 A2’ A1 A1’ A0 A0’ Xn
Xn-1
X1
to Xn-1 to X1 to X0
X0
0
Figure 6. Generation of one's complement of a 4-bit
0 1An-1 0 1 A1 0 1 A0
multiplicand along with its replication in the first proposed X2n-1 X2n-1 Xn+1 F2G F2G F2G

multiplier An-1 A1 A1’

A0 A0’

An-1’

0 0 0 0 0 0

ZCG ZCG ZCG 1

A3 A2 A1 A0 1
0 0 0 0 0 0 Xi

FRG FRG FRG FRG FRG FRG

F2G F2G to 0
Xi-1

FRG FRG FRG

A3’ A2’ A1’ A0’

Figure 7. Proposed circuit for inverting four bits of FULL FULL HALF
Cout
multiplicand instead of using four NOT gates ADDER ADDER ADDER

Sn-1 Sn-2 S0
to X2n-1 to X2n-2 to Xn

B=2's complement of A Figure 12. Generalized structure of proposed n×n Booth’s-

0 A3 B3 0 0 A2 B2 0 0 A1 B1 0 0 A0 B0 0 Xi based multiplier
FRG FRG FRG FRG FRG FRG FRG FRG

Xi-1
FRG
The second proposed signed serial multiplier is based on
FRG FRG FRG
the K-algorithm reported in literature [14] which is an
R3 R2 R1 R0 improved version of the Booth’s algorithm, as stated in
Figure 8. 4-bit 4 to 1 multiplexer based on [14] section 3.2.1. This multiplier, depicted in Figure 13, is
implemented as follows for 4-bit operands:
(1) Similar to that of the first proposed multiplier, 12
0 0 X7 R3 0 0 X7 R2 0 0 X6 R1 0 0 X 5 R0
F2Gs are used for parallel shifter. However, this
section has been implemented by eight FRGs and five
ZPLG ZPLG ZPLG ZCG F2Gs in literature [14].
(2) The implementation of 4-bit parity-preserving 2 to 1
S3 S2 S1 S0
Cout
to X7 to X6 to X5 to X4
multiplexer requires four FRGs since each one-bit 2
Figure 9. 4-bit adder in the first proposed multiplier to 1 multiplexer can be realized by a FRG.
(3) According to Figure 5, to obtain the one's complement
0 F2G
0
F2G F2G F2G F2G F2G F2G F2G
of multiplicand using the XOR gates between the
0
X7
X6
0 0 0 0 0 0 0 0 multiplexer and the adder, only two F2Gs are required
F2G
X5
X4
X3
F2G
to X3
F2G
To X2 to X1
F2G
to X0
similar to Figure 7 instead of four F2Gs used in
X2
X1
X0 to MUX
literature [14]. It should be noted that the one's
to 4-bit adder
complement will be sent to the adder only when yi
Figure 10. Parallel shifter in the first proposed multiplier equals '1'.
 F. Eslami-Chalandar et al. / IJE TRANSACTIONS C: Aspects Vol. 32, No. 3, (March 2019) 381-392 387

0
(4) The 4-bit adder of the second proposed multiplier 0
0
F2G F2G F2G F2G
0 0
F2G
0 0
F2G
0 0
Xi
0 F2G
X2n-1

includes four full adders implemented by four ZPLGs X2n-2

Xn
Xn-1
F2G
to Xn-1
F2G
to X1
F2G
to X0
X1
instead of using MIGs. The input carry of this adder X0
0

is y i so that the two's complement of multiplicand is An-1 0 An-2 0 A0 0 Xi  Xi-1

Xn+1 FRG FRG FRG

finally used when y i equals '1' according to Table 2 X2n-1 X2n-1

and Figure 5. yi
yi

In addition to the sections described above, a F2G is to 0

F2G F2G

required to produce xi ⨁ xi-1 and two copies of xi to be

yi

moved to the y i by default. This gate is placed on top- Cout

FULL FULL FULL Cin = yi
ADDER ADDER ADDER
right of Figure 13. Therefore, the second proposed signed Sn-1 Sn-2 S0
to X2n-1 to X2n-2 to Xn
serial multiplier includes 23 gates with the quantum cost
Figure 14. Generalized structure of proposed n×n multiplier
of only 82 by utilizing new arrangements of some basic based on the K-algorithm
parity-preserving gates to realize the different parts of the
multiplier.
To extend the size of second proposed multiplier to
be used for larger operands, Equation (4) can be used to (3) The 4-bit adder of the third proposed multiplier
compute the number of different gates and total quantum includes a half adder in the least significand bit and
cost. The generalized circuit of proposed multiplier based three other full adders. Thus, it is constructed by a
on the K-algorithm is shown in Figure 14 for n-bit ZCG as a half adder and three ZPLGs as full adders.
operands. This multiplier that includes 20 gates requires the
quantum cost of 74 which is lower than that of the
𝑅𝑒𝑞𝑢𝑖𝑟𝑒𝑑 𝑔𝑎𝑡𝑒𝑠 𝑜𝑓 (𝑛× 𝑛) 𝑚𝑢𝑙𝑡𝑖𝑝𝑙𝑖𝑒𝑟 previous multipliers. To extend the size of third proposed
= (3𝑛 + 1 + ⌈𝑛/2⌉) × 𝐹2𝐺 + 𝑛 × 𝐹𝑅𝐺 + 𝑛 × (4) multiplier for larger operands, Equation (5) is useful to
𝑍𝑃𝐿𝐺 compute the number of different gates and total quantum
cost. The generalized circuit of proposed multiplier based
on the Add & Shift method is shown in Figure 16 for n-
4. 2. Unsigned Multiplier The third proposed bit operands.
multiplier in this paper is an unsigned serial multiplier
based on the Add & Shift method. Due to the fact that 𝑅𝑒𝑞𝑢𝑖𝑟𝑒𝑑 𝑔𝑎𝑡𝑒𝑠 𝑜𝑓 (𝑛× 𝑛) 𝑚𝑢𝑙𝑡𝑖𝑝𝑙𝑖𝑒𝑟
this multiplier is unsigned, it naturally has less = 3𝑛 × 𝐹2𝐺 + 𝑛 × 𝐹𝑅𝐺 + 1 × 𝑍𝐶𝐺 + (𝑛 − (5)
complexity compared to the first and second proposed 1) × 𝑍𝑃𝐿𝐺
multipliers. In this method, according to the least
significant bit of the second operand, only two situations
may occur. If this bit equals zero, "0000" will be sent to
the adder, otherwise if it equals one, the multiplicand (A) 5. PROPOSED PARITY-PRESERVING PARALLE L
will be sent to the adder. This multiplier, depicted in MULTIPLIER
Figure 15, is implemented as follows for 4-bit operands:
(1) Similar to previous proposed multipliers in this paper, The proposed parity-preserving parallel multiplier in this
12 F2Gs are used for parallel shifter. paper is a signed array multiplier based on the Baugh-
(2) Similar to the second proposed multiplier, the Wooley method. A sample 4-bit multiplication regarding
implementation of 4-bit 2 to 1 multiplexer requires four this method is shown in Figure 17. In this figure, Pij ' is
FRGs. The selection is made between the multiplican d the complement of Pij , and X3 , Y3 and Z7 are the sign bits
and the 4-bit zero number. of two input operands and output product, respectively.
0
0 F2G F2G F2G F2G F2G F2G F2G F2G Xi
0 0 F2G
X7 0 0 0 0 0 0 0 0
X6
X5 F2G F2G F2G F2G 0
X4
X3 to X3 to X1
F2G F2G F2G F2G F2G F2G F2G F2G
X2 to X2 to X0
X1 0
X0 X7 0 0 0 0 0 0 0 0
0 X6
X5 F2G F2G F2G F2G
X4
A3 0 A2 0 A1 0 A0 0 Xi  Xi-1 X3 to X3 to X2 to X1 to X0
X2
X1
X7 X7 X6 X5 FRG FRG FRG FRG X0

A3 0 A2 0 A1 0 A0 0 Xi
yi
X7 X6 X5 FRG FRG FRG FRG
F2G F2G
to 0
yi

Cout FULL FULL FULL HALF

FULL FULL FULL FULL Cin = yi
Cout
ADDER ADDER ADDER ADDER ADDER ADDER ADDER ADDER
S3 S2 S1 S0 S3 S2 S1 S0
to X7 to X6 to X5 to X4 to X7 to X6 to X5 to X4
Figure 13. Proposed 4-bit parity-preserving multiplier based Figure 15. Proposed 4-bit parity-preserving multiplier based
on the K-algorithm on the Add & Shift method
388 F. Eslami-Chalandar et al. / IJE TRANSACTIONS C: Aspects Vol. 32, No. 3, (March 2019) 381-392

0
F2G F2G F2G F2G F2G F2G their previous counterparts. To perform precise
0 0 0 0 0 0 0
X7
X6
X5 F2G F2G F2G comparisons, the main criterions are used including gate
X4
X3
X2
X1
to Xn-1 to X1 to X0
count, number of constant inputs, number of garbage
X0

An-10 An-2 0 A0 0 Xi
outputs, quantum cost, and hardware complexity. The
X2n-1 Xn+1 FRG FRG FRG
gate count is the number of required gates to realize a
circuit. In addition, the number of constant inputs in each
circuit is the number of gates' inputs whose values should
Cout FULL
ADDER
FULL
ADDER
HALF
ADDER
be constant at either '0' or '1' to perform the intended
Sn-1 Sn-2 S0 functions. However, the number of garbage outputs is the
to X2n-1 to X2n-2 to Xn
number of gates' outputs in the whole design that are not
Figure 16. Generalized structure of proposed n×n multiplier
based on the Add & Shift method connected to the other gates or are not used as the outputs
of the circuit.
The proposed parity-preserving serial multipliers are
PARTIAL PRODUCT X3 X2 X1 X0
GENERATION Y 3 Y2 Y 1 Y 0 characterized in Table 3 along with the previous designs.
The only existing parity-preserving serial multipliers
P03’ P02 P01 P00
MULTI OPERAND were proposed in literature [14], so the comparisons are
ADDITION P13’ P12 P11 P10
made with these circuits in Table 3. According to this
P23’ P22 P21 P20
table, the first and second proposed serial multipliers
P33 P32’ P31’ P30’
+ 1 1 which are based on the Booth’s algorithm and the K-
Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 algorithm, respectively, are better than their previous
Figure 17. A 4×4 signed multiplication based on the Baugh- equivalent designs presented in literature [14] in all
Wooley method criteria.
X0 Y3
Y0 Y1 Y2
0 LMH LMH LMH FRG
In addition, Pij stands for Xj .Yi that can be produced by 0
X0Y0 0
0
X0Y1 0
0
X0Y2
0 X0Y3

an AND gate in the partial product generation part.

X1
According to literature [25], Figure 18 can be used for a 0 LMH X1Y0 0 LMH
X1Y1 0
LMH
X1Y2
FRG
0
low-cost PPG part of a 4×4 multiplier which includes 0 0 0 X1Y3

seven FRGs and nine LMH gates with the total quantum X2

cost of 89. In this figure, LMH gates receive two 0

0
LMH X2Y0 0
0
LMH
X2Y1 0
0
LMH
X2Y2
0
FRG
X2Y3
operands as inputs, and generate a copy of both input
operands and their corresponding one-bit partial product X3
FRG FRG FRG FRG
Pij , as well. However, based on Figure 17, some Pij Pij=XjYi 0 X3Y0 0 X3Y1 0 X3Y2 0 X3Y3

signals should be inverted to comply with the signed Figure 18. Partial product generation for the 4×4 array
multiplication. Therefore, some F2Gs should be utilized multiplier
similar to Figure 7 to produce the required inverted
values. For a 4×4 multiplier, three F2Gs are enough to P32 P23 P31 P13 P30 P03 1
yield six Pij ' signals shown in Figure 17, as depicted in
Figure 19. F2G F2G F2G
The second part of an array multiplier is the multi-
operand addition. To implement this circuit in the P32’ P23’ P31’ P13’ P30’ P03’
proposed design, ZCG is used as half adder and ZPLG is Figure 19. Inverted one-bit partial products as required in
used as full adder, according to Figure 20. Since these Figure 17
gates have the quantum cost of six and eight, 0 0 P01 P10 P00
0 0 1 P22 P31’ 0 0 P12 P21 P30’ 0 0 P02 P11 P20
respectively, the quantum cost of multi-operand addition ZPLG ZPLG ZPLG ZCG
circuit shown in Figure 20 is equal to 92 including the
single F2G. This F2G is responsible to produce the 0 0 P32’P23’ 0 0 P13’ 0 0 P03’ 0 0
correct MSB of the product based on the Baugh-Wooley ZPLG ZPLG ZPLG ZCG
method. Therefore, the total quantum cost of this 4×4
multiplier including the circuits shown in Figs. 18 to 20 0 0 P33 0 0 0 0 0 0
is equal to 187. ZPLG ZPLG ZPLG ZCG

0 1 Z7’
Z6 Z5 Z4 Z3 Z2 Z1 Z0
6. RESULTS AND DISCUSSION F2G

Z7

In this section, some comparisons will be performed Figure 20. Proposed multi-operand addition for the 4×4
between the proposed parity-preserving multipliers and signed array multiplier
 F. Eslami-Chalandar et al. / IJE TRANSACTIONS C: Aspects Vol. 32, No. 3, (March 2019) 381-392 389

In addition, the third proposed serial multiplier which literature [14] based on the gate count and quantum cost
is based on the Add & Shift method is the only unsigned that are 41% and 34.9%, respectively.
multiplier in Table 3, and has the best values based on the The amounts of required gate count and quantum cost
mentioned criteria. for larger multipliers are illustrated in Table 4 according
It should be noted that the number of constant inputs to their general formula. Similar to that of Table 3, the
and garbage outputs in the proposed multipliers can third proposed serial multiplier which is based on the Add
simply be obtained regarding their corresponding figures & shift method requires the least gate count and quantum
shown before. However, the Cout signal of the adder part cost for all the adder sizes. Furthermore, Figure 22
in the first and second proposed multipliers (Figures 11 depicts the percentages of reduction in the gate count and
and 13) is accounted as a garbage output due to the fact quantum cost of the first and second proposed multipliers
that it is not used for the multiplication process. compared to the Booth’s-based and K-based counterparts
Furthermore, the number of constant inputs and garbage proposed in literature [14], respectively, for 8×8 and
outputs of half adders and full adders are apparent since 16×16 multipliers. According to this figure, the amounts
ZCG and ZPLG are used in the adder parts of proposed of improvements are almost the same for a specific
serial multipliers similar to the adder shown in Figure 9. proposed multiplier with different sizes. However, the
Regarding the hardware complexity, this criterion for amounts of improvements are slightly increasing for the
each circuit is calculated by summing the hardware first proposed multiplier while the size of multiplier is
complexity of all the gates constructing the circuit. increasing. The reverse of this characteristic is true for
To illustrate the precise amounts of improvements the second proposed multiplier.
attained by the new proposed multipliers, Figure 21 Table 5 demonstrates comparative results of different
depicts the percentages of reduction in four different parallel multipliers including the fourth proposed parity-
criterions for the first and second 4-bit proposed preserving multiplier which is based on the Baugh -
multipliers compared to their older Booth’s-based and K- Wooley method along with the previous parity -
based counterparts proposed in literature [14], preserving designs. In this table, the designs from [8] and
respectively. According to this figure, the maximu m [25] are unsigned array multipliers while the design from
improvements are obtained for the second proposed [9] is the only existing parity-preserving signed
multiplier compared to its K-based counterpart in multiplier.

TABLE 3. Comparison of different parity-preserving serial multipliers

Base Gate Constant Garbage Q uantum Hardware
4×4 multiplier Signed
algorithm count inputs outputs cost complexity
[14] (based on Figure 4) Booth’s Yes 44 52 61 200 99α+98β+30γ
1 st proposed circuit (Figure 11) Booth’s Yes 36 44 48 146 105α+67β+20γ
[14] (based on Figure 5) K-alg. Yes 39 30 34 126 82α+60β+20γ
nd
2 proposed circuit (Figure 13) K-alg. Yes 23 24 28 82 70α+28β+8γ
rd
3 proposed circuit (Figure 15) Add & Shift No 20 21 25 74 61α+27β+8γ

TABLE 4. Comparison of larger serial multipliers and their general formula

8×8 multiplier 16×16 multiplie r
Multiplier design Main formula
Gate count Q uantum cost Gate count Q uantum cost
( 3n + ⌈𝑛/2⌉) × 𝐹2𝐺 + ( 5𝑛 − 1) × 𝐹𝑅𝐺
[14] (based on Figure 4) 90 412 182 836
+( 3𝑛 − 1) × 𝑀𝐼𝐺
4𝑛 × 𝐹2𝐺 + 3𝑛 × 𝐹𝑅𝐺 +
1 st proposed circuit (Figure 11) 72 294 144 590
( 𝑛 + 1) × 𝑍𝐶𝐺 + ( 𝑛 − 1) × 𝑍𝑃𝐿𝐺
[14] (based on Figure 5) (5𝑛 + 3) × 𝐹2𝐺 + 3𝑛 × 𝐹𝑅𝐺 + 𝑛 × 𝑁𝐹𝑇 75 246 147 486
( 3n + 1 + ⌈𝑛/2⌉) × 𝐹2𝐺 +
2 nd proposed circuit (Figure 13) 45 162 89 322
𝑛 × 𝐹𝑅𝐺 + 𝑛 × 𝑍𝑃𝐿𝐺
3𝑛 × 𝐹2𝐺 + 𝑛 × 𝐹𝑅𝐺 + 1 × 𝑍𝐶𝐺 +
3 rd proposed circuit (Figure 15) 40 150 80 302
(𝑛 − 1) × 𝑍𝑃𝐿𝐺
390 F. Eslami-Chalandar et al. / IJE TRANSACTIONS C: Aspects Vol. 32, No. 3, (March 2019) 381-392

50 nearest counterpart proposed in literature [9] in all

1st proposed multiplier
45 criteria. Figure 23 illustrates the percentages of
2nd proposed multiplier
40 improvements attained by the fourth proposed multiplier
Improvement (%)

35 in four different criterions compared to the only existing

30 signed multiplier proposed in literature [9] and the best
25 unsigned multiplier proposed in literature [25] for the
20 4×4 size. According to this figure, the fourth proposed
15 multiplier is better than previous designs except in the
10 number of constant inputs and garbage outputs compared
5 to reported data in literature [25]. Regarding this fact, it
0 should be noted that signed multipliers naturally require
Gate count Constant inputs Garbage outputs Quantum cost
Figure 21. Improvements obtained in the 1st and 2nd 4-bit more cost in comparison with unsigned multipliers .
proposed multipliers compared to the designs in [14] However, the fourth proposed design in this paper only
requires more constant inputs and garbage outputs
compared to reported data in literature [25], and it is
50 better in the other criteria especially in the quantum cost
45 1st proposed multiplier that is a more important criterion.
2nd proposed multiplier
40
Improvement (%)

35
30 40
25 35 Compared to [9]
20 30 Compared to [25]
15 25
Improvement (%)

10
20
5
15
0
Gate count Quantum cost Gate count Quantum cost
10
8×8 8×8 16×16 16×16 5
0
Figure 22. Improvements of the larger 1st and 2nd proposed -5
multipliers compared to the designs in [14] -10
-15
Gate count Constant Garbage Quantum
Based on this table, the fourth proposed multiplier in this inputs outputs cost
paper requires the least quantum cost and gate count Figure 23. Improvements of the 4th proposed multiplier
compared to previous designs while it is better than its compared to previous designs

TABLE 5. Comparison of different parity -preserving parallel multipliers

Gate Constant Garbage Q uantum Hardware
4×4 multiplier Base algorithm Signed
count inputs outputs cost complexity
[8] Array No 48 64 64 244 116α+104β+36γ
[25] Array No 52 49 49 205 125α+78β+36γ
[9] Baugh-Wooley Yes 38 61 56 247 121α+109β+43γ
4 th proposed circuit (Figures 18 to 20) Baugh-Wooley Yes 32 53 55 187 136α+79β+28γ

7. CONCLUSIONS used including new arrangements of parity-preserving

reversible gates, better utilization of existing reversible
In this paper, three novel low-cost reversible serial gates, and exploiting newer gates. This way, the low-cost
multipliers were proposed along with a new parallel signed and unsigned serial multipliers were proposed for
multiplier with the parity-preserving capability. Since cost-critical applications in which if only unsigned
attaining the low-cost designs useful for error detection numbers exist, the third proposed multiplier can be used
was the main goal of this paper, some techniques were as the best design. On the other hand, the fourth proposed
 F. Eslami-Chalandar et al. / IJE TRANSACTIONS C: Aspects Vol. 32, No. 3, (March 2019) 381-392 391

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‫‪392‬‬ ‫‪F. Eslami-Chalandar et al. / IJE TRANSACTIONS C: Aspects Vol. 32, No. 3, (March 2019) 381-392‬‬

‫‪Reversible Logic Multipliers: Novel Low-cost Parity-Preserving Designs‬‬

‫‪F. Eslami-Chalandar, M. Valinataj, H. Jazayeri‬‬

‫‪School of Electrical and Computer Engineering, Babol Noshirvani University of Technology, Babol, Iran‬‬

‫‪PAPER INFO‬‬ ‫چكيده‬

‫‪Paper history:‬‬ ‫منطق برگشتپذیر یکی از نمونه های نوظهور برای بهینهسازی توان مصرفی است که میتواند به جای مدارهای فعلی مورد‬
‫‪Received 05 April 2018‬‬
‫‪Received in revised form 27 February 2019‬‬ ‫استفاده قرار گیرد‪ .‬همچنین‪ ،‬تحملپذیری اِشکال به صورت تشخیص یا تصحیح خطا جنبهای ضروری برای سیستمهای‬
‫‪Accepted 07 March 2019‬‬
‫پردازشی امروزی است‪ .‬در این مقاله‪ ،‬به خاطر اهمیت عملیات ضرب در سیستم های محاسباتی‪ ،‬چندین طراحی جدید برای‬
‫‪Keywords:‬‬ ‫ضربکننده برگشتپذیر با ویژگی حفظ پریتی پیشنهاد می شوند که برای تشخیص خطا مناسب خواهند بود‪ .‬در ابتدا‪ ،‬دو‬
‫‪Reversible Logic‬‬
‫‪Parity-Preserving Gates‬‬ ‫ضربکننده سری عالمت دار بهینه بر مبنای الگوریتم بوث و نسخه بهبودیافته آن به نام الگوریتم ‪ ، K‬با استفاده از چینشهایی‬
‫‪Multiplication‬‬
‫جدید برای گیت های برگشت پذیر ارائه می گردند‪ .‬سپس‪ ،‬ضربکننده سری کم هزینه دیگری بر پایه روش مرسوم جمع‪-‬‬
‫‪Booth’s Algorithm‬‬
‫‪Error Detection‬‬ ‫انتقال پیشنهاد می شود که برای کاربردهایی شامل ضرب اعداد بدون عالمت مناسب است‪ .‬در انتها‪ ،‬یک ضربکننده مواز ی‬
‫‪Fault-Tolerance‬‬
‫عالمتدار جدید بر پایه روش باو‪-‬وولی پیشنهاد می گردد که برای کاربردهای نیازمند به سرعت باال مناسب است‪ .‬نتایج‬
‫مقایسه ها نشان میدهد که ضربکننده های پیشنهادی با توجه به معیارهای اصلی مورد استفاده در مدارهای با منطق‬
‫برگشتپذیر شامل هزینه کوانتومی‪ ،‬تعداد گیت‪ ،‬تعداد ورودی های ثابت و تعداد خروجی های بیاستفاده‪ ،‬بسیار بهتر از‬
‫طراحی های موجود هستند‪.‬‬

‫‪doi: 10.5829/ije.2019.32.03c.05‬‬