No. of Guestions 8) [Total No, of Printed Pages - 3} 5) 5322 2. Tech 7th Semostor Examination ‘Advanced Computor Arhiteturo (NS) cs-atzirate ‘Time 3 Hours Max. Mark 100 ‘The canidates shalt tht ansuers precisa wii the answer bak (40 pages) sd otha and na suplemenareaninuaion Note: Candidates are requred to attemet five questions inal Selecing one question fom each ofthe section A, BC {2 D ofthe quosion paper and ll the subparts of the ‘queston in section E. Use of non-programmabl clelater alowed SECTION - 1. Characterao the architect! operators of SIMD and MIMD computers. Distingulsh between multiprocessors and mulcomper based on the sutures. resource sharin, and Intrerases vommuntations Also. expian the ferences among UMA NUMA, and COMA, and NORMA computers 2) 2 (8) Bxplah ow instruction set, coma technology, CPU. implementation and contol, and cache and fandom herarey affect he CPU performance. dusty the eect: infers of program length, cock rate and eflecive CP 19) (B) Explain the terms data dependence and resource dependence. Aso, cyplan, row these dependencies ized to enhance the degree of parllism. (10) pro} a a 15322 SECTION -8 (a) Consider aniston pane wih fur stages (61, S2. SS and 64) nach win combinational creat nly ‘The pone restore are requred between each siage and fat he end ofthe lst stage. Delays forthe stages a {or the ppelne rogers areas gven i he fie i Vina the approximate speed up of the pipeline in ead slat under ea condone when comearedt the Bee ae H feerponding nampesine inplementaion? (10) (0) Descibe the architecture of typical superscalar VU processor wih the fel of lock agram. (0) Consider the non-iptined processor inveduced proviousy ‘Assume that has a ne deck eo and it uses 4 cycles for {ALU operations and branches, and 6 cycles for memory ‘operations, assume thatthe elave frequencies of tee ‘Sparaions are 40%, 20%, ad 40%, expecvely Suppose fat ‘de fo Gock skew and setup, piptning the processor adds ‘ans of overhead tothe clock ignting any tency mpact how much speed ine isbn execution rate wl we ah tom a ppelne? 20) secmiOn -¢ (@)_ Explain four possicle hardware schemes tht can be sed in an rtueton peeine inorder to mevmize the performance degradation caused by instruction Brancing (0) (©) Briony compare CISC, RISC and VLIW areheectue, (0)(2) what co you mean by coherence propery? wre coun the diferent methods to retain this propery, (10) (0) Acomputer has 8 256 KByte, nay vet ssociaive write back data cache wih Dlock tze of 32 Bytes The processor sende 2 bt addresses fo the cache contall, Een cache tag drectory erty cntans, in eaation to acess tag, 2 vai Bis, | modifed Bt and {replacement bit Find he number of item te ag is ofan acres, 1) SECTION -D (2) Comment on the use of setter gether operation andthe tne of vecor masks in 8 vector pressor (10) (0) What ae he advaiages and disadvantages of sofate- bases and hardware based speculaton mechanic? 10) Explain CMS architects with block dagram and compare it wwty M2 arentecture 20) SECTION -E ‘Wate shot note on folowing (@) Soil versus paral processing cise. (©) Data fow archtsotue (©) Chuetr Compute (@) Recuction Computers (f) Crossoar networks (@) System effciency and speedup (ty Localy of reference, () Cache coherence 1) Gustatron's Law for sealed problems. _(10+2=20)