IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO.

12, DECEMBER 2019 3281

A 192-pW Voltage Reference Generating

Bandgap–Vth With Process and Temperature
Dependence Compensation
Youngwoo Ji , Jungho Lee, Byungsub Kim , Senior Member, IEEE, Hong-June Park , Senior Member, IEEE,
and Jae-Yoon Sim , Senior Member, IEEE

Abstract— This article presents a methodology to design a dependence of about −2 mV/◦ C. By selecting the design para-
circuit to compensate for process skew by exploiting an inherent meters to adjust the temperature coefficient of a proportional-
dimension-dependent effect of process skew on change in the to-absolute-temperature (PTAT) voltage [8], the reference
threshold voltage. We design a voltage reference circuit with
a hybrid architecture of bandgap reference (BGR) and CMOS generates a voltage level of VBG . For low-power imple-
reference, which generates a nominal voltage level of (bandgap mentation of BGR, various PTAT generation schemes have
- threshold). By compensating the process skew of the threshold been proposed with differential amplifier [9], capacitor net-
term with the proposed dimension-induced effect as well as work [10], [11], and use of leakage current for bias [12], [13].
the temperature dependence, the circuit achieves the simulta- However, complicated circuits with multiple branches require
neous benefits of BGR and CMOS references. For verification,
the circuit was fabricated in three wafers of a 0.18-µm CMOS a large area and preclude further reduction of power usage
including extreme slow and fast corners. With an active area into the sub-nW regime.
of 0.0045 mm2 , it consumes 192 pW at room temperature. Mea- In CMOS reference circuits, the reference is determined
surement from 45 chips (15 chips per wafer) shows untrimmed by the threshold voltage of the MOS transistor (Vth ). Vth
process/voltage/temperature variations of 0.53%, 0.020%/V, and typically holds a CTAT characteristic with a smaller temper-
33 ppm/◦ C, respectively.
ature dependence than that of BJT. Vita and Iannaccone [14]
Index Terms— Bandgap, process compensation, temperature and Ueno et al. [15] proposed current-bias circuits that had
compensation, ultra-low power (ULP), voltage reference. a square-root temperature dependence to generate a PTAT.
I. I NTRODUCTION Flowing this current into a MOS diode leads to a reference
voltage that is close to Vth . To further reduce the power con-
I MPLANTABLE and attachable electronics often require a
nanowatt (nW)-consuming smart system-on-a-chip (SoC)
[1]–[7]. Processing with a duty cycling has been actively
sumption, Magnelli et al. [16] and Seok et al. [17] flow the
leakage current with an exponential temperature dependence
into a MOS diode. In this approach, the level of the reference
adopted to effectively manage energy consumption. Since the
voltage is represented as the difference between the threshold
SoC mostly stays in the sleep mode, the power dissipation
voltages (Vth ) of two transistors. Since this difference is too
in this mode becomes an important consideration. A voltage
small to be directly used, it should be amplified with an up-
reference circuit is an essential building block, which is often
scaling [18], which eventually results in an amplification of
required to be turned on even during sleep mode to ensure
the standard deviation as well (Table I).
fast start-up and, therefore, contributes significantly to overall
Compared with BGR approaches, CMOS references have
energy consumption.
achieved lower power consumption with a smaller area
Voltage reference circuits can be categorized into two types:
(Fig. 1). However, the inclusion of the Vth term in the output
bandgap reference (BGR) and CMOS reference. In BGR
results in an inevitable effect of the process variations [19].
circuits, an inherent voltage of the silicon bandgap (VBG ) is
The process sensitivity can be reduced by constructing a circuit
associated with the p-n junction. The p-n junction, if conducted
that uses only one type of transistor, e.g., only PMOS [20].
with a current bias, provides a complementary-to-absolute-
Geometry dependence of Vth has also been considered for the
temperature (CTAT) voltage that has a large temperature
generation of the voltage reference [21]. However, a small
Manuscript received April 25, 2019; revised July 31, 2019 and September 4, Vth requires a large amplification factor to up-scale the out-
2019; accepted September 10, 2019. Date of publication October 4, 2019; put. Process compensation schemes have also been proposed
date of current version November 22, 2019. This article was approved by
Guest Editor Youngcheol Chae. This work was supported by the Engineer- for current bias [22], [23]. However, they assume a stable
ing Research Center Program of the National Research Foundation (NRF) supply voltage which is not ensured for the voltage reference.
funded by the Korea Ministry of Science and ICT under Grant NRF- This article presents a methodology to compensate for the
2019R1A5A1027055. (Corresponding author: Jae-Yoon Sim.)
The authors are with the Department of Electrical Engineering, Pohang process variation in Vth [24]. We propose a voltage reference
University of Science and Technology, Pohang 37673, South Korea (e-mail: circuit with a hybrid architecture of BGR and CMOS ref-
[email protected]; [email protected]). erence; it generates a nominal voltage level of (VBG − Vth ).
Color versions of one or more of the figures in this article are available
online at http://ieeexplore.ieee.org. By compensating for the process skew of the Vth term with the
Digital Object Identifier 10.1109/JSSC.2019.2942356 dimension-induced side effect, the proposed scheme achieves
0018-9200 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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3282 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 12, DECEMBER 2019

TABLE I of STI, which is generally taken in the recent CMOS tech-

P REVIOUSLY R EPORTED V OLTAGE R EFERENCES nologies [25]. A gate voltage generates an electric field that
depletes the channel. The fringing field on both edges of the
channel is an extra field and helps to deplete the channel. As a
result, the fringing field effectively reduces Vth . As the channel
width decreases, the relative contribution of the fringing field
increases, so the reduction that it causes in Vth also increases.
As substrate doping concentration increases, the process
corner becomes slow-skewed, so the required electric field
increases and Vth itself increases. However, the relative portion
of the fringing field becomes weaker due to the thinner deple-
tion region [Fig. 2(a)]. In contrast, for a fast-skewed process
corner, the electric field to turn on the channel decreases and
Vth itself decreases. However, the relative portion of the fring-
ing field becomes stronger due to the thicker depletion region
[Fig. 2(c)]. Since the fringing effect becomes more noticeable
as the channel width decreases [Fig. 3(a)], the difference in
the Vth between slow and fast corners (Vth,SS − Vth,FF ) is a
function of the width, where the subscripts SS and FF mean
the slow and the fast corners. The difference increases as
the channel width decreases while it becomes almost constant
when the width is sufficiently large [Fig. 3(b)]. This indicates
the process skew affects more significantly for the smaller
devices. Vth itself decreases as the process skew goes from
slow to fast corners, but the decrease is increasingly significant
as the channel width decreases [Fig. 3(c)].
This relationship suggests a method to include the amount
of process skew as a circuit design parameter. As an example,
given a differential pair that is composed of two input transis-
tors, load resistors, and a current source [Fig. 4(a)], the offset
voltage is
  
∼ VGS − Vth R D (total W /L)
VOS = + −Vth [26].
2 RD (total W /L)
(1)

Assuming identical load resistors and the same total widths

of input transistors with one composed of N fingers while the
other drawn with a single finger [Fig. 4(b)], the offset voltage
is simplified to

Fig. 1. Power and area of the voltage references in Table I. VOS ∼

= −Vth = Vth,L − Vth,R (2)

where Vth,L and Vth,R are the threshold voltages of M L and

M R . The effect of process skews on the offset voltage can be
the benefits of both BGR and CMOS references. Section II
derived as follows:
introduces the principle of the proposed process compensation
with the dimension-induced side effect. Section III describes (V OS,SS − VOS,FF )
the circuit design. Section IV shows the measurement results, ∼
= (V th,L,SS − Vth,R,SS )−(V th,L,FF − Vth,R,FF )
and Section V concludes this article.
= (V th,L,SS − Vth,L,FF )−(V th,R,SS − Vth,R,FF )
II. R ELATING P ROCESS S KEW TO D ESIGN PARAMETERS = (V th,SS − Vth,FF )|W L − (V th,SS − Vth,FF )|W R (3)
The dependence of Vth on transistor dimension is affected where VOS,SS and VOS,FF represents the offset voltage in slow
by the device-isolation process. There are two representa- and fast corners. Monte Carlo simulations were performed
tive schemes: local oxidation of silicon (LOCOS) isolation with 1000 iterations (Table II). Mismatches were not consid-
and shallow-trench isolation (STI). While LOCOS isolation ered in this simulation. The effect of dimension parameter,
exhibits a gradually grown oxidation, STI drastically defines W2 , on the statistics of the offset voltage increased the spread
device boundaries. Fig. 2 illustrates a cross-sectional view due to the increase in the relative contribution of the fringing
of a MOS transistor along the width direction for the case field as the number of fingers (N) increased (Fig. 5).

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JI et al.: 192-pW VOLTAGE REFERENCE GENERATING BANDGAP– Vth 3283

Fig. 2. Electric field in STI structure when channel is formed for (a) slow, (b) typical, and (c) fast corners.

Fig. 3. Simulation of a threshold voltage as channel width varies. (a) Threshold voltages for each process corners. (b) Difference in the threshold voltages
of slow and fast corners. (c) Width dependence of the threshold voltage as the process skew goes from slow to fast corners.

TABLE II
S IMULATED I NTER -D IE VARIATIONS OF THE O FFSET V OLTAGE
W ITH D IFFERENT U NIT W IDTHS AND F INGERS

velocity saturation. However, the overall trend of the Vth

variation is similar to that of the width.
The proposed compensation scheme is still valid for other
technologies. Fig. 6 shows the simulations of dimension-
induced Vth difference across process corners for 180-, 130-,
and 65-nm CMOS technologies. It should be noted that the
length dependence shows steeper slope around the minimum
Fig. 4. (a) Test differential amplifier with (b) two example designs for input dimension due to the effect of DIBL. It leads to a higher
transistors and (c) resulting offset voltage, where W L and W R are the unit sensitivity to design change, so we considered the width as
width of each finger in M L and M R , respectively.
the design parameter with the length fixed.

Relating the amount of process skew to the design para- III. C IRCUIT D ESCRIPTION
meters can also be applied to the channel length. However, Using the previously mentioned method, the amount of
the length dependence of the Vth is affected by additional process skew can be controlled by the width parameters.
complicated factors including the reverse short channel effect This section describes how to apply the proposed method to
by HALO implant as well as the conventional short channel an actual circuit. The design strategy can be generalized as
effects such as drain-induced barrier lowering (DIBL) and follows.

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3284 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 12, DECEMBER 2019

Fig. 6. Simulated difference in the threshold voltages between slow and

fast corners for different technologies. (a) Width dependence and (b) length
dependence.

Fig. 5. Effect of width (W2 ) and finger (N2 ) on VOS . (a) Distributions of where m 1 , VT , and Vds are the subthreshold slope factor,
the Vth difference from 1000 runs of Monte-Carlo simulations with different the thermal voltage, and drain-to-source voltage, respectively.
fingers (N2 ) and (b) summary of (a) as the process skew goes from slow to
fast corners. The voltage generation part flows this current to a BJT
diode (Q1 ), whereas the compensation part flows it to a PMOS
diode (M2 × N2 ). The Q1 flows current of
1) Investigate the variation in the threshold voltage across  V 
1 5 − VBG V1
the process corners to obtain (Vth,SS − Vth,FF ) as a I = I S e −1 ∼
VT
= bT 2 e VT e VT (5)
function of width [Fig. 3(b)].
2) Obtain the required amount of the process compensation, where I S and b are the saturation current and a proportionality
or Vth change, for the circuit to be designed. factor, respectively [26]. Equating (4) and (5) yields
3) Develop a circuit that contains two widths of transistors,    5

W1 and W2 . Choose the optimal W2 in Fig. 3(b) with a V bT 2
V1 ∼
th1
= VBG − −VT ln . (6)
given large W1 so that the vertical change matches the m1 μCox N1LW 1 (m 1 −1)VT2
required Vth change obtained from step 2.
4) Combine the two circuits into one. The temperature dependence of m is small enough to
be neglected (<0.1%/◦C) [27]. A SPICE simulation using
We propose a process-independent voltage reference by
BSIM4v5 reveals that it is about 0.05%/◦ C with the used
stacking a process-dependent and its compensating parts in
180-nm CMOS technology. Since the mobility is proportional
series. It holds a hybrid architecture of BGR and CMOS
to T −(3)/(2), the overall temperature dependence of the term
reference that generates (VBG − Vth ). The process dependence
in the logarithm follows T 2 . SPICE simulations were also
of the Vth is compensated by the unit width of each finger
performed to quantify how the process variations affected m
while the temperature dependence compensated by the number
and μCox . The σ/μ for m and μCox are about 0.3% and
of fingers. Table III shows two core parts of the proposed
1.4%, respectively. Thus, the total effects of these variations
reference circuit: a voltage generation part and a compensation
on V1 are less than 0.1%, and the process dependence of
part. Zero-bias leakage current of PMOS transistors (M1 ) with
V1 is dominated by Vth1 . Rearranging V1 according to the
N1 fingers provides bias current for both parts, which is
temperature-dependent terms in the logarithm leads to
−Vth1
 −Vds
  
N1 W 1 Vth1
I∼
= μCox (m 1 − 1)VT2 e m 1 VT 1 − e VT (4) V1 ∼
= VBG − − VT ln(αT 2 ) (7)
L m1

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JI et al.: 192-pW VOLTAGE REFERENCE GENERATING BANDGAP– Vth 3285

TABLE III
C ORE B UILDING B LOCKS FOR R EFERENCE G ENERATION AND C ONCEPT OF T HEIR C HARACTERISTICS

where α is a proportionality factor. We can define two do not have identical width. The effect of Vds in (4) can
terms: 1) complementary to faster-skewed process (CTFP) be ignored because Vds for M2 is larger than 5VT in all
and 2) proportional to faster-skewed process (PTFP). The process/voltage/temperature (PVT) conditions. By using the
Vth1 decreases as the process skew goes to faster corner, subthreshold current equation, V2 is derived as follows:
so Vth1 itself is a CTFP voltage. However, due to the minus
sign (−(Vth1 )/(m 1 )), V1 holds a PTFP behavior. For the
temperature dependence, −(Vth1 )/(m 1 ) and −VT ln(αT 2 ) hold    
∼ m2 N1 W1
PTAT and CTAT behaviors, respectively. However, the over- V2 = Vth2 − Vth1 + m 2 VT ln . (9)
m1 N2 W2
all temperature dependence of V1 is CTAT with a reduced
coefficient [28] because the BJT has stronger temperature
dependence. The temperature dependence of V1 can be derived
as follows: There are four design parameters: W1 , W2 , N1 , and N2 . The
∂ V1 ∼ 1 ∂ Vth1 VT process dependence of V2 can be controlled to compensate
=− − (ln(αT 2 )+2). (8) that of V1 by adjusting W1 and W2 . Once W1 and W2 are
∂T m1 ∂ T T
chosen, N1 can be determined to set the leakage current
The value of (∂ V1 )/(∂ T ) varies from −1.05 to −1.11 mV/◦ C. level for bias. Finally, N2 is the factor that changes only the
Since the effect of nonlinearity on the final reference voltage is temperature dependence of V2 . With the given W1 , W2 , and
less than 0.5% in the temperature region of interest, additional N1 , the temperature dependence compensation can be achieved
curvature compensation is not considered in this article. by setting N2 . When the optimal values of W1 , W2 , N1 , and N2
The compensation part (the right side in Table III) has the are found, V1 and V2 operate as in the last row in Table III.
same form as the leakage-based PTAT generator employed The overall circuit is composed of two core building blocks
in [12] and [13]. The previous works used identical unit which are stacked in series to share the bias current while
transistors for pull-up and pull-down transistors to eliminate maintaining their operations (Fig. 7). To avoid an excessive
the effect of the process variation, but (Vth2 − (m 2 )/(m 1 )Vth1 ) size ratio between M1 and M2 for temperature compensation,
is no longer canceled out in this article because the transistors two PMOS diodes (M2 × N2 ) are also stacked in series. The

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3286 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 12, DECEMBER 2019

Fig. 8. Curve fitting by regression function of extracted threshold difference.

TABLE IV
D ESIGN PARAMETERS OF THE P ROPOSED H YBRID R EFERENCE

Fig. 7. Overall circuit schematic of the proposed hybrid reference.

resulting reference voltage can be represented as follows:

VREF ∼
=V1 + 2V2

∼ Vth1
= VBG − − VT ln(αT 2 )
m1
   
m2 N1 W1 0.08466 for A, B, and C, with root-mean-squared error
+2 Vth2 − Vth1 + 2m 2 VT ln . (10)
m1 N2 W2 of 0.1314 and R 2 of 0.9999 (Fig. 8).
Assuming the process variation of VREF is mainly affected by To quantify the effect of process variation of BJT, we sim-
the MOS transistor, it can be obtained as follows: ulated BJT-only load when connected with an ideal cur-
rent source of 200 pA. Monte Carlo simulations with 1000
(VREF,SS − VREF,FF ) iterations show a standard deviation of 1.54 mV. However,
∼ (V1,SS − V1,FF ) + 2(V2,SS − V2,FF )
= technology-dependent characteristics should be considered in
  the sub-nA biasing of the BJT. While the effect of process
∼ 1 + 2m 2
= 2(Vth2,SS − Vth2,FF ) − (Vth1,SS − Vth1,FF ). variation in BJT voltage is only about 1 mV in the 180-nm
m1
CMOS technology [24], [32], a biasing of BJT in pA region
(11)
can cause a standard deviation of more than 5 mV in other
To nullify (11) technology [29].
  The line regulation and power supply rejection ratio (PSRR)
1 + 2m 2
(Vth2,SS − Vth2,FF ) = (Vth1,SS − Vth1,FF ). (12) are the indicators of dc and ac supply sensitivities. To suppress
2m 1 the supply sensitivity, native NMOS transistors (M N1 ) are
Now, ((1 + 2m 2 )/(2m 1 )) is bigger than 1, so W2 should be placed on the top of core circuits [17]. The stacked structure
small enough with a large W1 . If the plot in Fig. 3(b) is of two native NMOS is used to increase the effect of line
modeled as follows: regulation [30]. In the proposed scheme, the native NMOS
B transistors (M N1 ) and the leakage PMOS transistor (M1 )
(Vth,SS − Vth,FF ) ∼
= A+ (13) perform a double regulation, which dramatically amplifies the
W +C
effect of the line regulation without affecting the amount of
then (12) can be rearranged as follows: leakage bias current. M1 sees a low resistance of the common
    
B ∼ 1 + 2m 2 B gate topology formed by M N1 . Therefore, the source node of
A+ = A+ . (14) M1 is effectively isolated from the supply.
W2 + C 2m 1 W1 + C
Since M1 has the biggest size (Table IV), its gate-to-drain
With a large W1 , an iterative fine tuning for W2 can start side gives the dominant parasitic capacitance. The transfer
from function from the supply voltage to the reference voltage is
 
2m 1 B derived as follows:
W2 ∼
= − C. (15)  
2m 2 − 2m 1 + 1 A
gm,2 + R Q1 1 + ωsz
2
VREF ∼ 1
With this model, the curve fitting by MATLAB nonlinear (s) =  (16)
VDD gm,N1 r O,N1 r O,1 1+ s
regression function extracts values of 0.06758, 0.01305, and ωp

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JI et al.: 192-pW VOLTAGE REFERENCE GENERATING BANDGAP– Vth 3287

Fig. 10. Discrepancy between simulation and measurement results of the

proposed reference.

Fig. 9. Chip micrograph.

where gm,N1 , gm,2 , r O,N1 , r O,1 , and R Q1 represent transcon-

ductances of M N1 and M2 , output resistances of M N1 and M1 ,
and equivalent resistance of Q1 , respectively. Their values are
about 4 nS, 3 nS, 20 G, 70 G, and 350 M, respec- Fig. 11. Measured VREF from 45 chips in three extreme-skewed wafers
without trimming.
tively. Equation (16) also indicates that the supply sensitivity
is improved by a factor of the device gain of the native
NMOS transistor (gm,N1 r O,N1 ). The pole and zero in (16)
are estimated as follows: all the measurements. Since the failure of temperature coeffi-
⎧ 1
cient modeling in pA range results in a discrepancy between
⎪
⎨ω z ∼
= simulation and measurement, original design parameters do
C p r O,1 (17) not lead to the optimal results. Fig. 10 compares simulated
⎪ gm,N1
⎩ω p ∼ = and measured VREF when the optimal code extracted from the
Cp
measurement of nine chips is applied. Though the inaccuracy
where C p represents the parasitic capacitance of M1 . The in modeling causes a difference in VREF itself, deviations from
simulation showed that the zero and pole are located around the average hold reasonably matched characteristics. Monte
7 Hz and 1.8 kHz, respectively. Carlo simulations with the original design parameters show
that VREF at room temperature has a standard deviation of
IV. M EASUREMENT R ESULTS about 0.7% while the measurement with three different wafers
The proposed circuit was fabricated with a standard shows a standard deviation of 0.53%. Simulated σ/μ is about
0.18-μm CMOS technology on three different wafers of 0.2% for each of SS, TT, and FF corners. Measured intra-die
process corners (SS, TT, and FF). Fig. 9 shows the chip variations show σ/μ of 0.38%, 0.21%, and 0.22%, for SS, TT,
micrograph. This article is based on the assumption that the and FF corners, respectively.
effect of process variations has well-defined statistics once the The effect of oxide thickness change (tOX ) on the thresh-
technology of interest is given. The statistics of the process old voltage can be expressed as follows:
variations should be included in the SPICE model parameters. tOX  tOX
Though the SPICE model has extracted sets of numerical Vth = 4εsi q N A ψ B = ψOX (18)
εOX tOX
coefficients and skew parameters that can represent the temper-
ature and process variations, commercially available models where ψ B is the difference between the Fermi potential and
now do not guarantee to precisely cover the extreme range of the intrinsic potential, ψOX is the potential drop across the
pA-leakage level. Therefore, we implemented programmabil- oxide, tOX is the oxide thickness, N A is the channel doping
ity in transistor size for M1 and M2 (Fig. 7) in the chip. While concentration, and εOX and εsi are the permittivities of the
the widths of unit transistors for M1 and M2 (W1 and W2 ) were oxide and the silicon [31]. According to the manufacturer’s
fixed, the multiplier numbers (N1 and N2 ) were designed to data, oxide thickness varies ±2.5% across the extreme process
be a variable, which can be controlled with a binary-weighted corners. Considering the proposed hybrid scheme generates
4 bits. To find the optimal codes for sizing, we tested nine VREF level of VBG (∼1.2 V) − Vth (∼0.5 V), the contribution
chips of a typical wafer, then we applied these codes to all of Vth to the final output is about 70%. Therefore, the effect
the chips; it is defined as “untrimmed” and is fixed throughout of oxide thickness on VREF would be less than ±2%.

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3288 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 12, DECEMBER 2019

Fig. 15. Measured 99% settling time after the start-up as temperature varies.

Fig. 12. Fig. 12. Measured statistics of each process corners at 30 ◦ C.

(a) VREF and (b) temperature coefficient of VREF .

Fig. 16. Measured line sensitivity.

Fig. 13. Measured VREF at different VDD .

Fig. 17. Simulated and measured PSRR without load capacitor.

wafers was 0.53%. The average level of the reference voltage

is 0.6926 V, which is approximately (VBG − Vth ) in the given
technology. The average temperature coefficients without trim-
ming were 33 ppm/◦C, 35 ppm/◦C, and 32 ppm/◦ C in typical,
slow, and fast corners, respectively. Standard deviations of the
temperature coefficient at typical, slow, and fast corners were
7.0%, 18%, and 9.7%, respectively. The average temperature
coefficient for all 45 chips was 33 ppm/◦ C. Fig. 13 shows the
measured temperature dependence in different supply voltages.
VREF started to be fully regulated from 1 V. Fig. 14 shows
the measured current consumption at different supply voltage
Fig. 14. Measured current consumption when supply voltage and temperature and temperature conditions. It consumed 192 pW at room
change. temperature. Current consumption strongly depended on tem-
perature and was almost unaffected by the supply voltage.
The 15 chips were measured from each corner (Fig. 11). The start-up time to reach within 1% of the final value was
Fig. 12 shows the distributions of the reference output and tem- measured at different temperatures (Fig. 15). Measured line
perature coefficient for each process corner at 30 ◦ C. Standard sensitivity was 0.020%/V at the supply voltage above 1.0 V
deviations of VREF at typical, slow, and fast corners are 0.21%, (Fig. 16). Measured PSRR was −55 dB at 100 Hz without
0.38%, and 0.22%, respectively. Standard deviation among using any capacitor (Fig. 17). To protect the leakage-biased

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JI et al.: 192-pW VOLTAGE REFERENCE GENERATING BANDGAP– Vth 3289

TABLE V
P ERFORMANCE S UMMARY AND C OMPARISON

without using any capacitor (Fig. 18). It can be improved

at the cost of increasing power consumption or increasing
area. Table V shows the comparison of performance with
the previously reported low-power voltage reference circuits.
The proposed circuit achieves process variation of only 0.53%
across the whole process skews and achieves power consump-
tion and area compared with those of the group of the CMOS
references [16]–[18], [20].

V. C ONCLUSION
This article proposes a process/temperature-compensated
Fig. 18. Measured noise spectrum (with no-load capacitance). voltage reference circuit with a hybrid architecture of BGR
and CMOS references, which generates a nominal voltage
level of (VBG − Vth ). Vth is affected by so many technology-
internal circuit in the measurement of the output voltage, induced factors, but the major effect is originated from a
a unity-gain configured two-stage amplifier is integrated in the consequence of a change in doping concentration. However,
chip. The amplifier output is monitored. The limited bandwidth once the technology of interest for circuit design is given,
due to the monitoring circuit affects PSRR measurement the variations by the skew would have an average with a
at frequencies above kHz. To obtain a credible result that limited range of variation. The statistics are even clearly
excludes the effect of the output buffer amplifier, we measured defined in matured process for mass production. The proposed
the PSRR only up to 1 kHz. The measured noise spectrum of design methodology matches the amount of variation range
VREF showed integrated noise of 26.8 μV from 0.1 to 10 Hz with the dimension dependence of the Vth variation change.

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3290 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 12, DECEMBER 2019

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JI et al.: 192-pW VOLTAGE REFERENCE GENERATING BANDGAP– Vth 3291

Byungsub Kim (M’11–SM’16) received the B.S. Jae-Yoon Sim (M’02–SM’13) received the B.S.,
degree in electronic and electrical engineering from M.S., and Ph.D. degrees in electronic and electrical
the Pohang University of Science and Technology engineering from the Pohang University of Science
(POSTECH), Pohang, South Korea, in 2000, and and Technology (POSTECH), Pohang, South Korea,
the M.S. and Ph.D. degrees in electrical engineering in 1993, 1995, and 1999, respectively.
and computer science from the Massachusetts Insti- From 1999 to 2005, he was a Senior Engineer with
tute of Technology (MIT), Cambridge, MA, USA, Samsung Electronics, Suwon, South Korea. From
in 2004 and 2010, respectively. 2003 to 2005, he was a Post-Doctoral Researcher
From 2010 to 2011, he was an Analog Design with the University of Southern California, Los
Engineer with Intel Corporation, Hillsboro, OR, Angeles, CA, USA. From 2011 to 2012, he was a
USA. In 2012, he joined the Department of Elec- Visiting Scholar with the University of Michigan,
tronic and Electrical Engineering, POSTECH, as a Faculty Member, where Ann Arbor, MI, USA. In 2005, he joined POSTECH, where he is currently
he is currently an Assistant Professor. a Professor. From 2017 to 2019, he was the Director of the Joint Research
Dr. Kim was a recipient of the MIT EECS Jin-Au Kong Outstanding Lab, which is nominated by the Korea Institute of Science and Technology,
Doctoral Thesis Honorable Mentions in 2011, the IEEE J OURNAL OF Seoul, South Korea. Since 2019, he has been the Director of the Scalable
S OLID -S TATE C IRCUITS Best Paper Award in 2009, and the Analog Device Quantum Computer Technology Platform Center, Pohang, which is an Engi-
Inc. Outstanding Student Designer Award from MIT in 2009. He was a neering Research Center nominated by the Korea Ministry of Science and
co-recipient of the Beatrice Winner Award for Editorial Excellence at the Information and Communication Technology (ICT), Sejong, South Korea. His
2009 IEEE International Solid-State Circuits Conference (ISSCC). research interests include sensor interface circuits, high-speed serial/parallel
links, phase-locked loops (PLLs), data converters, power module for plasma
generation, and quantum computing.
Dr. Sim was a recipient of the Special Author-Recognition Award at ISSCC
2013 and was a co-recipient of the Takuo Sugano Award at ISSCC 2001. He is
Hong-June Park (M’88–SM’13) received the B.S. an IEEE Distinguished Lecturer. He has served on the technical program com-
degree from the Department of Electronic Engineer- mittees for the IEEE International Solid-State Circuits Conference (ISSCC),
ing, Seoul National University, Seoul, South Korea, Symposium on VLSI Circuits, and Asian Solid-State Circuits Conference.
in 1979, the M.S. degree from the Korea Advanced
Institute of Science and Technology, Daejeon, South
Korea, in 1981, and the Ph.D. degree from the
Department of Electrical Engineering and Com-
puter Sciences, University of California at Berkeley,
Berkeley, CA, USA, in 1989.
He was a CAD Engineer with ETRI, Daejeon,
from 1981 to 1984, and a Senior Engineer with the
TCAD Department, Intel Corporation, Santa Clara, CA, USA, from 1989 to
1991. In 1991, he joined the Faculty of Electronic and Electrical Engineering,
Pohang University of Science and Technology (POSTECH), Pohang, South
Korea, where he is currently a Professor. His research interests include CMOS
analog circuit design such as high-speed interface circuits, readout integrated
circuit (ROIC) of touch sensors, and analog/digital beamformer circuits for
ultrasound medical imaging.
Dr. Park is a member of IEEK. He was a recipient of the 2012 Haedong
Academic Award from IEEK and Haedong Foundation. He served as the
Editor-in-Chief for the Journal of Semiconductor Technology and Science and
the SCIE Journal from 2009 to 2012, the Vice-President of IEEK in 2012,
and a Technical Program Committee Member of ISSCC, SOVC, and A-SSCC
for several years.

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