Scribd
Upload
16 views2 pages

Co Ass

Assignment

Uploaded by

shivam agrawal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
16 views2 pages

Co Ass

Assignment

Uploaded by

shivam agrawal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

GLA University, Mathura

Department of Computer Engineering and Applications

Assignment

Subject: Computer Organization


Subject Code: BCSC1005
Submission deadline: 25 November, 2024

1. Show the execution of complete instruction for the instruction given below

(i) ADD R1, R3 where contents of Register R1 and R3 are added and result is
stored in R3

(ii) LOAD a memory word to accumulator

2. Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average
cycles per instruction of 4. The same processor is upgraded to a pipelined processor
with five stages but due to the internal pipeline delay, the clock speed is reduced to
2 gigahertz. Assume there are no stalls in the pipeline. Determine the speed up
achieved in this pipelined processor.

3. What do you mean by pipeline processing? In a certain scientific computation, it is


necessary to perform the arithmetic operation Ai * Bi * (Ci * Di) with a stream of
numbers. Specify a pipeline configuration to carry out this task. List the content of
all registers for i = 1 to 6.

4. What do you mean by high-impedance state of buses? A computer uses RAM chips
of 1024 × 1 capacity. How many chips are needed to provide a memory capacity of
1024 bytes? How many addresses line are required to access 2048 bytes of memory?

5. A computer uses a memory unit with 256 K words of 32 bits each. A binary
instruction code is stored in one word of memory. The instruction has four parts: an
indirect bit, an operation code, a register code part to specify one of 64 registers,
and an address part.
(a) How many bits are there in the operation code, the register code part, and the
address part?
(b) Draw the instruction word format and indicate the number of bits in each part.
(c) How many bits are there in the data and address inputs of the memory.

6. What do you mean by cache memory? Discuss its different types. Differentiate
write through and write back with respect to cache memory.
7. What do you mean by interrupt? Discuss different types of interrupts in detail.

8. What is DMA controller? Explain in detail the Direct memory Access (DMA)
transfer in a computer system by giving appropriate figure.

9. What do you mean by virtual memory? How it is useful for executing any program.
A virtual memory system has an address space of 8K words, a memory space of 4K
words, and page and block size of 1K words. The following page reference changes
occur during a given time interval.

5 1 3 2 3 7 5 2 1 2 3 1 4 8 6

Determine the four pages that are resident in main memory after each page reference
change if the replacement algorithm used is FIFO and LRU and Optimal page
replacement

10. Consider a 32-bit microprocessor that has an on-chip 16 KB four way set associative
cache. Assume that the cache has a line size of four 32-bit words. Draw a block
diagram of this cache showing its organization and how the different address fields
are used to determine a cache hit/miss. Where in the cache is the word from memory
location ABCDE8F8 mapped?

11. A computer system has a 4K word cache organized in block associative manner
with 4 blocks per set, 64 words per block. The main memory consists of 65536
blocks. How many bits are there in each of the TAG, SET and WORD fields?

You might also like